JPH0560261B2 - - Google Patents

Description

[Detailed Description of the Invention] <Technical Field> The present invention relates to an LSI pad layout method, and particularly to an LSI pad layout method using a computer.
This relates to the method of arranging the pads located around the chip in the design of the chip.

<Prior Art> Conventionally used LSI layout design methods include a manual layout method using manual design and an automatic layout method using a computer.

In recent years, design rules for LSI have been reduced,
The number of elements built into one chip is increasing, and it is becoming difficult to design them manually in order to shorten the development period. Against this background, various methods for automating layout have been developed to date, such as the polycell method, which consists only of cells of the same height, and the building block method, which allows layouts to be arranged in any shape. Representative.

In general, a square or rectangular LSI chip has a functional block part consisting of logic gates, flip-flops, etc. arranged inside the chip, and pads that serve as external terminals and interfaces between the pads and the above-mentioned functional blocks are arranged around the chip. A buffer will be placed. When an automatic layout method is used to layout an LSI having such characteristics, the placement and wiring methods are different between the chip peripheral area where pads are placed and the other internal areas.
Therefore, in the conventional layout method, the internal layout and wiring of the chip are first performed, and the pads are placed around the periphery while taking into account the shape obtained through this process, and the internal functional blocks and A layout method is adopted in which wiring connections are made between the two.

In order to automate placement and wiring at
Logical connection information is necessary to determine the relationship between the functional blocks that make up the LSI. However, the logical connection information for placement and wiring generally does not include information on where the cell should be placed on the layout. Therefore, when placing and wiring from the internal part, consider the connection relationship with the pad and determine where the pad and the internal part should be connected to each other, that is, the wiring outlet of the internal part. must be defined.

The figure schematically shows the chip layout, in which a logic function block 3 is arranged in the internal part 2 of the chip 1, a pad 5 is arranged in the peripheral part 4 of the chip,
In order to connect the pad 5 with the inner part 2, an outlet 6 is defined as a virtual terminal. This kind of definition of the wiring outlet 6 is normally carried out at the stage of layout, but since it is done manually while taking into consideration the internal parts for which the layout has been determined, the layout work is temporarily switched to manual work. However, there was a problem in that a completely automatic layout could not be implemented and the advantages of computers could not be effectively utilized.

<Object of the Invention> The present invention was made in view of the problems of the conventional automatic layout method, particularly in the pad placement method, and provides an LSI pad placement that can completely automate everything from logic input to layout during LSI design. provide a method.

<Embodiment> In the layout design of an LSI, the circuits built into a chip are divided into functional blocks, and the positions occupied within the chip and the wiring between them are determined with each functional block as a unit. The divided functional blocks are interconnected and wired based on the connection terminals each functional block has. In order to set such wiring and arrangement, logical connection information is required, and this is shown using a logic circuit diagram. In this embodiment, in the process of expressing logical connection information using a logic circuit diagram, layout information regarding pads to be placed around the chip and buffers that serve as interfaces between the pads and the logic circuit is also included in the logic circuit diagram. Draw and form. That is, for example, the following layout information regarding pads and buffers is included.

1. Where should the chips be placed on the top, bottom, left and right sides? 2. In what order should they be placed on each side? 3. How far should the pads be spaced?

Based on the logic circuit diagram drawn including the above pad and buffer layout information, the layout of functional blocks, buffers, and pads within the chip is determined to minimize the chip size and enable efficient interconnection. be done.

By creating a logic circuit diagram that includes layout information regarding the pads and buffers mentioned above, pad placement can be performed first, and then It becomes possible to layout internal parts so that wiring relationships are optimized, and at the same time, it becomes unnecessary to input information defining virtual terminals, which was required immediately before layout.

<Effects> According to the present invention, information on the placement of pads and buffers on the layout is included in the logic circuit diagram created during the LSI layout design process, thereby making it possible to perform automatic layout using a computer. It is also possible to fully automate everything from logic input to layout.

[Brief explanation of the drawing]

The figure is a diagram for explaining a conventional LSI layout method. 1... Chip, 2... Internal part, 3... Function block, 4... Peripheral part, 5... Pad.

Claims (1)

[Claims] 1. In a method of determining the LSI layout by placing the functional block in the center of the chip and the pads and buffers in the periphery of the chip, the layout information of the pads and buffers mentioned above is added to the logic circuit diagram, which is the connection information between the functional blocks. 1. A method for arranging pads for an LSI, characterized in that the layout of functional blocks, pads, and buffers is determined based on the logic circuit diagram.