JPH0560266B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to semiconductor devices, and in particular to an insulated gate field transistor (FIELD) suitable for very small integrated circuits having very high speed and very low power performance. Regarding MOSFET).

[Background of the invention]

FIG. 1 shows the cross-sectional structure of a conventional MOSFET. Conventional n-channel MOSFET is p
It has a structure in which source and drain n-type diffusion regions 12 and 13 are formed in a type substrate 11, and a gate electrode 14 is formed on a gate oxide film 15. In addition,
Reference numeral 16 denotes a selectively formed silicon oxide film for element isolation. Conventional MOSFET shown in Figure 1
Because the current conduction path between the source and drain was provided on the horizontal surface of the substrate, it had the following drawbacks.

(1) The source and drain electrodes must be taken out through holes (contact holes) smaller than the source and drain diffusion regions 12 and 13. Therefore, the source/drain diffusion region is at least larger than the contact hole, and the parasitic capacitance between this diffusion region and the substrate 11 cannot be ignored. The charging and discharging time of this parasitic capacitance slows down the switching operation of the device.

(2) The gate capacitance and electron transit time, which determine the operating speed of the device, are proportional to the gate length. Therefore, it is necessary to shorten the gate length for high-speed operation. Since the gate length is determined by lithography, it is difficult to shorten it.

(3) In order to quickly charge and discharge the load capacitance in the next stage, it is necessary to increase the gate width and increase the mutual conductance. This results in an increase in the area of the device in proportion to the gate width.

(4) Since the current conduction path is on the substrate surface, it is susceptible to the effects of radiation such as alpha rays. This reduces the reliability of a circuit using the same element.

[Purpose of the invention]

An object of the present invention is to gradually eliminate the above-mentioned problems and provide a semiconductor device with high density, high speed, and low power consumption.

[Summary of the invention]

In order to achieve the above object, the present invention has a structure in which a current conduction path between a source and a drain is provided on a substantially vertical side wall formed in a single crystal semiconductor substrate. The current flowing through the current conductive path is controlled by a voltage applied to a polycrystalline silicon layer provided through a thin oxide. This polycrystalline silicon layer is insulated from the semiconductor substrate by a thick oxide film.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 shows a first embodiment of the present invention.
FIG. 3 shows a plan view of the MOSFET, and FIG. 3 shows a structural cross-sectional view taken along the line -' in FIG.
In FIG. 3, reference numeral 23 denotes a highly doped n-type drain diffusion layer provided on the surface of the p-type substrate 21. The p-type region 211 and the heavily doped n-type regions 22 and 28 are formed by sequentially adding impurities to the n-type epitaxial layer 210 on the substrate, and in particular, 22 represents a source diffusion layer. A silicon oxide film 25 and a gate electrode 24 are provided in contact with the substantially vertical sidewalls of the p-type region 211. The gate electrode 24 is insulated from the substrate 21 and the heavily doped n-type diffusion layer region 23 by silicon oxide films 26 and 27.

FIG. 4 shows the manufacturing process of the first semiconductor device of the present invention, and shows the state before the cross-sectional structure shown in FIG. 3 is formed. The manufacturing process will be explained below using the drawing numbers.

FIG. 4a: Impurities are selectively added to the surface of the p-type silicon substrate 21 to form a high concentration n-type layer region 23. FIG. Thereafter, an n-type epitaxial layer 210 is grown on the entire surface of the substrate, and a silicon oxide film 4 is grown.
1. Deposit a silicon nitride film 42 and a silicon oxide film 43 to form a three-layer film 41, 42, 43.
selectively etching and removing predetermined portions of the material into a predetermined shape.

FIG. 4b: Using the three-layer films 41 to 43 as a mask, the epitaxial layer 210 is selectively etched almost vertically. Thereafter, a silicon oxide film 25 is formed on the entire surface by thermal oxidation.

FIG. 4c: A silicon nitride film is deposited on the entire surface, and dry etching is performed to remove the silicon nitride film on the horizontal surface portions, leaving the silicon nitride film 44 only on the side surfaces of the protruding portions. Thereafter, a silicon oxide film 27 is formed by thermal oxidation using the silicon nitride film 44 as a mask.

FIG. 4d: After removing the silicon nitride film 44, polycrystalline silicon 24 is deposited on the entire surface.

FIG. 4e: After removing the polycrystalline silicon on the silicon single crystal convex portion, a silicon nitride film is deposited on the entire surface and patterned to leave a portion 45 of the silicon nitride film. After that, silicon nitride film 4
5 as a mask, a portion of the polycrystalline silicon 24 is thermally oxidized to form a silicon oxide film 26.

FIG. 4f: After adding impurities to the region from which the drain electrode is taken out to form a heavily doped n-type region 28, the silicon nitride film 45 and silicon oxide film 43 are removed. Thereafter, the surface of the polycrystalline silicon 24 is oxidized using the silicon nitride film 42 as a mask. After this, p-type impurities and n-type impurities are sequentially added to the surface to form a p-type region 211 and a high concentration n-type region 22, and a gate contact hole 29 and aluminum electrode wiring are formed, as shown in FIG. A semiconductor device having the cross-sectional structure shown is obtained.

FIG. 5 shows a second embodiment of the present invention.
FIG. 6 is a plan view of the MOSFET type semiconductor device, and FIG. 6 is a structural sectional view taken along the line V-V' in FIG. In this example, the epitaxial layer 210
A gate oxide film 25 is formed on a side surface of a portion of the same layer 210, and a polycrystalline silicon layer 2 is formed on a side surface of another portion of the same layer 210.
4b is directly connected. This is achieved by selectively etching a part of the oxide film 25 by patterning after removing the silicon nitride film 44, as shown in FIG. Realized. In FIGS. 5 and 6, 51 is a polycrystalline silicon 24
The p-type impurity contained in the epitaxial layer 2
This is a p-type region formed by diffusion into 10. P-type region 211 is electrically connected to p-type region 51 and connected to an aluminum electrode through polycrystalline silicon layer 24b and contact hole 29b, and by applying a voltage thereto,
The threshold voltage of the MOSFET can be controlled.

FIG. 7 shows a third embodiment of the present invention.
This shows the cross-sectional structure of a MOSFET. In this example, an n-type epitaxial layer 210 is in contact with a p-type substrate 21. Further, in the structural process diagram of FIG. 4b, p-type impurities are added to the entire surface, thereby forming the p-type region 71 of FIG. 7. p-type region 21
1 passes through the p-type substrate 21 through the p-type regions 51 and 71.
By applying a voltage to the substrate, the thread-to-shoulder voltage of the MOSFET can be controlled. In this example, the p-type region 21
Since the wiring for the voltage applied to 1 is done by the substrate, there is an advantage that the device area is smaller than the devices shown in FIGS. 5 and 6. In addition, in FIG. 7, 24b and 5
1 is not necessary. However, in that case, p-type regions 71 and 211 must be connected.

In each of Examples 1 to 3 above, the insulator may be formed by thermal oxidation of silicon, or an insulating resin or the like may be used in addition to a silicon nitride film.
Furthermore, the conductivity types of p-type and n-type can be reversed. Furthermore, the source and drain can also be used in reverse. The device of the present invention can also be realized using other semiconductors such as GaAs as the semiconductor.

〔Effect of the invention〕

According to the present invention, the current conduction path between the source and drain of the MOSFET is formed on the almost vertical side of the substrate surface, so the gate length is short and the gate width is large.
MOSFETs can be integrated in high density. Additionally, because parasitic capacitance is reduced, high-speed, low-power MOSFETs can be realized. Furthermore, the probability that radiation such as α-rays will irradiate the source-drain current conduction path is reduced, making it possible to realize a MOSFET that is resistant to α-rays.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional structure diagram of a conventional MOSFET, Figure 2
The figure is a plan view of a MOSFET as an embodiment of the present invention, FIG. 3 is a cross-sectional structural diagram taken along the line -' in FIG. 5 is a plan view of a MOSFET as another embodiment of the present invention, FIG. 6 is a cross-sectional structural diagram taken along the line V-V' in FIG. 5, and FIG. 7 is a plan view of a MOSFET as another embodiment of the present invention. A cross-sectional structure diagram of a MOSFET as an example. 21...p-type substrate, 23...high concentration n-type region,
210...n-type epitaxial region, 211...
P-type region, 22, 28...high concentration n-type region, 25
...Gate oxide film, 26, 27...Silicon oxide film, 24...Polycrystalline silicon, 29...Gate
Conductive hole, 51... p-type region, 71... p-type region.

Claims (1)

[Claims] 1 a semiconductor substrate having a first conductivity type; a first semiconductor region formed on the main surface of the semiconductor substrate and having a second conductivity type opposite to the first conductivity type and having a predetermined shape; , a second semiconductor region having the first conductivity type formed in contact with an upper surface of the first semiconductor region; and a second conductivity type formed within the surface region of the second semiconductor region. 3rd having
a first insulating film formed on the main surface of the semiconductor substrate and in contact with a side of the first semiconductor region; and a first insulating film formed on one side of the second semiconductor film. a low-resistance gate electrode formed on the first insulating film in contact with the gate insulating film; and a low-resistance gate electrode formed on the second semiconductor film on a side opposite to the one side. a fourth semiconductor film having the first conductivity type formed; a low resistance polycrystalline silicon film formed on the first insulating film in contact with the fourth semiconductor film; in contact with the lower end of the semiconductor film and the main surface of the semiconductor substrate,
A semiconductor device comprising: a fifth semiconductor film having the first conductivity type formed on one side of the first semiconductor film.