JPH0561566B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a signal display device that stores input signals in a storage circuit, reads out the stored input signals, and displays them on a display.

[Prior Art] A signal display device such as a transient digitizer is a device used for, for example, digitizing an analog signal waveform and processing it with a computer, or converting it back to an analog signal and observing it on a display. It is indispensable for observing and analyzing high-speed transient phenomena and mechanical vibrations.

The operation of such a conventional device is performed as follows. In the write mode, input signals are analog-to-digital converted and sequentially stored in a storage circuit (for example, a random access memory RAM), and in the read mode, the digital signals stored in this RAM are sequentially read out. This read signal is converted back into an analog signal and displayed on a display. This is the same even when the input signal is a logic signal, except for analog-to-digital conversion and digital-to-analog conversion.

[Problems to be Solved by the Invention] In a conventional signal display device, when input signals of a plurality of channels are stored and these stored input signals are displayed on a display, the display position of the input signal for each channel is Control was possible only in the amplitude axis direction (Y direction). However, the display position in the time axis direction (X direction) could not be controlled unless all channels were displayed simultaneously. Therefore, it is inconvenient to compare temporally different input signal portions of different channels.

Therefore, an object of the present invention is to provide a signal display device that can independently control the display position of input signals of a plurality of channels in the time axis direction for each channel.

[Means for Solving the Problems] The present invention provides a memory circuit that stores input signals of a plurality of channels, a counter that generates an address signal for the memory circuit, and a display that displays the input signals stored in the memory circuit. A signal display device comprising a plurality of bias latch circuits provided for each of the plurality of channels, a changing means for changing the memory contents of the bias latch circuit, and a counter. It further includes an adder circuit that adds the address signal and the contents stored in the bias latch circuit.

[Operation] The signal display device of the present invention addresses a storage circuit using the output signal of the adder circuit, reads out input signals stored in the storage circuit, and displays these read input signals on the display. Then, the storage contents of the plurality of bias latch circuits are changed by the changing means, and the display position of the input signal displayed on the display in the time axis direction is controlled for each channel.

[Example] FIG. 1 is a block diagram showing an example of the present invention.
FIG. 2 is a block diagram showing a part of FIG. 1 in detail. FIG. 1 shows a case where signal waveforms of two channels are observed, CH1 and CH2 are input terminals of the first channel and the second channel, respectively. 1 is an input circuit including a buffer and attenuator, 2 is an analog/digital (A/D)
Converter, 3 is a selection storage circuit having a selector, RAM, etc., 4 is an output circuit having a digital-to-analog converter, an output amplifier, etc., 5 is an output terminal, and 6 is a display connected to the output terminal 5. 7 is a trigger circuit that generates a trigger signal in response to an input signal; 8 is an address control circuit that specifies the address of the RAM of the selective storage circuit 3 mainly during writing and reading; 9 is a trigger circuit that generates a trigger signal in response to an input signal; Central processing unit (hereinafter referred to as "CPU"), 10 is CPU9
11 is a RAM of the CPU; 12 is a keyboard (changing means) for issuing various commands; 13 is a read-only memory (ROM) that stores processing procedures;
This is a clock generator that supplies clock signals to each circuit. 14 is a bus (bus line), and the part without an arrow indicates that it is bidirectional. Through these buses, the CPU 9 controls the clock frequency of the clock generator 13, controls the channel selection of the selector of the selective storage circuit 3, processes (for example, erases) data in the RAM of the selective storage circuit 3, and controls the trigger circuit. Trigger level and slope control for 7 is performed. In addition,
Reference numeral 81 indicates a read/write control line, and 82 indicates an address designation line.

FIG. 2 shows the address control circuit 8 in FIG.
FIG. In the figure, bias latch circuits 15 and 16 store the RAM address of the selective storage circuit 3 related to when writing is stopped; 15 is for the first channel, 16 is for the first channel;
is for the second channel. Furthermore, the stored contents of the bias latch circuits 15 and 16 can be changed arbitrarily using the keyboard 13. The read counter 17 selects the selected memory circuit 3 in the read mode.
The write counter 18 serves as a reference for the RAM address of the selected memory circuit 3 in the write mode.
This determines the RAM address. The port 22 is an interface to the CPU 9, and the delay counter 25 is used to delay the trigger for a predetermined period of time as necessary, and is used when it is desired to store the input signal in the RAM after the trigger occurs. The multiplexer 19 connects the bias latch circuits 15 and 1 for each cycle of the count of the read counter 17.
6 outputs are selected alternately. Adder circuit 20 algebraically adds the address of bias latch circuit 15 or 16 selected by multiplexer 19 with the address from the read counter. The multiplexer 21 controls the write counter 18 in response to the output of the control circuit 26 which is responsive to the output of the delay counter 25.
Or select the output of the adder circuit 20. Control circuit 2
3 is for triggering and enabling the AND gate 24 in response to a carry signal of the write counter 18, which will be described later, and the output of the port 22.

Next, the operation of the embodiment shown in FIGS. 1 and 2 will be explained. Assuming that the device is now in the read mode, the multiplexer 19 switches the bias latch circuit 15 in response to the operation of the read counter 17.
and 16 alternately, multiplexer 21
selects the adder circuit 20. According to the output of this multiplexer 21, the RAM of the selective storage circuit 3
The address is selected and the data stored in this RAM is read out. The operation in this read mode will be described in detail later. During this time, the control circuit 23
AND gate 24 is prohibited.

When you operate the reset/start key on the keyboard 12, the CPU 9 detects this and starts the ROM 10.
Each circuit is controlled as follows according to the processing procedure stored in the controller. First, the CPU 9 connects the selector of the selection storage circuit 3 to the ground potential via the bus 14.
It commands the data input terminals of the RAM to be applied and, via bus 14, commands control circuit 26 to generate a write mode signal on signal line 81. This write mode signal causes the RAM of the selective storage circuit 3 to change from the read mode to the write mode, and the multiplexer 21 selects the write counter 18. Further, the CPU 9 supplies a start signal to the write counter 18 via the bus 14 and the port 22.
starts counting the clock signals and supplies the output signal as an address signal to the RA of the selective storage circuit 3 via the multiplexer 21. Now, this
Write logic “0” (installation level) to RAM. Since the maximum count value of the write counter 18 and the storage capacity of the RAM are equal, when logic "0" is written to all storage elements of the RAM, erasure of the old signal (first data) stored in the RAM is completed. Then, the write counter 18 generates the first carry signal. Note that when erasing the RAM of the circuit 3, a logic "1" may be written instead of a logic "0". Alternatively, the address signal and data may be sent directly from the CPU 9 to the RAM to erase the RAM, and in this case, the write counter 18 is not used.

The first carry signal from the write counter 18 is sent to the CPU 9 via the port 22 and the bus 14.
sent to. When the CPU 9 detects this carry signal, the selector of the selection storage circuit 3 outputs the output of the analog-to-digital converter 2 via the bus 14.
bus 1 as well as commands to supply RAM.
A second start signal, ie, a first control signal, is supplied to the write counter 18 via the port 22 and the second start signal. Therefore, the RAM of the circuit 3 writes the digitized input signal, that is, the second data, in response to the address signal of the write counter 18 from the multiplexer 21. During this time, the AND gate 24 is prohibited by the control circuit 23, as in the read mode and the erase mode.

When the second data is written to the RAM of the circuit 3 for one cycle, the write counter 18 generates a 12th carry signal, which is sent to the port 22 and the bus 14.
Send it to CPU9 via. The CPU 9 determines that this carry signal is the second time, and instructs the control circuit 23 via the bus 14 and port 22 to trigger enable the AND gate 24. When the AND gate 24 is set to trigger enable, the trigger signal generated by the trigger circuit 7 is always supplied to the delay counter 25. In addition, the CPU 9 sends the start signal to the bus 14 and port 2 again in response to the second carry signal.
2 to the write counter 18, and the RAM of the selective storage circuit 3 is successively rewritten with new second data. This operation is repeated until the trigger circuit 7 generates a trigger signal. The write counter 18 and control circuit 23 described above may be controlled by hard logic instead of by the CPU 9. Hard logic has the advantage of being able to process faster than a CPU.

When a trigger signal is generated after trigger enable, this trigger signal is provided to delay counter 25 through AND gate 24 . The delay counter 25 is controlled by the CPU 9 and the bus 14 according to the setting on the keyboard 12, and after the output of the AND gate 24 is generated, the delay counter 25 counts the clock pulses up to the set value and outputs the delay signal as the second control signal. Generate a trigger signal. In the pre-trigger mode, in which a signal before the trigger signal is generated, the set value of the delay counter 25 is set to zero, so that the delay counter 25 generates the trigger signal immediately after the trigger circuit 7 generates the trigger signal. In modes other than the pre-trigger mode, as described above, the set value of the delay counter 25 is set to a value other than zero, and depending on this set value, the preceding and following trigger signals from the trigger circuit 7 can be arbitrarily stored in the RAM. In either case,
Note that in this embodiment, the output signal of the delay counter 25, rather than the trigger signal from the trigger circuit 7, becomes the second control signal.

The delay trigger signal (second control signal) of the delay counter 25 is supplied to the write counter 18 as a stop signal, causing the write counter 18 to stop counting. Since the bias latch circuits 15 and 16 are supplied with the address signal of the write counter 18 and the output of the delay counter 25, the address signal of the write counter 18 when the output of the delay counter 25 occurs, that is, the selection storage circuit. 3
Stores the final write address of RAM. Further, the delay trigger signal of the delay counter 25 is also supplied to the control circuit 21, the signal line 81 changes from the write mode to the read mode, the RAM of the circuit 3 changes to the read mode, and the multiplexer 21 selects the adder circuit 20. . Further, the read counter 17 starts counting the clock signals, supplies the address signal to the adder circuit 20, and supplies the carry signal to the multiplexer 19, so that the bias latch circuits 15 and 16 are alternately activated each time a carry signal is generated. select. This means that the RAM of circuit 3 has 2
This is because although the channel signals are stored, since the output circuit 4 has only one digital-to-analog converter, the first and second channels must be read out alternately. Therefore, if only the first channel signal is stored, the multiplexer 19 should always select the bias latch circuit 15.

On the other hand, the final address stored in bias latch circuits 15 and 16 is transmitted via bus 14.
It is stored in RAM 11 of the CPU, algebraically incremented by 1 by CPU 9, and stored again in bias latch circuits 15 and 16 via bus 14. The newly stored address becomes the starting address for RAM writing. However, the write counter 18 stops counting at the next clock signal supplied with the stop signal, and the bias latch circuit 1
If 5 and 16 memorize the address at this time,
Addition of +1 by the CPU becomes unnecessary. The adder circuit 20 uses this start address and the read counter 17.
Since the address signals are added logarithmically, the output of the adder circuit 20 becomes the write start address of the RAM when the address signal of the read counter 17 is zero. In this way, the address of the RAM of the circuit 3 is selected according to the output of the adder circuit 2, and the read mode is set. Note that when the address signal of the read counter 17 is zero, the horizontal display position of the display 6 is at the left end.

In this way, before the trigger signal is generated (delay counter 2
5) is displayed on the display 6, but the displayed content is always a new one even if a trigger signal is generated and writing is stopped within one cycle after trigger enable. 2 data, and will not be mixed with old 1st data. In some cases, the erase mode in the above operation may be omitted. In addition, CPU9, port 22,
The control circuit 23 and the AND gate 24 constitute an inhibition circuit.

The signal waveforms of the two channels displayed on the display 6 are, for example, as shown in FIG. 3A. Conventionally, although these two waveforms can be moved independently in the vertical direction, Because a common sweep signal was used, they could not move separately in the horizontal (time axis) direction and could only move together at all times. Therefore, as shown in FIG. 3A, two large pulse waveforms that are time-shifted cannot be viewed together in time. In the figure, CH1 and CH
2 indicate the first and second channels, respectively.
However, in the present invention, as shown in FIGS. 3B and 3C, the signal waveforms of the two channels can be shifted freely and independently in the horizontal direction, and the entire waveform can always be displayed. . That is, since the read start address is set to the address stored by the bias latch circuits 15 and 16 at the time of stop writing plus 1, if the memory contents of the bias latch circuit 16 are changed,
The starting point when reading the second channel changes and is displayed as shown in FIG. 3B. If the stored contents of the bias latch circuit 15 are changed, the starting point at the time of reading the first channel will be changed, and the display will be as shown in FIG. 3C. It is thus possible to freely move both or one of the signal waveforms in their entirety in the horizontal direction. To change the memory contents of the bias latch circuits 15 and 16, use the keyboard 1 which is a changing means.
The value set in step 2 may be sent to the bias latch circuit via the CPU 9 and bus 14, or while a specific key on the keyboard 12 is held down,
Bias latch circuits 15 and 1 by CPU9
It is also possible to add or subtract one by one to the stored contents of 6.

Moreover, even if the bias latch circuit 15 or 1
Even if the storage contents of 6 are changed and the display is moved horizontally, the entire capacity of the RAM of the selected storage circuit 3 is read out, so all the data stored in the RAM, that is, one cycle's worth of data, is always stored. Is displayed. In this case, it must be noted that the time relationship of the displayed waveforms is partially reversed.

Note that the present invention is not limited to the above-described embodiments, and various modifications and changes can be made without departing from the gist of the invention as set forth in the claims. For example, adding 1 to the memory contents of the bias latch circuit may be omitted in some cases. In this case, the read counter starts counting from 0001. Moreover, the present invention
In addition to transient digitizers, logic
It can also be applied to analyzers. Furthermore, the AND gate 24 may be provided after the delay counter 25.

[Effects of the Invention] As explained above, according to the present invention, when displaying input signals of multiple channels stored in a storage circuit on a display, the display position in the time axis direction can be controlled independently for each channel. . Therefore, temporally different portions of each input signal can be easily compared.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the invention, FIG. 2 is a detailed block diagram of a part of the invention, and FIG. 3 is a diagram showing an example of signal display according to the invention. 3: selection storage circuit, 6: display, 12: keyboard (changing means), 15, 16: bias latch circuit, 17: read counter, 20: addition circuit.

Claims (1)

[Claims] 1. A storage circuit that stores input signals of a plurality of channels, a counter that generates an address signal for the storage circuit, and a display that displays the input signal stored in the storage circuit. In the signal display device, a plurality of bias latch circuits provided for each of the plurality of channels, a changing means for changing the memory contents of the bias latch circuit, an address signal generated by the counter and the bias - further comprising an adder circuit that adds the memory contents of the latch circuit, addresses the memory circuit with the output signal of the adder circuit, reads the input signal stored in the memory circuit, and reads the read input signal. Displaying the signal on the display, changing the memory contents of the plurality of bias latch circuits by the changing means,
A signal display device characterized in that the display position of the input signal displayed on the display device in the time axis direction can be controlled for each channel.