JPH0562871B2 - - Google Patents

Description

[Detailed Description of the Invention] Industrial Application Field The present invention provides additional images such as characters and graphics that are independent of the received television image in a television receiver.
Superimposed on the TV received image (superimpose)
This invention relates to a screen position mark signal generation circuit that is necessary for displaying the screen position mark signal on the display of the receiver.

Prior Art The screen position for displaying such an additional image is determined by counting the horizontal retrace pulse signal from the vertical retrace pulse signal in the vertical direction, and by counting the horizontal retrace pulse signal from the horizontal retrace pulse signal in the horizontal direction. It was determined by counting the output pulse signals of a separately provided clock oscillator.

Problems to be Solved by the Invention In this conventional system, when a television video signal is being received, the vertical and horizontal retrace pulse signals are stable and vertically synchronized in phase with the vertical and horizontal synchronization signals, respectively. Since the horizontal deflection amplitude and horizontal deflection amplitude are also stable, the screen position for displaying the additional video is also stable, and the additional video is displayed at a fixed position and superimposed on the received TV video, so there is no problem, but if the TV video signal is not being received. Otherwise, vertical and horizontal deflection is performed by each oscillator that oscillates freely, and the period and deflection amplitude become unstable, and the display position of the additional image also changes from moment to moment, making it extremely difficult to see. Become something.

The present invention has been devised in view of these points, and it is an object of the present invention to provide a screen position mark signal generation circuit for displaying additional video at a fixed position on the screen regardless of the presence or absence of a received television video signal. The purpose is

Means for Solving the Problems FIG. 1 is a block diagram of a screen position mark signal generation circuit according to the present invention, in which 10 is a sawtooth voltage generation circuit proportional to the deflection current (hereinafter simply referred to as the sawtooth voltage generation circuit) 11 is a sawtooth voltage generation circuit proportional to the deflection current. The sawtooth voltage center potential detection circuit (hereinafter simply abbreviated as center potential detection circuit),
12 is a DC bias power supply, and 13 is a comparator. Output terminal 101 of sawtooth voltage generation circuit
is one input terminal 131 of the comparator 13
and is connected to the input terminal 111 of the center potential detection circuit 11. Output terminal 11 of center potential detection circuit 11
2 is connected to one electrode of the DC bias power supply 12, and the other electrode of the DC bias power supply 12 is connected to the input terminal 132 of the comparator.

With the above circuit configuration, a screen position mark signal is obtained at the output terminal 133 of the comparator 13.

Operation FIG. 2 is an explanatory diagram showing voltage waveforms at various parts of the block diagram of FIG. 1. In FIG. 2, 1 is the output terminal voltage v ₁ of the sawtooth voltage generation circuit in a synchronous state where a TV video signal is being received, and 2 is the output terminal voltage v ₂ in an asynchronous state where a TV video signal is not being received. shows. 3 is the output terminal voltage V ₀ of the center potential detection circuit detected for the voltages v ₁ and v ₂ ;
As shown in the figure, even if the sawtooth voltage changes greatly, the deflection is performed vertically or horizontally symmetrically, so the output terminal voltage V ₀ of the center potential detection circuit, which is the center potential of the sawtooth voltage proportional to the deflection current, is almost constant. is maintained. 4 is a DC bias voltage V _b , and a voltage of V ₀ +V _b is applied to the input terminal 132 of the comparator. On the other hand, the input terminal 131 of the comparator
is applied with v ₁ or v ₂ . Therefore, the output terminal voltage of the comparator is v ₁ and V ₀ +V _b or v ₂ and V ₀
+V _b is reversed at the matching point t ₁ or t _2, v ₅ is shown as 5 for v ₁ , v 6 is shown as ₆ for v ₂
The shape will be . That is, t ₁ and t ₂ can be detected from the point where the output terminal voltage of the comparator is inverted. point, t ₁ ,
The screen position corresponding to t ₂ is both at a potential V ₀ corresponding to the deflection center.Therefore, the position is shifted by the deflection width corresponding to the DC bias voltage V _b from the top and bottom or left and right center lines of the screen, and the output terminal voltage of the comparator The screen position corresponding to the point where is reversed remains constant regardless of the amplitude (deflection amplitude) of the sawtooth voltage. That is, the output voltage of the comparator becomes a screen position mark signal which is the object of the present invention.

Embodiment FIG. 3 is a block diagram of a video circuit of a television receiver having an additional video transmission circuit controlled by the screen position mark signal generation circuit of the present invention, and shows the output terminal of the screen position mark signal generation circuit 1. 18
is connected to the control terminal 20 of the additional video output circuit 2, its output terminal 21 is connected to the input terminal 30 of the video signal amplification circuit 3, and its output terminal 31 is connected to the input terminal 40 of the display 4. When a screen position mark signal (hereinafter abbreviated as mark signal) S ₀ is applied to the control terminal 20 of the additional video sending circuit 2, the additional video signal S ₁ is sent out from its output terminal 21, and together with the TV received video signal S ₂ . It is applied to the input terminal 30 of the video signal amplification circuit 3. Therefore, when the television reception video signal _S2 is present, the additional video signal _S1 is displayed superimposed on it, and when the television reception video signal _S2 is not present, only the additional video signal _S1 is displayed. Ru.

FIG. 4 shows an embodiment of blocks 1 and 2 of FIG. In FIG. 4, blocks and terminals common to those in FIG. 3 are given the same numbers. One input terminal 14 of the AND circuit 16 of block 1 of FIG. 4 is connected to the output terminal of the comparator of FIG. 1 for vertical deflection, and the other input terminal 15 is connected to the output terminal of the comparator of FIG. 1 for horizontal deflection. be done. The output terminal of the AND circuit 16 is one shot.
It is connected to the trigger terminal of a multivibrator (hereinafter abbreviated as one-shot MV) 17, and the output terminal of the one-shot MV 17 is connected to the output terminal 18 of block 1. The output terminal of block 1 is connected to the control terminal 20 of block 2. Control terminal 2
0 is connected to the input terminal 293 of the gate circuit 29 and the input terminal 281 of the counter 28;
The output terminal 282 of is connected to the second control terminal 292 of the gate circuit 29. The output terminal 294 of the gate circuit 29 is the reset terminal 274 of the counter 27.
and the first control terminal 253 of the gate circuit 25. The output terminal 277 of the counter 27 is connected to the second control terminal 254 of the gate circuit 25.
The output terminal 262 of the clock oscillation circuit 26 is connected to the input terminal 275 of the counter 27 and the input terminal 251 of the gate circuit 25, and the output terminal 252 of the gate circuit 25 is connected to the clock terminal 231 of the CPU 23. CPU 23 is connected to additional video data memory 22 by bus 24, and its output port 232 is connected to output terminal 21 of block 2. The other control terminal 50 of block 2 is the counter 2
The first gate circuit 29 of the reset terminal 283 of
is connected to the control terminal 291 of.

FIG. 5 is an explanatory diagram showing the process of forming the output signal _S0 of block 1 in FIG.

In FIG. 5, 1 is the vertical sawtooth voltage v ₁ , 2
is its center potential V ₀ , and 3 is the vertical DC bias voltage
V _b , 4 indicates V ₀ +V _b . 1st regarding vertical deflection
In the comparator shown in the figure, v ₁ and V ₀ +V _b are compared, and the potential at the input terminal 14 of the AND circuit 16 connected to its output terminal changes as shown in 5v ₅ in FIG.
In addition, 6 in FIG. 5 is the horizontal sawtooth voltage h ₁ , 7 is the center potential H ₀ , 8 is the horizontal DC bias voltage H _b ,
9 indicates H ₀ +H _b . In the comparator of FIG. 1 regarding horizontal deflection, h ₁ and H ₀ +H _b are compared and the input terminal 1 of the AND circuit 16 is connected to its output terminal.
The potential of 5 changes as shown in 10h ₅ in FIG. Since the AND circuit 16 takes an AND operation between v ₅ and h ₅ , its output voltage changes as shown in 11a in FIG. One shot MV triggered by the rise of this voltage
The output signal of is as shown in 12S ₀ in FIG. Here, the reversal period for one-shot MV is said to be extremely short. The first S ₀ of one field is a point shifted vertically from the center of the screen by a deflection width equivalent to voltage V _b from the center of the screen as shown in Figure 5, and horizontally from the center to H _b . Mark the point that shifted by the deflection width. Reference numeral 13 in FIG. 5 indicates the vertical retrace pulse signal V _r .

The vertical retrace pulse signal V _r is passed through the control terminal 50 of block 2 to the first control terminal 2 of the gate circuit 29.
91, closing this gate circuit and also resetting counter 28. _S0 passes through the control terminal 20 of block 2, passes through the gate circuit 29, and is applied to the first control terminal 253 of the gate circuit 25.
This gate is closed and the counter 27 is reset. When the gate circuit 25 is closed, the clock signal passes through this gate from the output terminal 262 of the clock oscillation circuit to the clock terminal 23 of the CPU 23.
1, and the CPU addresses the additional video data memory 22 in synchronization with this clock signal.
The data is read out and sent out from the output terminal 21 of block ₂ as the additional video image signal S1. The clock signal is also applied to the input terminal 275 of the counter 27, and the trailing edge of the clock of the last data counted by the counter 27 and sent out on one scanning line is applied to the input terminal 275 of the counter 27.
This signal is applied to the second control terminal 254 of the gate circuit 25 to open this gate. S ₀ is also counted by a counter 28 and the trailing edge of S ₀ for the last scan line sending out data is taken to the output terminal 282 of the counter 28 and this signal is passed to the second control terminal 2 of the gate circuit 29.
92 to open this gate. Through the operations of each block described above, one field of additional video signal is transmitted.

Generally, the clock oscillation circuit in Fig. 4 is not shown, but it is synchronized in phase with the horizontal retrace pulse signal, and the luminance component of the transmitted additional video signal mixes into the color signal frequency band, causing incorrect colors to be displayed in the additional video. Prevent from sticking.

The sawtooth voltage generation circuit 10 proportional to each deflection current and the circuit 11 for detecting its center potential shown in FIG. 1 are actually often included in the deflection circuit itself.

Figure 6 shows a typical vertical deflection circuit, in which transistors Q ₁ and Q ₂ are vertical deflection final stage drivers, L
is the vertical deflection coil, and C and R are the capacitor and resistor for improving linearity. Transistor _Q1 is NPN
type, Q ₂ is PNP type, both emitters are connected,
One end of the vertical deflection coil L is connected to that connection,
The other end is connected to one end of a capacitor C, and the other end of the capacitor C is grounded via a resistor R. Transistor Q ₁ causes current for the first half of deflection to flow through the vertical deflection coil, and transistor Q ₂ causes current for the second half of deflection to flow through the vertical deflection coil. The resistor R and capacitor C
The voltage at the junction of is completely proportional to the vertical deflection current. Therefore, if one end of another capacitor _C1 is connected to this point, the voltage at the other end of the capacitor _C1 becomes a sawtooth wave proportional to the vertical deflection current with the center potential at ground potential. That is, as shown in Figure 6, C ₁
The open end of the circuit 10 may be used as the output terminal 101 of the circuit 10 in FIG.

Figure 7 shows an example of a horizontal deflection circuit, where _Q3 is a final stage transistor, T is a flyback transformer, and the horizontal deflection coil L _h , capacitor C _h , and resistor R _h are connected in series to the secondary winding of the transformer. One end of _h is grounded. Therefore, since the voltage at the other end of resistor R _h is completely proportional to the horizontal deflection current, if one end of another capacitor C ₂ is connected to this point, the other end can be connected to the first
The output terminal 101 of the circuit 10 shown in the figure may be used as the output terminal 101, and the ground may be used as the output terminal 112 of the circuit 11.

Effects of the Invention As described above, according to the present invention, in a television receiver, an additional image independent of broadcasting is always stably displayed at a fixed position on the display regardless of the presence or absence of a television reception video signal. It is now possible to display not only the time display and channel number as additional images, but also CAPTAIN and teletext receiving terminals,
The present invention is extremely useful for constantly and stably displaying service information with a large number of characters in combination with graphic data such as explanations of each function of a television receiver equipped with multiple functions such as a monitor for a personal computer.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a screen position mark signal generation circuit according to the present invention, FIG. 2 is an explanatory diagram showing voltage waveforms at various parts of FIG. 1, and FIG. 4 is a block diagram showing an embodiment related to FIG. 3, FIG. 5 is an explanatory diagram regarding screen position mark signal formation in FIG. 4, and FIG. 7th
FIG. 1 is a circuit diagram showing an embodiment of the screen position signal generating circuit shown in FIG. 10...Deflection current proportional sawtooth wave voltage generation circuit, 11...Sawtooth wave voltage center potential detection circuit,
12...DC bias power supply, 13...Comparator.

Claims (1)

[Claims] 1 Consists of a sawtooth voltage generation circuit proportional to the deflection current, a sawtooth voltage center potential detection circuit, a DC bias power supply, and a comparator, and the output terminal of the sawtooth voltage generation circuit is connected to one input terminal of the comparator. Then, the sawtooth voltage center potential detection circuit and the DC bias power supply are connected so that the DC bias power supply voltage is added in series to the output terminal voltage of the sawtooth voltage detection circuit, and the added voltage is obtained. A screen position mark signal generation circuit whose terminal is connected to the other input terminal of the comparator to obtain an output signal from the output terminal of the comparator.