JPH056424B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a booster circuit comprising a MOS transistor and a capacitor.

An object of the present invention is to provide a booster circuit that has minimal voltage loss and power loss, is small in size, and is easy to manufacture.

Conventionally, in liquid crystal display wristwatches, a booster circuit has been used to obtain the high voltage necessary to drive the liquid crystal. Furthermore, since high voltage is required for dynamic driving of liquid crystals, a booster circuit is used. Typical conventional step-up circuits include: 1. A step-up circuit using a transformer.

2 Schenkel type booster circuit using capacitors and diodes.

There is. Figure 1 shows a step-up circuit using a transformer.
Figure 2 shows a Schienkel type booster circuit. In FIG. 2, a is a voltage doubler booster circuit, and b is a quadruple voltage booster circuit. In FIG. 1, 1 is a power supply battery, 2 is a step-up rectangular wave generation circuit, 3 is a step-up transformer, 4 is a rectifier diode, E ₁ is a power supply voltage, and E ₂ is a step-up output voltage. In FIG. 2, 5, 6, 9, 10, 11, and 12 represent Schottky diodes, and 7, 8, 13, 14, 15, and 16 represent boost capacitors, respectively.

Q in FIGS. 1 and 2 is a boosting square wave signal and its inverted signal, respectively, and since the circuit operation is already well known, a description thereof will be omitted.

These conventional booster circuits have large individual components.
Disadvantages include high losses and diode losses. The circuit of FIG. 1 requires a separate component, a large transformer. The Schenkel type booster circuit shown in FIG. 2 requires a large number of capacitors and diodes. This diode uses a somewhat special individual component called a Schottky diode to reduce the forward voltage drop. Furthermore, as long as diodes are used, voltage loss and power loss due to forward voltage drop are unavoidable. Regarding voltage, there is a loss of about 0.2V per diode, and it becomes even larger in the low temperature range. Regarding power loss, the circuit shown in Figure 2 is better than that shown in Figure 1, but it is still generally less than 85%.

In the present invention, it is a linear switching element.
A MOS transistor is used to charge and discharge a capacitor to boost the voltage. Since MOS transistors can be integrated onto watch ICs, there are fewer individual components, making it easier to incorporate them into watches. Furthermore, since nonlinear elements such as diodes are not used, an ideal boost ratio can be obtained. For example, in a voltage doubler booster circuit, a boost ratio of 1.99 times or more has been obtained. Furthermore, by considerably shifting the inversion timing of the gate signals of the multiple MOS transistors that serve as switching elements, leakage current is completely prevented and high power conversion of over 90% is possible. As described above, the present invention eliminates many of the drawbacks of conventional booster circuits.

FIG. 3 shows the principle of a voltage doubler booster circuit comprising a capacitor and a linear switching element according to the present invention. 1 is a power supply battery, S ₁ to _{S 3} are switching elements,
7 and 8 are individual capacitors. E ₁ is the power supply voltage,
E ₂ is the boost voltage.

In FIG. 3a, first the capacitor 7 is charged to the power supply voltage _E1 . At this time, S ₁ is closed and S ₂ is grounded. On the other hand, capacitor 8 is unaffected because _S3 is open. Next, the state shown in FIG. 3b is reached. At this time, _S1 is opened and _S2 is connected to the power supply side, so the power supply battery 1 and the capacitor 7 are connected in series. Therefore, the sum of the voltage E ₁ of the power supply battery and the voltage E ₁ charged in the capacitor 7, that is, a voltage of 2E ₁ appears at the tip of the capacitor 7. and
When S ₃ is closed, capacitor 8 receives this voltage 2
Charged with E ₁ . By repeating the states a and b in FIG. 3 alternately, the terminal voltage _E2 of the capacitor 8 becomes completely _2E1 , and a complete voltage doubler step-up circuit is realized. A 2 ^m voltage doubler circuit can be realized by repeating voltage boosting based on this output voltage E ₂ , and if the power supply voltage E ₁ is stacked l times on the 2 ^m boosted voltage, the voltage is increased by (2 ^m + l) times. A booster circuit can be realized. In other words, by using this boosting principle, any n-times boosting circuit can be realized. However, m, l, n are 1
These are the above natural numbers.

The actual upper limit of the boost ratio is limited by the switching element and the withstand voltage of the capacitor.

FIG. 4 shows a voltage doubler booster circuit using MOS transistors according to the present invention, and FIG. 5 shows its timing chart. The power supply battery 1 and capacitors 7 and 8 are the same as in FIG. 3, and the P-MOS transistor 20, C-MOS inverter 23, and
Each MOS transistor of the MOS transistor 22 functions as S ₁ , S ₂ , and S ₃ in FIG. 34 is a low voltage system-high voltage system C-MOS interface circuit, which converts the switching control signal c of the P-MOS transistor 22 from a low voltage to a high voltage.
Also, the substrate electrodes of the MOS transistors 20 and 22 must be connected in the direction shown in FIG. 4, that is, to their respective drain electrodes, so that the parasitic diodes of the MOS transistors are in the forward direction with respect to the charging current of the capacitor. There must be. Otherwise, the urgent boosted voltage will flow back to the power supply side due to the parasitic diode. The operation of the circuit is P-
The MOS transistor 20 receives the switching signal control signal B which is inverted by the C-MOS inverter 21, and the P-MOS transistor 22 receives the signal C obtained by inverting and converting the switching control signal ^C.
A C-MOS inverter consisting of two C-MOS inverters, each of which is switched by a switch, serves as a changeover switch.
A switching control signal A is input to the buffer 23 to switch the potential of one terminal of the capacitor 7, thereby operating as explained in FIG. Here, the switching control signals for driving the switching elements 23, 20, 22 are shown as A, B, and C in FIG.
By slightly different pulse widths,
Interference between switching elements is eliminated.

This means that when switches _S1 and _S3 are turned on at the same time, even momentarily, when changing from the state shown in Figure 3a to the state shown in Figure 3b, the charge in capacitor 8 charged to _2E1 is transferred to battery _E1. There is a risk of discharge through the In particular, if switches S ₁ and S ₂ are configured with MOS transistors and controlled by signals that are inverted at the same timing, MOS transistor 22 will turn on before MOS transistor 20 in FIG. The charge is discharged and the boost dynamic rate decreases. In the present invention, the inversion timing of switch control signals B and C is shifted as shown in FIG. The configuration is such that the signal changes from high to high, turning on the MOS transistor 22.
Similarly, when the state changes from b to a in Fig. 3, the switching control signal C in Fig. 5 changes from high to low, and then the signal B changes so that switch _S3 turns off and then switch _S1 turns on. It changes from low to high to prevent charge leakage.

Furthermore, the relationship between switching control signals A and B is similar. That is, when changing from a to b in FIG. 3, if the switch _S2 is turned off before the switch _S1 is turned off, the charge in the capacitor 7 will be discharged. Therefore, the switching control signal A in Fig. 5 changes depending on whether the signal B changes to high or low.
After the MOS transistor 20 is completely turned off, it changes from low to high, changing the voltage at one terminal of the capacitor 7 to the battery voltage _E1 , thereby preventing the charge in the capacitor 7 from discharging. Similarly, Figure 5b
When changing from to a, the signal B in Fig. 5 is turned on so that switch S ₁ is turned on after switch S ₂ is switched.
is configured so that the signal A changes from high to low and then changes from low to high, turning on the MOS transistor 20, thereby preventing charge leakage.

In this way, in the present invention, the MOS transistor 2
By shifting the inversion timing of switching control signals B and C of 0 and 22 to prevent charge leakage from the capacitor 8, and by shifting the inversion timing of switching control signals A and B to prevent charge leakage from the capacitor 8, further switching control is performed. By shifting the inversion timing of the signals A and C, charge leakage from the capacitor 8 can be prevented, and by using the relationship between these signals alone or in combination, the boosting rate of the booster circuit can be significantly increased.

Furthermore, switching control signals A and C in FIG.
Similarly, when signal A changes from low to high and signal C changes from low to high, changing from a to b in Figure 3, switch _S3 is turned on while switch _S2 is on the low side. Similarly _, when _changing from FIG.
In order to prevent the charge from leaking, the signal A changes from high to low after the signal C in FIG. 5 changes from high to low.

4th under conditions similar to conventional Schenkel type booster circuit
FIG. 6 shows the results of an experiment using the circuit shown in the figure. Operating frequency is 256Hz, capacitors 7 and 8 are both 0.47μF,
Measurements were made at E ₁ =3000V using RCA's CD4000A series C-MOS transistor. The CD4000A series has an input protection circuit, so we added some circuitry to prevent league current from occurring. The vertical axis in FIG. 6 shows the boost ratio and the power conversion efficiency, and the power conversion efficiency is very excellent, although the value of the boost ratio marked with ● is represented by an x mark. When the negative resistance was 200KΩ or more, the boost ratio was 1.9 times or more, which was very satisfactory. The measured value of power conversion efficiency is indicated by a circle, and this is also a fairly good result, with efficiency exceeding 90% over a wide range. The efficiency decreases on the high resistance load side (minimal current negative side), but this is due to the MOS transistor itself.
Or it was because the leakage current from the input protection circuit was about 1μA.

Therefore, C- with low leakage current is suitable for watches.
If made with MOS-IC, the efficiency on the high resistance negative side is also 90%.
It is thought that it will be more than that.

As described above, the booster circuit of the present invention has control signals A,
Since the inversion timings of B and C are shifted from each other, superior data can be obtained using the conventional booster circuit. Furthermore, based on this data, it is predicted that the liquid crystal can be sufficiently driven even by using a small capacitance capacitor integrated in a thin film on a monolithic IC.

As described above, the present invention uses a MOS transistor as a linear switching element, shifts the inversion timing of the switch control signal, and prevents leakage of charge from the capacitor, thereby achieving an extremely high dynamic rate and This is an ideal booster circuit for watches, etc.

Further, in the present invention, the first terminal of the first capacitor 7 is connected to the second electrode of the first switch element 20, and the second terminal of the first capacitor 7 is connected via the changeover switch 23. MOS transistors of different channels connected in series and connected alternately to the output terminals of the first polarity or the second polarity of the power supply are connected in parallel to the first capacitor 7, and the gate electrodes are connected to each other and the output electrodes are connected to each other. The output electrodes are connected to the first switch element 20.
CMOS transistor 2 connected to the gate electrode of
1 is provided, and the polarity of the power supply applied to the second terminal of the first capacitor 7 is switched only when the transistor of the same channel as the first switch element 20 of the CMOS transistor 21 is on. By making the switching timing of the control signal B applied to the gate electrode of the CMOS transistor 21 different from the polarity switching timing of the control signal A applied to the changeover switch 23, backflow from the first capacitor to the power supply is prevented. It is possible to increase the pressure efficiently.

Further, when the first capacitor 7 is discharged, the voltage at the first terminal of the first capacitor 7 becomes the sum of the power supply voltage and the charging voltage of the first capacitor 7, The voltage at the terminals of
Since the voltage is applied to the gate electrode of the first switch element 20 through the P-channel transistor of the CMOS transistor, when the first capacitor 7 is discharged, an additional voltage is required to maintain the off state of the first switch element 20. There is no need for a power source for high-voltage control signals, and the circuit can be easily configured.

[Brief explanation of the drawing]

Figure 1 is a diagram of a step-up circuit using a conventional transformer. Figure 2 shows a conventional Schenkel type booster circuit. A is a voltage doubler boosting circuit diagram, and b is a quadruple voltage boosting circuit diagram. FIG. 3 is a simple operational diagram of a voltage doubler booster circuit using a capacitor and a switching element according to the present invention. "a" indicates the operation during the charging period, and "b" indicates the operation during the boosting and discharging periods. Figure 4 is a diagram of a voltage doubler booster circuit using a capacitor and MOS switching element according to the present invention. FIG. 5 is a timing chart of control signals A, B, and C of the circuit shown in FIG. 6th
The figure is a graph showing the relationship between the step-up ratio, power conversion efficiency, and load resistance of the circuit of FIG. 5. 20, 22...P-MOS switching transistor. 21... Interface by C-MOS inverter. 23...C-MOS buffer that works as a switching element. 34...Low voltage system-
High voltage interface circuit. A...C-
Switching control signal for MOS buffer 23. B
...Switching control signal of P-MOSTr20.
C...Switching control signal of P-MOSTr22. D...Boost output.

Claims (1)

[Claims] 1. Includes a gate electrode and first and second electrodes.
A MOS transistor is used as a switch element, a first polarity output terminal of the power supply is connected to a first electrode of the first switch element, and a second electrode of the first switch element is connected to a first polarity of the output terminal of the first switch element. a first terminal of the second switch element is connected to the first terminal of the first capacitor; a first terminal of the second capacitor is connected to the first terminal of the second switch element; the second terminal of the first capacitor is alternately connected to the first polarity or second polarity output terminal of the power source via a changeover switch; In a booster circuit configured such that a second terminal of a capacitor is connected to an output terminal of a second polarity of the power supply, the substrate electrodes of the first and second switch elements are connected to the first and second polarity, respectively. The capacitor is connected to an electrode such that a parasitic diode is formed in the charging direction of the capacitor, and MOS transistors of different channels connected in series are connected in parallel to the first capacitor, and the gate electrodes and the output electrodes are connected to each other. a CMOS transistor whose output electrode is connected to the gate electrode of the first switch element; said terminal so as to switch the polarity of the power applied to the second terminal
By making the switching timing of the control signal applied to the gate electrode of the CMOS transistor different from the polarity switching timing of the control signal applied to the changeover switch, backflow from the first capacitor to the power supply is prevented. A booster circuit characterized by the following.