JPH0564374B2 - - Google Patents

Description

[Detailed description of the invention]

(Industrial Application Field) The present invention relates to a list processing device such as a computer that performs non-numerical processing such as list processing at high speed. (Prior Art) The Lisp language is widely used as a language for knowledge processing, and a program written in the Lisp language is expressed and executed in a computer using list cells and data. FIG. 2a shows the format of a conventional list cell. A conventional list cell consists of a data type section and an address section, and the address section consists of a base address section and an offset address section. Second
FIG. b shows a case where list data (AB) is expressed using the above list cells. That is, a list node is expressed using two of the above list cells. In addition, the list cell and data A and B are stored in different areas in the storage device, the base address part of the address part fixes the area, and the offset address part shows the address in the area selected by the base address part. . One list cell is usually represented by 32 bits,
In this case, the address field is expressed in 24 bits. Therefore, the address space in which list cells and data can be stored is limited to the range expressed in 24 bits. (Problems to be Solved by the Invention) However, programs written in Lisp often need to handle list cells and data exceeding 24 bits. In such a case, there is a problem in that the configuration of the conventional list cell must be expanded from 32 bits. Therefore, the present invention provides a list processing device that can expand the address space without expanding the list cells. (Problems to be Solved by the Invention) The device of the present invention stores a list cell, which is composed of a data type field and an offset address field that define the type of data, and data specified by the list cell. a list cell register for temporarily storing the list cell taken out from the storage means, a base address storage means for storing the base address of the list cell and the data, and a data type section of the list cell register. an address register for temporarily storing the address of the list cell and the address of the data, comprising a base address taken out from the selected base address storage means and an offset address section of the list cell register; and arithmetic means for processing the data, and the list cell and the data are specified by a base address stored in the base address storage means defined by the data type of the list cell. It provides equipment. (Example) Next, an example of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. The first list processing device includes a storage section 1, a list cell register 2, and a base address storage section 3.
, address register 4, arithmetic unit 5 and control unit 6
It is composed of. The storage unit 1 has a word structure of 32 bits per word, and stores list cells and data indicated by the list cells. List cell register 2
is a 32-bit long register. The base address storage section 3 has a word structure of 8 bits as one word, and stores base addresses corresponding to data types, as will be described later. address register 4
is a 32-bit register that temporarily stores the address to be supplied to the storage unit 1. The calculation section 5 is a circuit that processes list cells and data, and the control section 6 is a circuit that generates control signals to control each section of the list processing device. FIG. 3a shows the configuration of the list cell used in this embodiment. The list cell consists of an 8-bit data type field and a 24-bit offset address field. Further, FIG. 3b shows an example of the correspondence between the data type section, data type, and base address. In FIG. 3b, the data type field and base address are 8 bits long and are shown as two digits in hexadecimal representation. The data type section defines data such as list cells and stacks, binary data, character data, full word areas, etc. The base address corresponding to each is the base address where the list cells and data are stored in the storage section. stipulates. In this embodiment, the data type field and the base address have the same value, but they can be set freely. FIG. 4 shows the structure when the list data (AB) expressed by the conventional list cell shown in FIG. 2b is expressed by the list cell of this embodiment. Figure 4 shows list cells in storage unit 1.

[Formula] (hereinafter referred to as "Character (AO), 100") at address 7F100, list cell "List (7F), 201" at address 7F101, list cell "Character (AO), 100" at address 7F201 Add data A to the address
It also shows that data B is stored at address AO100 and data B is stored at address AO101. Figure 5 shows the base address value stored in the base address storage unit 3 when specifying the data type field and base address shown in Figure 3b. indicates that the value 7F is stored and the value AO is stored at the AO address. In this example, the value 00 is stored at address 60, the value 01 is stored at address 01, and the value AO is stored at address AO, but these values can also be set to other free values. It is. First, the process of executing the lisp function Atom on the list data (AB) shown in FIG. 4 will be explained. That is, when executing Atom [(AB)], the list cell "List (7F), 100" is set in the list cell register 2 from the calculation unit 5 via the signal line 51. This value is taken into the arithmetic unit 5 via the signal line 23, and by examining the value "7F" in the data type section, it is determined that the cell is a list cell. Therefore, it turns out that it is not lisp Atom data, and outputs a false value. Next, the process of executing the lisp function Cdaar on the list data (AB) shown in FIG. 4 will be described.
In other words, when executing Cdaar [(AB)],
“List (7F), 100” is set in the list cell register 2 from the calculation unit 5 via the signal line 51. The base address storage unit 3 is accessed via the signal line 21 using the value “7F” in the data type section of the list cell register 2, and the value 7F at address 7F is taken out via the signal line 31 and set in the upper part of the address register 4. do. At the same time, the value "100" in the offset address part of the list cell register 2 is set to the lower part of the address register 4 via the signal line 22. Next, the value "7F, 100" set in the address register 4 is sent to the storage unit 1 via the signal line 41, and the value "7F, 100" is sent to the storage unit 1 via the signal line 41.
The data at the next address "7F, 101" is read out and set in the list cell register 2. Through this process, "7F, 201" is set in the list cell register 2 as shown in FIG. After performing similar processing, address register 2 is set to “7F,”
201" is set. To perform car processing based on this value, signal line 4 is set.
Send “7F, 201” through 1 and send “Character (AO),
101" is taken out and set in list cell register 2.Furthermore, in order to perform car processing, similar processing is performed based on "character (AO), 101" of list cell register 2, and the address "AO, 101" is Cdaar processing is completed by extracting the value character "B" and setting it in the list cell register 2. An embodiment of the present invention has been described above, but by using the data type part of the list cell, It was shown that the address space can be expanded, i.e.,
While the conventional example is limited to 24-bit address expression, this embodiment allows 32-bit address expression even though it is a 32-bit long list cell expression. That is, in this embodiment, the data type section of the list cell indicates the data type and also indicates the base address of the storage unit 1 in which the data is stored. (Effects of the Invention) According to the present invention, by using the data type section for base address specification, it is possible to provide a list processing device that exhibits a large address space even when using list data with a small bit width.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2a is a configuration diagram showing a conventional list cell;
FIG. 2b is a configuration diagram showing an example of conventional list data, FIG. 3a is a configuration diagram showing a list cell according to an embodiment of the present invention, and FIG. FIG. 4 is a diagram showing the relationship between data types and base addresses, FIG. 4 is a configuration diagram showing an example of list data, and FIG. 5 is a diagram showing the contents of the base address storage section. 1...Storage unit, 2...List cell register, 3
... base address storage section, 4 ... address register, 5 ... calculation section, 6 ... control section.

Claims (1)

[Scope of Claims] 1. A storage means for storing a list cell including a data type field and an offset address field that define the type of list cell and data, and data specified by the list cell, and from the storage means. a list cell register for temporarily storing retrieved list cells; base address storage means for storing base addresses of the list cells and the data; and base address storage selected by the data type section of the list cell register. an address register for temporarily storing the address of the list cell and the address of the data, comprising a base address taken out from the means and an offset address part of the list cell register; and an arithmetic means for processing the list cell and the data. A list processing device, characterized in that the list cell and the data are specified by a base address stored in the base address storage means defined by the data type of the list cell.