JPH0564381B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] Regarding the data transmission device of the present invention, in particular, data transmitted at arbitrary time intervals can be transmitted independently and selectively to one of a plurality of parallel transmission paths. The present invention relates to a data transmission device for transmitting data to a computer.

[Prior Art] A processing device such as an electronic computer connects a plurality of processing units through communication using digitized signals to perform data processing. In this way, when data processing is distributed and processed by multiple processing units, the content of the data processing in each processing unit is generally different, and the data required for each processing and the results obtained are also different. .

[Problems to be solved by the invention] When combining the plurality of processing unit groups described above,
If you wire the units where data needs to be exchanged for each data process and provide input/output ports,
There were problems in that the hardware became very complex, the device became large, and the cost became expensive.

Therefore, the main object of the present invention is to be able to transmit different types of data groups using the same data transmission path, and to identify the destination of the data by a part of the data or an identifier attached to the data. It is an object of the present invention to provide a data transmission device that can reduce the amount of hardware wiring by specifying the data transmission path, and can independently and selectively transmit data to a desired transmission path.

[Means for Solving the Problems] The data transmission devices according to the present invention are provided in parallel, and in response to outputting a transmission permission signal to the subsequent stage, hold data from the subsequent stage and transmit data from the previous stage. In response to the permission signal being given,
a plurality of output side data transmission lines that output data;
In response to outputting a transmission permission signal to the subsequent stage, a transmission permission signal is given from the previous stage after receiving data from the latter stage and a part of the data or an identifier for specifying a transmission path associated with the data. an input side data transmission line that outputs data and an identifier to the previous stage according to the input side data transmission line, a determining means for determining whether or not a transmission permission signal is output from each of the plurality of output side data transmission lines, and an input side data transmission line. When the determining means determines that data can be transmitted to the output data transmission path represented by the identifier given by the identifier, the input data transmission path is permitted to receive data. and an input control means for controlling data transmission from the input data transmission path in response to the determination means determining that data can be transmitted to the output data transmission path corresponding to the identifier. and output control means for transmitting data to the output side data transmission path.

[Operation] In the data transmission device according to the present invention, when the output side data transmission path to be transmitted is in a transmittable state, according to a part of the data or an identifier attached to the data, the output indicated by the identifier is transmitted. If it is possible to transmit data to the data transmission path on the side and to the data transmission path on the output side represented by the identifier, control is performed to permit the data transmission path on the input side to receive data.

[Embodiment of the Invention] FIG. 1 is a schematic block diagram of an apparatus for splitting and transmitting a date into two according to an embodiment of the invention.

First, referring to FIG. 1, an example in which data is transmitted by branching to two transmission paths will be briefly described.
Data transmission lines 1, 100, and 200 used in the embodiment shown in FIG. 1 each include a data register and a transfer control circuit for transmitting data. is provided. The identifier transmission path 2 is for transmitting an identifier called a tag. This identifier indicates which of the two data transmission paths 100 and 200 the data transmitted to the data transmission path 1 should be transmitted to.

Now, when both data transmission paths 100 and 200 are empty and data transmission is possible, UK signals 10a and 2 are transmitted from the next stage data transmission path (not shown).
0a is given to the control units 10 and 20, respectively.
Further, the data transmission paths 100 and 200 are
Similarly for UL signals 10d and 20d,
The signals are provided to the control units 10 and 20, respectively. UL signals 10d and 20d are data transmission lines 100 and 200
This is a signal given from any preceding stage of the data transmission path, and indicates that the data transmission path is empty and data transmission is possible. The control units 10 and 20 respectively receive a UK signal 10a, an LU signal 10d, and a UK signal 2.
When the 0a and UL signals 20d are input, the data transmission path 100 and the data transmission path ahead of this data transmission path 100, and the data transmission path 200 and the data transmission path ahead of this data transmission path 200 are respectively empty. If the data has been retained by then, the data is transferred to the next stage,
It becomes active to enable branch control for subsequent input data.

When the NOR gate 4 receives determination signals 10b and 20b from the control units 10 and 20 indicating that the respective control units are empty and activated, the NOR gate 4 transmits the AK signal to the data transmission line 1 and the identifier. It is given to transmission line 2. In this way, the data transmission line 10
0, 200 and the UK signal and UL signal from the data transmission path at the preceding stage, the branch control units 10, 20 to the data transmission path 100, 200 depending on whether the preceding stage is empty or not. Data transmission is permitted or prohibited, and branching and transmission of data from the transmission path 1 to the control unit 10 or 20 is permitted or prohibited.

The identifier transmission path 2 provides the identifier decoder 3 with an identifier indicating that the data transmitted to the data transmission path 1 should be transmitted to the data transmission path 100, for example. The identifier decoding section 3 decodes the identifier transmitted from the identifier transmission path 2, and supplies a control signal 10c to the control section 10 to activate it. Thereby, data transmitted from the data transmission path 1 can be transmitted to the data transmission path 100 via the control section 10. Conversely, when an identifier indicating that data is to be transmitted from the identifier transmission path 2 to the data transmission path 200 is given to the identifier decoding section 3, the identifier decoding section 3 gives a control signal 20c to the control section 20 to activate it. data transmitted to the data transmission path 1 can be transmitted to the data transmission path 200 via the control unit 20.

If, for example, the data transmission path 100 is holding data or is transmitting data in any of the data transmission paths 100, 200, 100 and 200, the controller 10 In contrast, the UK signal 10a is not given. Similarly, even when the previous stage of the data transmission path 100 is holding data or is transmitting data, the UL signal d is not applied to the control unit 10. For this reason, the control unit 10
It determines whether the previous stage of 00 to 100 is transmitting or is in a jammed state, stores the data input to a register (not shown) included in the control unit 10, and outputs data to one input terminal of the NOR gate 4. Give an "H" level signal to.

Therefore, the NOR gate 4 is closed and the AK signal is not applied to the data transmission line 1 and the identifier transmission line 2. That is, data transmission paths 100, 20
If any of the data transmission paths at the first stage of 0, 100 and the first stage of 200 holds data or is in the process of transmitting data, and furthermore, when the control units 10 and 20 hold data, the data transmission The data transmitted through line 1 is held on data transmission line 1 without being input to control units 10 and 20. However, if the preceding stage of the data transmission paths 100 and 200 or the preceding stage of the data transmission paths 200 and 200 and the control section 10 or 20 complete data transmission and transition from the clogged state to the empty state, the control section 10 or 20 is activated. By that,
The data input held in the data transmission path 1 can be independently branched again according to the identifier.

FIG. 2 is a specific circuit diagram of an embodiment in which packet data is alternately divided into two branches. In this example,
Without using the UL signals 10d and 20d shown in FIG.
This is intended to selectively control branching only depending on the empty/clogged state of 0.

First, the configuration will be explained with reference to FIG. Data from the data transmission line 1 shown in FIG. 1 mentioned above is given to the register 5. This register 5 temporarily stores n-bit data. Further, the identifier transmitted to the identifier transmission line 2 shown in FIG. 1 is applied to the D input of a D type flip-flop 2 which also serves as an identifier decoding section.
C elements (coincidence elements) 6 and 7 control writing of data into the register 5 and the D type flip-flop 2 based on the pulse signal Co.

One control section 10 includes a register 11 and a C element 12.
and 13, AND gate 14, D-type flip-flop 15, delay element 16, and AND
It consists of gates 17 and 18. Also,
The other control section 20 is composed of a register 21, C elements 22 and 23, an AND gate 24, a D type flip-flop 25, a delay element 26, and AND gates 27 and 28.

Registers 11 and 21 temporarily store the n-bit data stored in register 5 described above. C elements 12 and 13 control writing of data to register 11, and C elements 22 and 23 control writing of data to register 21. The D-type flip-flops 15 and 25 register 5 based on the identifier decoded by the D-type flip-flop 2 described above.
Write the data stored in the register 11 of the control unit 10 or write the data stored in the register 2 of the control unit 20
This is to selectively control whether to write to 1 or not.

Next, the operation of the data transmission device shown in FIG. 2 will be explained. In the initial state, the reset signal is applied to C elements 6, 7, 12, 13, 22 and 2.
3 and initial resets them, and also initial resets D type flip-flops 15 and 25 via AND gates 14 and 24, respectively. D type flip-flop 15 and 2
5 has been initial reset,
The outputs of Q1 and Q2 are both at "L" level. Furthermore, since C elements 12, 13, 22 and 23 have also been reset, their respective Q1 outputs are at the "L" level and their Q2 outputs are at the "H" level.

Q1 output of C element 12 and Q1 of C element 22
The outputs are respectively given to NOR gates 4.
Since the two inputs of the NOR gate 4 are at the "L" level, it outputs the AK signal at the "H" level. When this AK signal is at the "H" level, it indicates that data and tags can be transmitted to the data transmission path 1 and the identifier transmission path 2.

In this state, data is input to register 5,
An identifier is applied to the D type flip-flop 2 and a pulse signal Co is applied to the C element 6.
At this time, the Q2 output of C element 7 is at the "H" level due to the initial reset. Pulse signal Co
When the Q1 output of C element 6 becomes "H" level, the Q1 output of C element 6 becomes "H" level. The AK signal of C element 7 is “H”
level, the pulse signal Co is transmitted to the Q1 output of the C element 7. Then register 5 is C
Data is stored at the timing when the Q1 output of element 7 rises to the "H" level. Q1 of C element 7
The output is about to be transmitted to the C elements 12 and 22, but since the Q1 output of the D type flip-flop 15 and the Q2 output of the D type flip-flop 25 are at the "L" level due to the initial reset, , the Q1 output of C element 7 is not allowed to be input to C elements 12 and 22.

On the other hand, it is assumed that the identifier given along with the data indicates "1", for example, in order to transmit the data to the data transmission path 100. The identifier of the D type flip-flop 2 is set to "1", and at the timing when the Q1 output of the C element 7 rises to the "H" level, the Q output is set to the "H" level and the output is set to the "L" level. . The “H” level Q output of D type flip-flop 2 is connected to AND gate 1.
is applied to one input terminal of 8. The other input terminal of this AND gate 18 is given the delayed signal of the Q2 output of the C element 13. Both signals are “H”
level, that is, when register 11 has completed data transmission and the Q of D type flip-flop 2 is
When the output reaches the "H" level, the D-type flip-flop 15 is set and its Q1 output goes to the "H" level, but the Q2 output of the D-type flip-flop 25 remains at the "L" level. is held.

The "H" level Q1 output of the D-type flip-flop 15 is applied to one input terminal of the AND gate 17. Since the Q output of the D-type flip-flop 2 is applied to the other input terminal of the AND gate 17, both signals become "H" level, and the Q1 output of the C element is accepted by the C element 12. is transmitted to its Q1 output. Then, when the transmission permission signal UK12 from the data transmission line 100 goes to "H" level, the Q1 output of C element 13 goes to "H" level. Then, at the rising timing, the data stored in the register 5 is stored in the register 11, and the data transmission line 10
0 can be transmitted.

On the other hand, since the Q2 output of the D-type flip-flop 25 is at "L" level, the AND gate 27
is closed, and the Q1 output of C element 7 is not transmitted to the Q1 output of C element 22. Therefore, register 2
1 is not given a pulse signal, and the data stored in register 5 is not transmitted to register 21. In this way, when the identifier becomes "1", the data stored in the register 5 is transmitted to the data transmission path 100 via the register 11, but not to the data transmission path 200.

As described above, when the Q1 output of the C element 13 goes to the "H" level and the Q2 output goes to the "L" level, the AND gate 14 activates the D type flip-flop due to the "L" level of the Q2 output of the C element 13. Reset the flop 15. When the D type flip-flop 15 is reset, its Q1 output goes to the "L" level and is applied to the AND gate 17. When the AND gate 17 is supplied with the "L" level signal, its output goes to the "L" level, and this is supplied to the C element 12, so that the Q1 output of the C element 12 goes to the "L" level. At this time, since the Q1 output of the C element 22 is also at the "L" level, the NOR gate 4 outputs the AK signal at the "H" level. Thereby, transmission of subsequent data to data transmission line 1 is permitted.

Next, the input data is transferred to the data transmission path 200.
When the identifier is set to "0" in order to transmit to It will be done. As a result, the data stored in the register 5 is stored in the register 21, and the data transmission line 2
It becomes possible to transmit to 00.

In the above explanation, data from data transmission path 1 is transmitted only to either data transmission path 100 or 200, but it is also possible to transmit data to both data transmission paths 100 and 200 at the same time. It is. In that case, the output of either Q or of the D-type flip-flop 2, which is the input of the AND gates 18 and 28 that generate the clock pulses of the D-type flip-flops 15 and 25, is commonly given. Just do it like this.

In this way, when data is sequentially input to the data transmission line 1, the operation when the data is held for a long time on the data transmission line 100 or 200 and smooth data transmission is interrupted is shown in Figure 2. This will be explained with reference to the examples shown. For example, if the data transmission line 100 is clogged and data transmission to the next stage is stopped, at this time the data transmission line 1
Assume that further data requesting branching of the data transmission path 100 is transmitted. Data transmission line 1
In response to 00 being jammed, UK12
continues to fall to the "L" level, so the Q1 output of the C element 13 is held to the "H" level, and the Q2 output is held to the "L" level.
The Q2 output of C element 13 is passed through AND gate 14 to hold D type flip-flop 15 in a reset state. That is, the Q1 output of the D-type flip-flop 15 is held at the "L" level and is applied to one input terminal of the AND gate 17. An identifier indicating branching to the data transmission line 100 is given to the other input end of the AND gate 17, but the output of the AND gate 17 is at "L" level, and as a result, the identifier is not accepted.
That is, the control unit 10 is not activated by data newly input to the data transmission path 1.

However, when the above-mentioned clogged condition is resolved and the data transmission line 100 starts transmitting data again,
UK12 transitions from the "L" level to the "H" level, the Q1 output of the C element 13 accordingly transitions to the "L" level, and the Q2 output transitions to the "H" level.
Thereby, the data stored in register 11 is transmitted to data transmission line 100. Furthermore, the Q2 output of C element 13 is
6 to one input terminal of the AND gate 18 and the other input terminal thereof is enabled, and the clock input terminal CP1 of the D-type flip-flop 15 is raised to the "H" level. .

As a result, the D-type flip-flop 15 transitions to the set state, and its Q1 output rises to the "H" level. Accordingly, the AND gate 17
The identifier input to the other input terminal is validated and applied to the C element 12. As a result, the Q1 output of the C element 7, which was holding the "H" level, is accepted by the C element 12 for the first time at this point, and the data stored in the register 5 is independently branched to the control unit 10. transmitted.

As described above, in this embodiment, when data is input to the data transmission path 1, the control unit 10
and at least one of the data transmission path 100 or the control unit 20 and the data transmission path 200 is clogged, and UK12 or UK2
2 is at the "L" level, the input data is held in the data transmission path 1 and is not branched and transmitted to the control section 10 or 20. However, when data transmission line 100 or 200 completes data transmission to the next stage, UK12 or UK
22 transitions to the "H" level, and the data that has been waiting on the data transmission path 1 is independently branched and transmitted to the input control section 10 or 20.

FIG. 3 is a specific circuit diagram of another embodiment in which data is divided into two branches. In this embodiment, the UL signals 10d and 20d shown in FIG.
Depending on the empty/clogged state of 00 and its predecessor,
The case of selective branching will be explained.

First, the configuration will be explained with reference to FIG. The apparatus shown in FIG. 3 is the same as that shown in FIG. 2 above, except for the following points. That is, the control unit 1
0 includes an AND gate 19 instead of the delay element 16 shown in FIG. AND gate 19 connects the UL1 signal sent from the previous stage data transmission path and C element 13.
When UL1 is “H” level after receiving the Q2 output of
The two outputs of the C element 13 are applied to one input terminal of the AND gate 18. Similarly, the AND gate 29 receives the UL2 signal sent from the previous data transmission line and the Q2 output of the C element 23, and UL2 goes "H".
If it is level, AND the Q2 output of C element 23.
It is applied to one input terminal of gate 28.

Next, the operation of the data transmission device shown in FIG. 3 will be explained. In exactly the same way as the embodiment shown in FIG. 2, when initialized by a reset signal, the data transmission line 100 and its preceding stage and the data transmission line 200 and its preceding stage are also in an empty state, that is, UK12, UK22, UL1 and UL2 all become “H” level. In this state, data is input to the register 5, an identifier is applied to the D type flip-flop 2, and a pulse signal Co is applied to the C element 6. It is assumed that the identifier given along with the data indicates "1", for example, in order to transmit the data to the data transmission path 100.
In this case, the same operation as in the embodiment shown in FIG. However, data transmission to the control unit 20 is prohibited.

Next, when the control unit 10 completes data transmission to the data transmission path 100, the NOR gate 4 becomes “H”.
Outputs level MK signal. Transmission of subsequent data is thereby permitted.

Next, in order to transmit the input data to the data transmission path 200, when the identifier is set to "0", the control section 20 is activated, and the data stored in the register 5 is transferred to the register via the control section 20. 21 and can be transmitted to the data transmission path 200.

Note that in the above explanation, data from data transmission path 1 is transmitted only to either data transmission path 100 or 200, but it is also possible to transmit data to both data transmission paths 100 and 200 at the same time. The possibilities are the same as in the embodiment shown in FIG.

As described above, when data is sequentially input to the data transmission line 1, the data is held for a long time on the data transmission line 100 and its subsequent stage, or on the data transmission line 200 and its subsequent stage, and smooth data transmission is prevented. The operation in the case of interruption will be explained with reference to the embodiment shown in FIG. For example, if the data transmission path 100 and its preceding stage are clogged, and data is held in all data transmission paths from the data transmission path 100 to the targeted preceding stage,
Assume that data requesting further branching to the data transmission path 100 is input to the transmission path 1 while data transmission is stopped.

At this time, UK12 and
UL1 continues to fall to “L” level,
Therefore, the Q1 output of C element 13 is held at the "H" level, and the Q2 output is held at the "L" level. Furthermore, the Q2 output of the C element 13 is passed through the AND gate 14 to the D type flip-flop 15.
is held in the reset state. That is, the Q1 output of the D type flip-flop 15 is held at the "L" level and is applied to the input terminal of the AND gate 17. The other input terminal of the AND gate 17 is given an identifier indicating branching to the data transmission path 100, but the output of the AND gate 17 is at the "L" level, and as a result, the identifier is not accepted.

That is, the control unit 10 is not activated by data newly input to the data transmission path 1.

Next, when the clogged state in the preceding stage of the data transmission path 100 of interest is resolved and data transmission begins to resume, UL1 transitions from the "L" level to the "H" level, but the data transmission path 100 is empty. The period until the state changes and data transmission resumes is UK1.
2 holds the "L" level. Therefore,
The Q2 output of the C element 13 remains at the "L" level, and the D type flip-flop 15 is maintained in the reset state via the AND gate 14. Therefore, in the same way as when the data transmission path 100 and its preceding stage are clogged,
0 is not activated and the input data remains stored in register 5 of path 1 and is not transmitted.

Thereafter, when the data transmission line 100 itself resumes data transmission and becomes empty, UK12 changes from the "L" level to the "H" level. In response, the Q1 output of C element 13 transitions to “L” level, its Q2 output transitions to “H” level, and the data stored in register 11 is transmitted to data transmission path 100. Furthermore, the Q of the C element 13
The second output enables UL1 input to the other input terminal of the AND gate 19 and outputs an "H" level, and therefore enables the identifier input to the other input terminal of the AND gate 18. AND gate 18 outputs an "H" level signal.

The output of the AND gate 18 is applied to the clock pulse input terminal CP1 of the D-type flip-flop 15, and the D-type flip-flop 15 is set on its rising edge to the "H" level. That is, D type flip-flop 1
The Q1 output of 5 transitions to “H” level, and the AND
is applied to gate 17. In response, the AND gate 17 validates the identifier input to the other input terminal, outputs an "H" level signal, and connects the C element 1.
Give to 2. As a result, the Q1 output of the C element 7, which was holding the "H" level, is accepted by the C element 12 for the first time at this point, and the data stored in the register 5 is independently branched to the control unit 10. and transmitted.

As mentioned above, in this embodiment, when data is input to the data transmission path 1, the control unit 1
0, the data transmission path 100 and its tip or the control unit 20, the data transmission path 200, and at least one of its preceding transmission paths is in a clogged state;
UK12 and UL1 are “L” level or UK2
2 or UL2 is at “L” level, the input data is held in the data transmission path 1 and the control unit 1
Branched to 0 or 20 and not transmitted. but,
When the previous stage of the data transmission path 100 or 200 resumes data transmission, and the data transmission path 100 or 200 itself completes data transmission to the next stage,
Either UL1, UK12 or UL2, UK22 transitions to "H" level. As a result, data that has been kept waiting on the data transmission path 1 is independently branched and transmitted to the input control section 10 or 20.

FIG. 4 is a schematic block diagram of an embodiment in which data is divided into four branches and transmitted. The example shown in Figure 4 is
The example shown in FIG. 1 above has two data transmission paths 1.
00, 200, but four data transmission lines 100, 200, 200,
300 and 400 for transmission. For this reason, each data transmission line 10
Control units 10, 20, 30 and 40 are provided corresponding to numbers 0, 200, 300 and 400, respectively. In addition, in order to branch and transmit the data to the four data transmission paths 100, 200, 300 and 400, the identifier decoding section 3 sends an identifier to the control sections 10, 20, 30 and 40 to specify each of them.
give to

Further, a NOR gate 4a is provided to determine whether all the control units 10, 20, 30, and 40 are in an empty state. This fourth
In the embodiment shown in the figure, data transmission lines 100, 20
0, 300 and 400 are all empty,
UK12, UK when data transmission is possible
22, UK32 and UK42 are provided to control units 10, 20, 30 and 40, respectively. In addition, UL1, UL2, UL3 and UL4 of the preceding stages of data transmission lines 100, 200, 300 and 400
Similarly, the control units 10, 20, 3
0 and 40. UL1, UL2, UL
3 and UL4 are data transmission paths 100, 200,
This is a signal given from any preceding stage of 300 and 400, and is a signal indicating that the data transmission path is empty and data transmission is possible.

The control units 10, 20, 30 and 40 are respectively UK12 and UL1, UK22 and UL2,
When UK32 and UL3, UK42 and UL4 are input, it is confirmed that the data transmission paths 100 and 100's first stage, 200 and 200's first stage, 300 and 300's first stage, and 400 and 400's first stage are respectively empty. It is determined, and if the data is held, the data is transmitted to the next stage. Then, it enters an active state that enables branch control for subsequent input data.

The NOR gate 4a includes control units 10, 20, 30
When a determination signal indicating that each control section is in an empty state and activated is inputted from 40 and 40, an AK signal is applied to data transmission line 1 and identifier transmission line 2. In this way, the UK received signals and
Based on the UL signal, data transmission lines 100, 200, 300, and 40 are transmitted from branch control units 10, 20, 30, and 40 depending on whether the previous stage is empty or clogged.
0, and control units 10, 20, 3 from the data transmission position.
Allow or disallow branching and transmission to 0 or 40.

From the identifier transmission path 2, an identification signal indicating which data should be transmitted to the identifier decoding section 3 is given to one of the control sections 10, 20, 30, and 40. For example, when an identification signal is given to the control unit 30, the control unit 30 enables data from the data transmission path 1 to be transmitted to the data transmission path 300. Also, for example, the control units 20, 40
When the identification signal is given to the data transmission path 20, the control unit 20 transfers the data from the data transmission path 1
0, and the control unit 40 enables the data to be transmitted to the data transmission path 400.

If, for example, the data transmission path 100, 200, 300, and 400 and any of the preceding data transmission paths,
When the UK 12 is holding data or is transmitting data, the UK 12 is not provided to the control unit 10. Similarly, even when the previous stage of the data transmission path 100 is holding data or is transmitting data, UL1 is not applied to the control unit 10.
For this reason, the control unit 10 determines whether the previous stage of the data transmission paths 100 or 100 is transmitting or is in a clogged state, stores the data input to the register 11 of the control unit 10, and stores the data input to one of the NOR gates 4a. An “H” level signal is applied to the input terminal of the Therefore, the NOR gate 4a is closed,
The AK signal is transmitted to data transmission path 1 and identifier transmission path 2.
cannot be given to

That is, data transmission paths 100, 200, 30
0 and 400 and any of their preceding data transmission paths hold data or are transmitting data, and the control units 10, 20, 30, and 40
holds data, the subsequent data transmitted to the data transmission path 1 is transmitted to the control unit 10,
It is not input to 20, 30 and 40 and is held on data transmission path 1. However, data transmission line 10
0, 200, 300 and 400 and their preceding stages, and the control units 10, 20, 30 and 40,
When the data transmission is completed and the state changes from the jammed state to the empty state, the control units 10, 20, 30 and 40
is activated, and the data input held on the data transmission path 1 can be independently branched and transmitted again according to the identifier.

FIG. 5 is a concrete circuit diagram of an embodiment in which packet data is divided into four branches in an arbitrary order and transferred to an arbitrary branch path. In this example, the
Without using UL signals 10d, 20d, 30d and 40d, that is, data transmission lines 100, 20
A case will be described in which selective branching occurs only in response to empty/clogged states of 0, 300, and 400. In this embodiment, four data transmission paths 10
To identify each of 0, 200, 300 and 400, an identifier is included as part of the data and consists of 2 bits. This 2-bit identifier is given to the identifier decoding section 3. The identifier decoder 3 outputs four identification signals DC1, DC2, DC3 and DC4 based on the 2-bit identifier. And these identification signals DC1, DC2,
DC3 and DC4 are control units 10, 20, respectively.
30 and 40.

The control units 10, 20, 30 and 40 are respectively constructed in the same manner as in the embodiment shown in FIG.
8 is commonly given the Q1 output of the C element 7. This makes it possible to transmit data to the same branch path two or more times in succession. That is, the control section 30 controls the register 31 and the C element 3.
2 and 33, an AND gate 34, a D-type flip-flop 35, a delay element 36, and AND gates 37 and 38.

Similarly, the control section 40 also has a register 41, C elements 42, 43, AD gate 44, D type flip-flop 45, delay element 46, AND
It consists of gates 47 and 48. Furthermore, in order to permit data transmission to the data transmission path 1 when all of the control units 10, 20, 30 and 40 of the 4 are in the selectable state, the 4 input
A NOR gate 4a is provided. That is, this four-input NOR gate 4a has Q1 of the C element 12.
Output, Q1 output of C element 22, Q1 of C element 32
output and the Q1 output of the C element 42 are given, and when both of these outputs are at the “L” level, the “H” level
A level AK signal is given to the C element 7 and can be transmitted to the input data register 5.

In the four-branch data transmission device configured as described above, after initialization by the reset signal, when the pulse signal Co is applied to the C element 6, the pulse signal is transmitted to the C element 7, and the pulse signal is sent to the register 5. Given. The register 5 stores data at the rising timing of the pulse signal. Among the data stored in the register 5, the 2-bit identifier is given to the identifier decoding section 3 and decoded. At this time, as the output of the identifier decoding section 30,
For example, if the identification signal DC4 is activated and applied to the AND gate 48, when the delayed signal of the Q2 output of the C element 43, which is the remaining input terminal of the AND gate, is at "H" level, the AND gate 48
The output becomes "H" level and is applied to the clock input terminal CK of the D-type flip-flop 45. Therefore, the D type flip-flop 45
is set, and one input of C element 42 is brought to the "H" level via AND gate 47. Thereby, the pulse signal output from the C element 7 is C
The pulse signal is transmitted to elements 42 and 43, and a pulse signal is applied to register 41. At the rising edge of the pulse signal, the data stored in the register 5 is stored in the register 41, and the data transmission line 400
transmission becomes possible.

Further, when the identifier for selecting the data transmission path 300 is given to the identifier decoding section 3, the identifier decoding section 3 outputs the identification signal DC3, and the data stored in the register 5 by the control section 30 is transmitted. It becomes possible to transmit the data to the route 300. Similarly, when an identifier for transmitting data to the data transmission path 200 is given to the identifier decoder 3, the identification signal DC2 is output, and the data stored in the register 5 by the control circuit 20 is changed to Transmission line 20
It becomes possible to transmit to 0. When an identification signal for transmitting data to the data transmission path 100 is given to the identifier decoding section 3, an identification signal DC1 is output, and the data stored in the register 5 by the control circuit 10 is transmitted to the data transmission path 100. It becomes possible.

Note that in the above description, four transmission lines 100,
Although data can be transmitted to any one of 200, 300, and 400, the present invention is not limited to this, and data can also be transmitted in parallel to two or more data transmission paths. In that case, the identifier decoder 3 may be configured so that the identifier decoder 3 can commonly output an identification signal for identifying a plurality of transmission paths to which transmission is desired.

In this way, when data is sequentially input to data transmission path 1, data transmission paths 100, 2
The operation when a blockage occurs at 00, 300, and 400, and the operation when the data transmission line resumes data transmission and becomes empty, are completely different from the two-branch case shown in FIG. Since they are similar, the explanation will be omitted, but the transmission line itself still independently performs branching and transmission control.

As described above, in this embodiment, when data is input to the data transmission path 1, the data transmission path 10
At least one of 0, 200, 300 and 400 is clogged, UK12, UK22,
At least one of UK32 and UK42 is at "L" level, and the control units 10, 20,
If at least one of 30 or 40 is clogged, the input data is held in data transmission path 1 and is not branched and transmitted to control section 10, 20, 30 or 40. However, when data transmission to the next stage of at least one of the aforementioned four data transmission paths is completed, the corresponding signal among the aforementioned four UK signals transitions to the "H" level, and the data The data that was kept waiting on the transmission path 1 is transferred to the control units 10, 20, 3 according to the tag data.
It is independently branched into either 0 or 40 and transmitted.

FIG. 6 is a specific circuit diagram of another embodiment in which packet data is divided into four branches in an arbitrary order and transmitted to arbitrary branch paths. In this example, the third
Using the UL signals 10d, 20d, 30d and 40d shown in the figure, that is, the data transmission line 10
0, 200, 300, and 400, and a case where the branches are selectively branched according to the empty/clogged state of the preceding stages will be described. In this embodiment, in order to identify the four data transmission paths, the identifier is included in a part of the data and consists of 2 bits, similar to the embodiment shown in FIG. This 2-bit identifier is outputted by the identifier combining section 3 as four identification signals DC1, DC2, DC3 and DC4. And these identification signals DC1, DC2,
DC3 and DC4 are control units 10, 20, respectively.
30 and 40.

The control section 10, 20, 30 or 40 is constructed in substantially the same manner as the embodiment shown in FIG.
6 differs only in that it is replaced with AND gates 19, 29, 39 and 49 in the embodiment shown in FIG.

In the four-branch data transmission device configured as described above, the operation after initialization by the reset signal is exactly the same as that of the embodiment shown in FIG. 5, so a detailed explanation of the operation will be omitted. .

Also, when data is input to data transmission path 1 in sequence, data transmission paths 100, 200, 30
0 or 400 and any one of their predecessors
Regarding the operation when one transmission line becomes clogged, and the operation when the data transmission line resumes data transmission and becomes empty, see Section 3 above.
Since this is exactly the same as the two-branch case shown in the figure, its explanation will be omitted, but the fact remains that the transmission line itself branches autonomously and performs transmission control.

As mentioned above, in this embodiment, when data is input to data transmission line 10,
At least one data transmission path among 0, 200, 300, and 400 and their preceding stages is clogged, and UL1, UL2, UL3, and UL
4 or UK12, UK22, UK32 and UK
42 is at the "L" level and at least one of the control units 10, 20, 30, or 40 is clogged, the input data is held in the data transmission path 1, and the control units 10, It is not branched to 20, 30 or 40 and transmitted. However, when at least one of the aforementioned transmission paths completes data transmission to the next stage of each data transmission path, the aforementioned four UL signals and four
The corresponding signal among the UK signals transitions to the "H" level, and the data that was waiting on the data transmission path 1 is autonomously transferred to any one of the control units 10, 20, 30, or 40 according to the tag data. It is branched and transmitted.

[Effects of the Invention] As described above, according to the present invention, it is determined whether or not a transmission permission signal is output from each of a plurality of parallel transmission paths, and a part of data or Data is transmitted independently to one of the transmission paths according to the identifier for specifying the transmission path associated with the data, and depending on whether the previous transmission path is empty or clogged. Even if different types of data are input asynchronously, each data can be transmitted independently through the desired transmission path, eliminating the need for wiring or high-performance input/output ports for each type of data. , the device can be easily configured. Therefore, if this invention is applied to, for example, packet communication, the content of the packet can be divided into parallel data transmission paths, and the data can be combined in an order different from the one in which it was divided. It is also possible to sort them in order.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of an embodiment in which data is divided into two branches and transmitted. FIGS. 2 and 3 are specific circuit diagrams of an embodiment in which data is divided into two branches. FIG. 4 is a schematic block diagram of an embodiment in which data is divided into four branches and transmitted. FIGS. 5 and 6 are specific circuit diagrams of an embodiment in which data is divided into four branches and transmitted. In the figure, 1,100,200,300,4
00 is a data transmission path, 2 is an identifier transmission path, 3 is an identifier decoding section, 10, 20, 30, 40 is a control section,
5, 11, 21, 31, 41 are registers, 2, 1
5, 25, 35, 45 are D type flip-flops, 6, 7, 12, 13, 22, 23, 32, 3
3, 42, 43 are C elements, 4, 4a are NOR gates, 14, 24, 34, 44, 17, 27, 3
7, 47, 18, 28, 38, 48, 19, 2
9, 39, 49 are AND gates, 16, 26, 3
6 and 46 indicate delay elements.

Claims (1)

[Claims] 1. Each of them is provided in parallel and holds data from the latter stage in response to outputting a transmission permission signal to the latter stage, and retains data in response to outputting a transmission permission signal from the former stage. Multiple output side data transmission lines that output
An input that receives data from the subsequent stage and a part of the data or an identifier for specifying a transmission path associated with the data, and outputs the data and identifier to the previous stage in response to a transmission permission signal given from the previous stage. side data transmission path; determining means for determining whether a transmission permission signal is output from each of the plurality of output side data transmission paths; and output side data transmission represented by an identifier given from the input side data transmission path. input control means for controlling the output side data transmission path to permit reception of data in response to the determination by the determination means that data transmission is possible through the transmission path; When the determining means determines that data can be transmitted to the corresponding output data transmission path, the data from the input data transmission path is transferred to one of the output data transmission paths. A data transmission device equipped with an output control means for transmitting data to 2. The output control means, in response to the determination means determining that all of the plurality of parallel transmission paths are enabled for transmission, displays a part of the data or an identifier attached to the data. The data is sent to the transmission path that is
A data transmission device according to claim 1. 3. The input control means and the output control means each include transmission path selection signal output means for outputting a transmission path selection signal indicating which of the plurality of parallel transmission paths data should be transmitted to, based on the identifier; a storage means provided corresponding to each of the plurality of parallel transmission paths, for storing the data when the data transmission is permitted; and a storage means provided corresponding to each of the plurality of parallel transmission paths; and a determination signal for determining that a transmission permission signal has been given to the transmission line in question is given from the discrimination means, and a transmission line selection signal for selecting the transmission line is given from the transmission line selection means. 2. The data transmission device according to claim 2, further comprising a transmission control means for storing the data whose input is permitted in a storage means corresponding to the transmission path in response to the transmission path, and transmitting the data to the transmission path. . 4. The data according to claim 1, wherein the input control means is configured to intermittent the identifier based on a clock signal when identifiers for selecting the same transmission path are consecutively given. Transmission device.