JPH0564827B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an inter-processor communication device that reduces the communication load between processors.

[Conventional technology]

FIG. 2 shows an example of a conventional inter-processor communication method. There are two processors 1 and 2, and processor 1 sends a write signal 7 and write data 6 to processor 2 only when processor 2 generates an input permission signal 8. Processor 1 will be referred to as a transmitting processor, and processor 2 will be referred to as a receiving processor.

The transmitting processor 1 and the receiving processor 2 often have different processing speeds. Therefore, accurate synchronization means are required.

A conventional example from this point of view is JP-A-61-138357. JP-A-61-138357 is an example in which a FIFO memory is provided on the receiving processor side to achieve synchronization.

[Problem to be solved by the invention]

JP-A-61-138357 aims to synchronize communication between two processors. Therefore, synchronization between a single transmitting processor and multiple receiving processors is not considered. In particular, in this multiprocessor system, the receiving processor has to perform transmission processing every time the input permission signal 8, which is a response of the receiving processor, is generated. As a result, the time required for transmission processing at the transmitter processor increases, resulting in what is called an increase in load.

SUMMARY OF THE INVENTION An object of the present invention is to provide an interprocessor communication device that can reduce the communication load between processors in a multiprocessor system, that is, the transmission load on a transmitting processor.

[Means to solve the problem]

The present invention performs an AND operation between a clock generator that generates a clock of a fixed period and the above-mentioned clock for each input enable signal of a FIFO register corresponding to a receiving processor, and then performs an OR operation on the result of the AND operation. Means for issuing a transmission request interrupt to the transmitting processor when the logical sum result is "1" is provided.

[Effect]

The transmitting processor receives the transmitting interrupt when the OR output is "1", and causes the transmitting interrupt to be transmitted to the receiving processor. At this time, "1" is synchronized with the clock and with the input permission signal of the receiving processor. By this,
Synchronization of the sending and receiving processors with each other can be achieved. Moreover, the transmission processing load on the transmitting processor can be reduced.

〔Example〕

FIG. 1 shows an embodiment of a multiprocessor system according to the present invention. In this system, one processor device 1 constitutes a transmitting section, and two processor devices 2 and 2A constitute a receiving section. Of course, the number of receiving sections is often three or more.

The processor device 1 includes a transmitting processor 14
, a clock pulse generator 3, and a logic gate 4.

The novel part is the provision of a generator 3 and a logic gate 4.

The processor devices 2 and 2A have the same configuration, and each has a receiving processor 15 and a FIFO memory (register). However, the capacity of the FIFO memory and the content after receiving processing may differ.

Further, in the processor devices 2 and 2A, the FIFO memory 5 generates input enable signals 8 and 8A, which are input to the logic gate 4 together with the clock 9. The output of the logic gate 4 becomes an interrupt input to the transmitter processor 14 as a transmission request signal 10. The sending processor 14 receives the sending request signal 10 and sends out write command signals 7, 7A and sending data 6, 6A. The FIFO memory 5 generates a read permission signal 11 and inputs an interrupt to the receiving processor 15, and the receiving processor 15 generates a read command signal 12.
is sent to the FIFO memory 5, and read data 13 is received.

The overall operation will be explained. Use the time chart shown in Figure 2.

It is assumed that the transmitting processor 14 has transmission data and is ready for transmission at any time. Under such conditions, when the input permission signals 8, 8A are input from the receiving processors 2, 2A, the transmission request signal 10 is generated by the logic gate 4 in synchronization with the clock 9. This transmission request 10 enters the transmission side processor 14 as an interrupt input, and the transmission side processor 14 immediately sends out write commands 7, 7A and transmission data 6, 6A. Here, 7 and 7A,
6 and 6A have the same content.

FIFO memory 5 receives these commands 7, 7A,
If it has issued an input permission signal, it accepts and latches the transmitted data. If it does not issue an input permission signal, it will not capture received data.

The FIFO memory 5 sends the latched data to the receiving processor 15 and completes the reception.

FIG. 4 is a diagram showing a detailed embodiment of the processor device 1, and FIG. 5 is a diagram showing a detailed embodiment of the processor device 2.

In FIG. 4, the clock oscillator 3 consists of a clock generation source 24 and a frequency dividing circuit 25.
The pulse output frequency-divided by 5 becomes the clock signal 9. The period of this clock signal (or interval clock signal) is determined by the transfer rate between processor devices 1 and 2.

Logic 4 is a flip-flop (FF)
19, 18, 18A, reception buffer 17, 17
A, AND gate 20, 20A, OR gate 24
Consists of. FF18, 18A is input permission signal 8,
Temporarily latch 8A. and gate 20,
20A is the clock signal 9 obtained from FF19.
and the input permission signals 8, 8A obtained from the FFs 18, 18A. or gate 20
B takes the logical sum of the outputs of the AND gate 20A, and at least one of the outputs is "1",
A transmission request signal 10 is generated. This transmission request signal 10 serves as an interrupt input to the transmitting side processor 14, and after receiving this interrupt, the processor 14 executes the transmitting process. That is, the processor 14
When receiving the transmission request signal 10 as an interrupt, it sends out the write command signals 7 and 7A via the transmission buffer 22, and also sends out the transmission data 6 and 6A via the transmission buffer 21.

On the other hand, in the receiving side processor device 2, the write command signal 7 and the transmission data 6 are sent to the receiving buffers 28, 2.
Receive via 7. At this point, FIFO memory 5
If the input permission signal terminal IR is “1”, the system sends the input permission signal to the sending processor device 1 via the sending buffer 29, so it does not send the write command 7 via the buffer 28. The received data 6 is taken in through the buffer 27 and latched.

On the other hand, if the signal end IR is "0", it means that the system is not the system that sent the input permission signal, so the transmission data 6
It is not latched and is abandoned. Here, the signal end
IR becomes "1" when a blank area occurs inside the FIFO memory 5.

Each time data is written to the FIFO memory 5,
A read permission signal 11 is generated from the read permission signal terminal OR. This permission signal 11 is input to the receiving processor 15 as a write signal, and the processor 1
5 generates a read command signal 12. Upon receiving this command signal 12, the FIFO memory 5 reads out the earliest stored data 13 according to the FIFO method, and the receiving processor 15 receives this data 13. Note that the reset signal 16 is sent to the memory 5 and the receiving processor 15.
For example, it is used to reset the system to the initial state at startup.

The above is a general flow of operations in FIGS. 4 and 5, and a more specific explanation will be provided.

When the internal reset is performed, the processor 1 outputs the transmitting side processor 14, the SR flip-flop 18,
DT flip-flop 19 is in the initial state, and SR
The 1 output of the flip-flop 18 and the 0 output of the DT flip-flop 19 are output, and the AND gate 20
If there is data to be transferred, the transmitting side processor 14 is interrupted via the transmitting side processor 14, and if there is data to be transferred, a program for transmitting the transferred data is executed. As a result, the transfer data signal 6
This write signal 7 is output from transmission buffers (driver circuits) 21 and 22. On the other hand, the 1 output of the SR flip-flop 18 and the 0 output of the DT flip-flop 19 are canceled by the write signal from the transmitting side processor 14, and the interrupt factors from the AND gate 20 and OR gate 20B disappear, and the transfer data signal 6 and this Write signal 7 is sent to driver circuit 21
Stop output from. When the internal reset is performed, the processor 2 communicates with the receiving processor 15.
The FIFO memory 5 is in its initial state. After this, the transfer data signal 6 from the processor 1 and this write signal 7 are transferred to the receiver circuit (buffer) 17 or 17.
When input from A, the FIFO memory 5 stores the transfer data signal in response to this write signal and stops outputting the input permission signal 8 from the driver circuits 21 and 22. When the FIFO memory 5 completes storing the transfer data signal, if a blank area remains, the driver circuits 21 and 22 output the input permission signal 8 again. As a result, the 0 output of the SR flip-flop 18 of the processor 1 is output again. on the other hand,
The FIFO memory 5 outputs a read permission signal 11 indicating the data storage state to the receiving processor 15.
The receiving processor 15 receives this read permission signal 11.
, and executes a program for receiving transfer data from the processor 1. Due to this
Outputs read signal 12 to FIFO memory 5,
The FIFO memory 5 outputs the read data signal 13 and stops outputting the read permission signal 11, the interrupt factor disappears, and the read signal 12 also stops being output.

On the other hand, the frequency dividing circuit 25 that divides the output of the oscillation source 24 of the processor 1 to the transfer rate outputs the interval pulse signal 9 according to the transfer rate.
DT flip-flop 19 is triggered and a 0 output is output again. As a result, the AND condition for one output of the SR flip-flop 18 is satisfied for the first time, and an interrupt is executed again to the transmitting processor 14. Note that a typical example of transmission data is transmission data in broadcast communication. However, it can also be applied to general communications other than broadcast communications.

〔Effect of the invention〕

According to the present invention, the transmitting side processor executes the transmission processing program for the data to be transferred by the interval pulse signal, and can execute programs other than transmission processing during the time when there is no interval pulse signal. As a result, the transmission rate can be made constant and synchronized, and the transfer processing load on the transmitting processor can be reduced.

[Brief explanation of the drawing]

Fig. 1 is an embodiment of the overall system of the present invention, Fig. 2 is a conventional example, Fig. 3 is a time chart, and Fig. 4 is a diagram of a conventional example.
The figure shows an embodiment of a transmitting processor, and FIG. 5 shows an embodiment of a receiving processor. 1... Transmission side processor device, 2... Receiving side processor device, 3... Clock pulse generator, 4
...Logic gate, 5...FIFO memory, 14...
Transmitting side processor, 15...Receiving side processor.

Claims (1)

[Claims] 1. A transmitting processor, a plurality of receiving processors, a clock generator that generates a clock with a constant cycle, a FIFO memory corresponding to each receiving processor, and a plurality of receiving processors.
Means for performing an AND with the clock for each input enable signal of the FIFO memory, taking a logical sum of the results of each logical product, and issuing a transmission request interrupt to the sending processor when the logical sum result is "1"; an inter-processor communication device comprising: means for transmitting the transmission data output from the transmitting processor in response to the interrupt to each of the FIFO memories; and means for transmitting the read data read from each FIFO memory to the corresponding receiving processor. . 2. The inter-processor communication device according to claim 1, wherein the FIFO memory that receives the transmission data outputted from the transmission side processor excludes the acquisition of the data if the FIFO memory itself does not issue an input permission signal.