JPH0565060B2 - - Google Patents
Info
- Publication number
- JPH0565060B2 JPH0565060B2 JP672287A JP672287A JPH0565060B2 JP H0565060 B2 JPH0565060 B2 JP H0565060B2 JP 672287 A JP672287 A JP 672287A JP 672287 A JP672287 A JP 672287A JP H0565060 B2 JPH0565060 B2 JP H0565060B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon film
- polycrystalline silicon
- ion implantation
- ions
- oxygen ions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 29
- -1 oxygen ions Chemical class 0.000 claims description 13
- 238000005468 ion implantation Methods 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 12
- 229910052760 oxygen Inorganic materials 0.000 claims description 11
- 239000001301 oxygen Substances 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 11
- 239000012535 impurity Substances 0.000 claims description 10
- 150000002500 ions Chemical class 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 229910052785 arsenic Inorganic materials 0.000 claims description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 5
- 229910052796 boron Inorganic materials 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- 238000001947 vapour-phase growth Methods 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 2
- 229910021419 crystalline silicon Inorganic materials 0.000 claims 1
- 238000007796 conventional method Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に高
抵抗の多結晶シリコン膜を高精度に、かつ、再現
性よく形成する方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming a high-resistance polycrystalline silicon film with high precision and good reproducibility.
半導体装置の微細化、高密度化に伴い、素子の
電気的特性の高精度化が強く求められている。そ
の中でも抵抗層の形成は、従来、半導体基板の所
望領域に、不純物イオンをイオン注入法により添
加する方法か、あるいは現圧CVD法で絶縁膜上
に多結晶シリコン膜を形成し、その後膜中に隣、
砒素、硼素等の不純物イオンを熱拡散法あるいは
イオン注入法により添加することにより形成して
いた。
As semiconductor devices become smaller and more dense, there is a strong demand for higher precision in the electrical characteristics of elements. Conventionally, the formation of a resistance layer has been carried out by adding impurity ions to a desired region of a semiconductor substrate by ion implantation, or by forming a polycrystalline silicon film on an insulating film by current pressure CVD, and then forming a polycrystalline silicon film on an insulating film. next to,
It is formed by adding impurity ions such as arsenic and boron by thermal diffusion or ion implantation.
〔発明が解決しようとする問題点〕
しかるに上述した従来の抵抗層の形成方法は、
特に多結晶シリコン膜を用いて抵抗層を形成する
場合には、抵抗値の不純物注入量依存性が非常に
強く、添加量を少し変えただけで抵抗値が大きく
変化すること、又抵抗値の上限に限界が存在する
ことにより高精度の高抵抗を得ることは不可能で
あつた。[Problems to be solved by the invention] However, the above-mentioned conventional method for forming a resistive layer is
In particular, when forming a resistance layer using a polycrystalline silicon film, the resistance value has a very strong dependence on the amount of impurity implanted. Due to the existence of an upper limit, it has been impossible to obtain a high resistance with high precision.
本発明の目的は多結晶シリコン膜を用いて高抵
抗の抵抗領域を形成しうる半導体装置の製造方法
を提供することにある。 An object of the present invention is to provide a method for manufacturing a semiconductor device in which a high resistance region can be formed using a polycrystalline silicon film.
上述した従来の多結晶シリコン膜を用いた抵抗
層の形成方法に対し、本発明は多結晶シリコン膜
に酸素イオンをイオン注入法で最初に添加してお
き、その後所望の不純物をイオン注入法で添加す
ることにより高抵抗で、かつ高精度の再現性を有
する多結晶シリコン膜が得られるという独創的内
容を有する。
In contrast to the above-described conventional method for forming a resistance layer using a polycrystalline silicon film, the present invention first adds oxygen ions to the polycrystalline silicon film by ion implantation, and then adds desired impurities to the polycrystalline silicon film by ion implantation. It has the original content that by adding it, a polycrystalline silicon film with high resistance and high precision reproducibility can be obtained.
本発明は半導体素子が形成された半導体基板上
に減圧気相成長法により多結晶シリコン膜を形成
する工程と、該多結晶シリコン膜に酸素イオンを
イオン注入法を用いて添加する工程と、該多結晶
シリコン膜を熱処理する工程と、多結晶シリコン
膜に隣、砒素、硼素等の不純物イオンをイオン注
入法により添加する工程と、該多結晶シリコン膜
に熱処理を施す工程とを含むことを特徴とする半
導体装置の製造方法である。
The present invention includes a step of forming a polycrystalline silicon film on a semiconductor substrate on which a semiconductor element is formed by a low pressure vapor phase growth method, a step of adding oxygen ions to the polycrystalline silicon film using an ion implantation method, and a step of adding oxygen ions to the polycrystalline silicon film using an ion implantation method. It is characterized by comprising the steps of heat treating a polycrystalline silicon film, adding impurity ions such as arsenic or boron to the polycrystalline silicon film by ion implantation, and heat treating the polycrystalline silicon film. This is a method for manufacturing a semiconductor device.
次に、本発明について図面を参照して説明す
る。
Next, the present invention will be explained with reference to the drawings.
第１図ａ，ｂは本発明の一実施例を説明するた
めの工程を工程順に示す断面図である。 FIGS. 1a and 1b are cross-sectional views showing steps in order to explain an embodiment of the present invention.
まず第１図ａに示すように３〜15Ω・cmの抵抗
値を有するＰ型半導体基板１１上に熱酸化膜１２
を形成した後、膜厚0.5μｍの多結晶シリコン膜１
３を形成する。続いて、多結晶シリコン膜１３中
に全面にイオン注入法により、1014〜1016／cm2の
酸素イオン１４を導入する。その後800〜1000℃
の高温で熱処理を行う。 First, as shown in FIG.
After forming, a polycrystalline silicon film 1 with a thickness of 0.5 μm is formed.
form 3. Subsequently, oxygen ions 14 of 10 14 to 10 16 /cm 2 are introduced into the entire surface of the polycrystalline silicon film 13 by ion implantation. Then 800~1000℃
Heat treatment is performed at high temperatures.
次に同図ｂに示すように、フオトレジスト１５
を形成して所望領域を開孔し、フオトレジスト１
５上から隣、砒素、硼素等の不純物イオン１６を
イオン注入法により導入し、その後注入されたイ
オンの活性化のための熱処理を行う。この場合、
多結晶シリコン膜に不純物イオンを注入するの
は、第１図ｂに示したフオトレジストをマスクと
した場合について述べたが、多結晶シリコン膜を
所望の形状にパターニングした後に全面に不純物
イオンの注入を行つてもよい。 Next, as shown in FIG.
A hole is formed in the desired area, and photoresist 1 is formed.
Impurity ions 16 such as arsenic, boron, etc. are introduced from above 5 by ion implantation, and then heat treatment is performed to activate the implanted ions. in this case,
Implantation of impurity ions into a polycrystalline silicon film was described using the photoresist as a mask shown in Figure 1b, but after patterning the polycrystalline silicon film into a desired shape, impurity ions are implanted over the entire surface. You may do so.
第２図は第１図ａ，ｂの工程を終えた後と多結
晶シリコン膜の抵抗値Ｒと隣イオンの注入量との
関係を示すものである。図中Ａは酸素イオンを
1014／cm2注入した結果であり、Ｂは1016／cm2注入
した場合、Ｃは注入なしの結果である。燐イオン
の注入量の増加に伴い抵抗値は下がる傾向を示し
ているが、抵抗値は前工程で注入される酸素イオ
ンの注入量により決定される。1014／cm2の注入量
の試料より1016／cm2注入した試料の方が一桁程度
高い抵抗値を示している。 FIG. 2 shows the relationship between the resistance value R of the polycrystalline silicon film and the amount of adjacent ion implantation after completing the steps shown in FIGS. 1a and 1b. In the diagram, A represents oxygen ions.
These are the results when 10 14 /cm 2 were implanted, B is the result when 10 16 /cm 2 was implanted, and C is the result without implantation. Although the resistance value tends to decrease as the amount of phosphorus ions implanted increases, the resistance value is determined by the amount of oxygen ions implanted in the previous step. The sample with an injection amount of 10 16 /cm 2 has a resistance value that is about one order of magnitude higher than the sample with an injection amount of 10 14 /cm 2 .
本発明の方法により形成された高抵抗多結晶シ
リコン膜は、通常のMOSトランジスタ作製工程
に従い、最終の配線、カバー工程へと進められ、
高精度の高抵抗値を具備した集積回路が完成す
る。 The high-resistance polycrystalline silicon film formed by the method of the present invention is advanced to the final wiring and cover process according to the usual MOS transistor manufacturing process.
An integrated circuit with high precision and high resistance value is completed.
以上説明したように本発明によれば、従来法に
加え、半導体基板表面に形成された多結晶シリコ
ン膜にイオン注入法を用いて酸素イオンを添加す
ることにより、従来得られなかつた安定な高抵抗
の抵抗層が得られ、集積回路の設計、製造に大き
な効果がある。
As explained above, according to the present invention, in addition to the conventional method, by adding oxygen ions to the polycrystalline silicon film formed on the surface of the semiconductor substrate using the ion implantation method, stable high temperature A resistive layer of resistance can be obtained, which has great effects on the design and manufacture of integrated circuits.
第１図ａ，ｂは本発明の一実施例を説明するた
めの工程断面図、第２図は第１図で得られた多結
晶シリコン膜の抵抗値と不純物注入量の関係を、
酸素イオンの添加量をパラメータとして示した図
である。
１１……シリコン基板、１２……酸化膜、１３
……多結晶シリコン膜、１４……酸素イオン、１
５……フオトレジスト膜、１６……隣、砒素又は
硼素イオン。
Figures 1a and b are process cross-sectional views for explaining one embodiment of the present invention, and Figure 2 shows the relationship between the resistance value of the polycrystalline silicon film obtained in Figure 1 and the amount of impurity implanted.
FIG. 3 is a diagram showing the amount of oxygen ions added as a parameter. 11...Silicon substrate, 12...Oxide film, 13
... Polycrystalline silicon film, 14 ... Oxygen ion, 1
5... Photoresist film, 16... Adjacent, arsenic or boron ion.
Claims (1)
気相成長法により多結晶シリコン膜を形成する工
程と、該多結晶シリコン膜に酸素イオンをイオン
法入法を用いて添加する工程と、該多結晶シリコ
ン膜を熱処理する工程と、多結晶シリコン膜に
隣、砒素、硼素等の不純物イオンをイオン注入法
により添加する工程と、該多結晶シリコン膜に熱
処理を施す工程とを含むことを特徴とする半導体
装置の製造方法。1 A step of forming a polycrystalline silicon film by low pressure vapor phase growth on a semiconductor substrate on which a semiconductor element is formed, a step of adding oxygen ions to the polycrystalline silicon film using an ion deposition method, and a step of adding oxygen ions to the polycrystalline silicon film using an ion deposition method; It is characterized by comprising the steps of heat treating the crystalline silicon film, adding impurity ions such as arsenic or boron to the polycrystalline silicon film by ion implantation, and heat treating the polycrystalline silicon film. A method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP672287A JPS63174349A (en) | 1987-01-13 | 1987-01-13 | Mamufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP672287A JPS63174349A (en) | 1987-01-13 | 1987-01-13 | Mamufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63174349A JPS63174349A (en) | 1988-07-18 |
| JPH0565060B2 true JPH0565060B2 (en) | 1993-09-16 |
Family
ID=11646150
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP672287A Granted JPS63174349A (en) | 1987-01-13 | 1987-01-13 | Mamufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63174349A (en) |
-
1987
- 1987-01-13 JP JP672287A patent/JPS63174349A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63174349A (en) | 1988-07-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4125426A (en) | Method of manufacturing semiconductor device | |
| JPS61179567A (en) | Manufacture of self-aligning laminated cmos structure | |
| JPH0640582B2 (en) | Method for manufacturing insulating gate field effect transistor | |
| JPH0614532B2 (en) | Method for forming a resistor in a polycrystalline semiconductor material | |
| US4502894A (en) | Method of fabricating polycrystalline silicon resistors in integrated circuit structures using outdiffusion | |
| JPH0195552A (en) | Manufacture of monolithic integrated semiconductor device | |
| JPH0565060B2 (en) | ||
| JPH06104384A (en) | High-value resistor and manufacturing method thereof | |
| JP2573021B2 (en) | Method for manufacturing semiconductor device | |
| JPS63292663A (en) | Manufacture of semiconductor device | |
| JPH0536911A (en) | Three-dimensional circuit element and manufacture thereof | |
| JPS61502993A (en) | 3-well CMOS technology | |
| JPS6220711B2 (en) | ||
| JPS5826177B2 (en) | Manufacturing method of semiconductor device | |
| JPS63301554A (en) | Method of forming polycrystalline silicon layer | |
| JP2745946B2 (en) | Method for manufacturing semiconductor integrated circuit | |
| JPS6010657A (en) | Manufacture of resistor | |
| JPS59105366A (en) | Manufacturing method of MOS type transistor | |
| JPS59108354A (en) | Manufacturing method of semiconductor device | |
| JPS592191B2 (en) | Method for manufacturing electrodes for semiconductor devices | |
| JPH0395965A (en) | Complementary type thin-film transistor | |
| JPH07115173A (en) | Method for manufacturing semiconductor integrated circuit | |
| JPS6359259B2 (en) | ||
| JPH0290664A (en) | Manufacture of condenser | |
| JPS5931225B2 (en) | Method of manufacturing integrated circuit device |