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JPH0566030B2 - - Google Patents
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JPH0566030B2 - - Google Patents

Info

Publication number
JPH0566030B2
JPH0566030B2 JP57232402A JP23240282A JPH0566030B2 JP H0566030 B2 JPH0566030 B2 JP H0566030B2 JP 57232402 A JP57232402 A JP 57232402A JP 23240282 A JP23240282 A JP 23240282A JP H0566030 B2 JPH0566030 B2 JP H0566030B2
Authority
JP
Japan
Prior art keywords
contact window
comb
region
drain region
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57232402A
Other languages
Japanese (ja)
Other versions
JPS59117166A (en
Inventor
Takeshi Ando
Yasunobu Okano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP57232402A priority Critical patent/JPS59117166A/en
Publication of JPS59117166A publication Critical patent/JPS59117166A/en
Publication of JPH0566030B2 publication Critical patent/JPH0566030B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]

Landscapes

  • Semiconductor Integrated Circuits (AREA)

Description

【発明の詳細な説明】 本発明はMOS集積回路に関し、特に出力バツ
フアにMOSトランジスタを使用しているMOS集
積回路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a MOS integrated circuit, and more particularly to a MOS integrated circuit using a MOS transistor for an output buffer.

従来、出力バツフアにMOSトランジスタを使
用したMOS集積回路は静電破壊に弱く、特にオ
ープンドレイン出力端子の静電破壊に弱いという
問題がある。その破壊モードは出力バツフア・ト
ランジスタのゲート破壊である。
Conventionally, MOS integrated circuits that use MOS transistors for output buffers have a problem in that they are susceptible to electrostatic discharge damage, and in particular, open drain output terminals are susceptible to electrostatic discharge damage. Its destruction mode is gate destruction of the output buffer transistor.

第1図は従来のMOSトランジスタの一例の平
面図である。
FIG. 1 is a plan view of an example of a conventional MOS transistor.

半導体基板1にソース領域2とドレイン領域3
とが設けられ、その間にチヤンネル領域4が形成
される。表面に絶縁膜が被着された後、ソース領
域2、及びドレイン領域3にそれぞれコンタクト
用窓5,6があけられ、この窓5,6を介してソ
ース電極及びドレイン電極(共に図示せず)が取
付けられる。そしてドレイン電極が出力端子に接
続される。
A source region 2 and a drain region 3 are provided on a semiconductor substrate 1.
and a channel region 4 is formed therebetween. After an insulating film is deposited on the surface, contact windows 5 and 6 are formed in the source region 2 and drain region 3, respectively, and a source electrode and a drain electrode (both not shown) are formed through the windows 5 and 6. is installed. The drain electrode is then connected to the output terminal.

今、このMOSトランジスタのドレインに出力
端子から静電気が印加された場合、ドレイン領域
3のコーナ部で電界集中が生じ、ゲート絶縁膜破
壊を生じる。このゲート破壊を防ぐために、出力
バツフアの電気的特性とは無関係に、トランジス
タのチヤンネル幅がドレインの接合容量とゲート
絶縁膜厚とから決められるという設計基準が採用
されていた。その設計基準ではチヤンネル幅は1
mm以上とすると規定されていた。つまり、出力バ
ツフアの出力の大小に関係なくチヤンネル幅を一
律に定めていたので、出力が小さい場合にはチヤ
ンネル幅は必要以上に大きいものとなりトランジ
スタの寸法を大きくしてしまい、無駄を生ずると
いう欠点があつた。
Now, if static electricity is applied to the drain of this MOS transistor from the output terminal, electric field concentration will occur at the corner of the drain region 3, causing breakdown of the gate insulating film. In order to prevent this gate breakdown, a design standard has been adopted in which the transistor channel width is determined from the drain junction capacitance and the gate insulating film thickness, regardless of the electrical characteristics of the output buffer. According to the design standard, the channel width is 1
It was specified that the diameter should be at least mm. In other words, since the channel width was set uniformly regardless of the magnitude of the output of the output buffer, if the output was small, the channel width would be larger than necessary, which would increase the size of the transistor, resulting in waste. It was hot.

本発明は上記欠点を除去し、出力端子からドレ
イン領域に静電気が印加されたとき生ずる電界集
中を緩和させるドレイン電極構造を採用し、静電
破壊に対する耐性を改良したMOS集積回路を提
供するものである。
The present invention eliminates the above-mentioned drawbacks and provides a MOS integrated circuit that has improved resistance to electrostatic breakdown by adopting a drain electrode structure that alleviates electric field concentration that occurs when static electricity is applied from an output terminal to a drain region. be.

本発明のMOS集積回路は、半導体基板に設け
られたソース領域及びドレイン領域と、前記ドレ
イン領域に設けられチヤンネルの幅方向に平行な
部分を有する第1のコンタクト用窓と、該第1の
コンタクト用窓に設けられた第1のドレイン電極
と、前記第1のコンタクト用窓を挾んで前記チヤ
ンネルと反対側の前記ドレイン領域に設けられ且
つ前記第1のコンタクト用窓の少くとも一部に沿
つて平行に設けられた第2のコンタクト用窓と、
該第2のコンタクト用窓に設けられ且つ出力端子
に接続する第2のドレイン電極とを備えたMOS
トランジスタを含んで構成される。
A MOS integrated circuit of the present invention includes a source region and a drain region provided in a semiconductor substrate, a first contact window provided in the drain region and having a portion parallel to the width direction of a channel, and a first contact window provided in the drain region. a first drain electrode provided in the contact window, and a drain electrode provided in the drain region on the opposite side of the channel across the first contact window and along at least a part of the first contact window. a second contact window provided in parallel;
a second drain electrode provided in the second contact window and connected to the output terminal;
Consists of transistors.

次に、本発明の実施例について図面を用いて説
明する。
Next, embodiments of the present invention will be described using the drawings.

第2図は本発明の一実施例の平面図である。 FIG. 2 is a plan view of one embodiment of the present invention.

半導体基板11にソース領域12、ドレイン領
域13とを設け、その間にチヤンネル領域14を
形成する。この実施例ではソース領域12とドレ
イン領域13とが櫛状になつているがこれは必須
要件ではない。表面に絶縁膜を被着し、ソース領
域12にソース・コンタクト用窓15をあける。
ドレイン領域13にはチヤンネル領域14の幅方
向に平行な部分(櫛の歯に相当する部分)を有す
る第1のコンタクト用窓16をあける。また、第
1のコンタクト用窓16を挾んでチヤンネル領域
14と反対側のドレイン領域13に第1のコンタ
クト用窓16の少くとも一部分に沿つて平行に第
2のコンタクト用窓17をあける。第2図では、
櫛の柄の部分に相当する部分に沿つて間隔18を
あけて平行に第2のコンタクト用窓17をあけ
る。Al等のオーム接触性金属を蒸着し、選択除
去してソース・コンタクト用窓15にソース電極
を、第1のコンタクト用窓16に第1のドレイン
電極を、第2のコンタクト用窓17に第2のドレ
イン電極をそれぞれ設け、第2のドレイン電極を
出力端子に接続する。
A source region 12 and a drain region 13 are provided in a semiconductor substrate 11, and a channel region 14 is formed therebetween. In this embodiment, the source region 12 and drain region 13 are comb-shaped, but this is not an essential requirement. An insulating film is deposited on the surface, and a source contact window 15 is formed in the source region 12.
A first contact window 16 having a portion (corresponding to the teeth of a comb) parallel to the width direction of the channel region 14 is formed in the drain region 13 . Further, a second contact window 17 is formed parallel to and along at least a portion of the first contact window 16 in the drain region 13 on the opposite side of the channel region 14 with the first contact window 16 interposed therebetween. In Figure 2,
A second contact window 17 is opened in parallel with an interval 18 along a portion corresponding to the comb handle portion. An ohmic contact metal such as Al is deposited and selectively removed to form a source electrode in the source contact window 15, a first drain electrode in the first contact window 16, and a second drain electrode in the second contact window 17. Two drain electrodes are provided, and the second drain electrode is connected to the output terminal.

今、出力端子から第2のドレイン電極に静電気
が印加されると、静電気は第2のコンタクト用窓
17を通つてドレイン領域13に注入される。ド
レイン領域13では必ず抵抗が存在し、かつその
抵抗分布は完全に均一ではないから電流の局所化
が生ずる。しかし、すぐ隣に第1のコンタクト用
窓16が設けられ、窓16にはAl等の低電気抵
抗の第1のドレイン電極が設けられているので、
局所化された電流はドレイン領域13を拡散して
第1のドレイン電極に到達すると、ここで平均化
が行われ、電界が緩和される。従つて、ゲート破
壊に対する強度が向上する。この耐破壊強度は間
隔18の値の設定である程度変えることができ、
耐破壊強度を向上させることができる。
Now, when static electricity is applied from the output terminal to the second drain electrode, the static electricity is injected into the drain region 13 through the second contact window 17. Since resistance always exists in the drain region 13 and the resistance distribution is not completely uniform, localization of current occurs. However, since the first contact window 16 is provided immediately adjacent to the window 16, and the first drain electrode of low electrical resistance such as Al is provided in the window 16,
When the localized current diffuses through the drain region 13 and reaches the first drain electrode, it is averaged and the electric field is relaxed. Therefore, the strength against gate breakage is improved. This breaking strength can be changed to some extent by setting the value of interval 18,
Breakage resistance can be improved.

以上詳細に説明したように、本発明によれば、
静電気によるゲート破壊に対する耐破壊強度を向
上させたMOSトランジスタを備えたMOS集積回
路が得られるのでその効果は大きい。
As explained in detail above, according to the present invention,
The effect is significant because a MOS integrated circuit including a MOS transistor with improved breakdown resistance against gate breakdown due to static electricity can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のMOSトランジスタの一例の平
面図、第2図は本発明の一実施例の平面図であ
る。 1……半導体基板、2……ソース領域、3……
ドレイン領域、4……チヤンネル領域、5……ソ
ース・コンタクト用窓、6……ドレイン・コンタ
クト用窓、11……半導体基板、12……ソース
領域、13……ドレイン電極、14……チヤンネ
ル領域、15……ソース・コンタクト用窓、16
……第1のコンタクト用窓、17……第2のコン
タクト用窓、18……第1のコンタクト用窓と第
2のコンタクト用窓との間隔。
FIG. 1 is a plan view of an example of a conventional MOS transistor, and FIG. 2 is a plan view of an embodiment of the present invention. 1... Semiconductor substrate, 2... Source region, 3...
Drain region, 4... Channel region, 5... Window for source contact, 6... Window for drain contact, 11... Semiconductor substrate, 12... Source region, 13... Drain electrode, 14... Channel region , 15...source contact window, 16
...first contact window, 17...second contact window, 18...distance between the first contact window and the second contact window.

Claims (1)

【特許請求の範囲】[Claims] 1 櫛状のドレイン領域、前記櫛状のドレイン領
域との間にチヤンネル領域を規定する櫛状のソー
ス領域、前記チヤンネル領域上にゲート絶縁膜を
介して設けられたゲート電極を備えるMOS集積
回路であつて、前記櫛状のドレイン領域の櫛の歯
の部分から櫛の柄の部分にわたつて連続的に形成
された第1のコンタクト用窓、前記第1のコンタ
クト用窓に設けられた第1のドレイン電極、前記
第1のコンタクト用窓を挟んで前記チヤンネル領
域と反対側の前記櫛状のドレイン領域の前記櫛の
柄の部分に設けられ且つ前記第1のコンタクト用
窓の少なくとも一部に沿つて実質的に平行に設け
られた第2のコンタクト用窓、前記第2のコンタ
クト用窓に設けられ且つ出力端子に接続される第
2のドレイン電極をさらに備えたことを特徴とす
るMOS集積回路。
1. A MOS integrated circuit comprising a comb-shaped drain region, a comb-shaped source region defining a channel region between the comb-shaped drain region, and a gate electrode provided on the channel region with a gate insulating film interposed therebetween. a first contact window formed continuously from a comb tooth portion to a comb handle portion of the comb-shaped drain region; a first contact window provided in the first contact window; a drain electrode provided at the comb handle portion of the comb-shaped drain region on the opposite side of the channel region across the first contact window, and at least a part of the first contact window; A MOS integrated circuit, further comprising a second contact window provided substantially parallel to the second contact window, and a second drain electrode provided in the second contact window and connected to an output terminal. circuit.
JP57232402A 1982-12-23 1982-12-23 Metal oxide semiconductor integrated circuit Granted JPS59117166A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57232402A JPS59117166A (en) 1982-12-23 1982-12-23 Metal oxide semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57232402A JPS59117166A (en) 1982-12-23 1982-12-23 Metal oxide semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
JPS59117166A JPS59117166A (en) 1984-07-06
JPH0566030B2 true JPH0566030B2 (en) 1993-09-20

Family

ID=16938674

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57232402A Granted JPS59117166A (en) 1982-12-23 1982-12-23 Metal oxide semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS59117166A (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5629370A (en) * 1979-08-18 1981-03-24 Mitsubishi Electric Corp Mos transistor

Also Published As

Publication number Publication date
JPS59117166A (en) 1984-07-06

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