JPH0566045B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a low power consumption, high speed semiconductor integrated circuit device that combines CMOS and bipolar, and particularly relates to a method for configuring these semiconductor integrated circuit devices. It is.

[Prior Art] Attempts have been made to combine CMOS, bipolar, and transistors to construct a semiconductor circuit that combines the low power consumption of CMOS and the high speed of bipolar. FIG. 1 shows an inverter as an example of a semiconductor circuit. Although circuits of this type with different configurations are known, inverters are the most common.

The circuit described above is manufactured by IE Transactions on Electrochron Devices,
Vol.ED-16, No.11, November 1969, pages 945-
Page 951 (IEEE TRANSACTION ON
ELECTRON DEVICES Vol.ED−16, No.11,
Nov. 1969, pp. 945-951).

According to this document, as is clear from equations (4) and (5) on page 950, the delay time of a bipolar/CMOS composite circuit is determined by the current amplification factor h _fe of the bipolar transistor in the output section of the CMOS circuit. It is considered that bipolar/CMOS composite circuits always operate faster than CMOS circuits.

Figure 2a shows the CMOS gate circuit 21 (a 2-input NAND gate is shown as an example) and the load capacitance.
Bipolar/CMOS composite circuit 22 between C and _L
(For example, the circuit shown in FIG. 1) is added to drive a very heavy load capacitance C _L at a relatively high speed using a bipolar/CMOS composite circuit 22 having a high load driving capability.

[ _Problems to be Solved by the Invention] As mentioned above, the bipolar/ _CMOS composite circuit shown in FIG. (sum of capacitance and input capacitance of the next stage gate to be driven)
When is small (for example, around 0.1pF),
The CMOS gate circuit 21 alone is sufficiently fast,
The inventors' studies have revealed that adding the bipolar/CMOS composite buffer circuit 22 actually slows down the load drive response.

However, if the bipolar/CMOS composite buffer circuit 22 is omitted, if the load capacitance C _L becomes large (for example, about 1 pF), the CMOS circuit 21
The inventors' studies have also revealed that the delay time is several times (for example, three times or more) that when the load is light.

This situation can be explained using the CMOS shown in Figure 2b.
A detailed explanation will be given with reference to the load capacitance dependence of the propagation delay time t _pd of the circuit and the bipolar/CMOS composite circuit.

First, as mentioned above, conventionally, bipolar
CMOS composite circuits were thought to always operate faster than CMOS circuits. However, according to the inventors' study, as shown in FIG. 2b,
2.0μm process is approximately 0.3pF, 1.3μm process is approximately
At 0.2pF, the relationship between the two is reversed. In other words, the operating speed of the CMOS circuit is fast below a certain load capacity. Figure 2b shows the circuit shown in Figure 2a when it is constructed of MOS transistors with a ratio of gate width W to gate L of W/L≈30, and the above-mentioned numerical values themselves are not specific. Obviously, this will vary depending on the configuration.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor integrated circuit device that can drive heavy loads at high speed and can also drive light loads at even higher speed.

[Means for Solving the Problems] In order to achieve the above object, the CMOS with load capacitance dependence discovered by the above-mentioned inventors
Inversion of propagation delay time of circuits and bipolar/CMOS composite circuits is actively applied.

That is, heavy load capacity is bipolar
The semiconductor integrated circuit device according to the typical embodiment of the present invention is driven by a CMOS composite circuit, and the light load capacity is driven by the CMOS circuit.
It is composed of CMOS circuits, and the heavy-load circuit parts are composed of bipolar/CMOS composite circuits.

[Function] The heavy load capacitance C _L is driven by a bipolar/CMOS composite buffer circuit with high load driving capability, and while an increase in delay time when driving a heavy load is avoided,
Light load capacitor
By driving C _L with a CMOS gate circuit, the propagation delay time can be made smaller than when driving with a bipolar/CMOS composite circuit.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

First, the bipolar type used in the embodiment of the present invention
I will explain CMOS composite circuit.

By the way, as shown in Figure 2a, usually
The CMOS logic gate 21 has a basic circuit of NAND and NOR, and when an inverter circuit is combined with these gates, it becomes a logic that does not include negation, such as AND and OR. Figure 2a shows an example,
The output of the NAND gate 21 composed of CMOS is connected to bipolar and CMOS as shown in Figure 1.
A composite buffer circuit 22 is connected to obtain an AND circuit.

However, it is difficult to frequently use such combinations that result in positive logic circuits, or to construct random logic as a basic circuit. Therefore, a non-inverter type buffer circuit with high speed and low power consumption is desired as these buffer circuits.

FIG. 3 shows a non-inverter type bipolar converter used in the embodiment of the present invention shown in FIGS. 9 and 10.
FIG. 2 is a circuit diagram showing an example of a CMOS composite buffer circuit. This circuit is an n-channel MOS transistor
QM1 and QM4, p-channel MOS transistors
It consists of QM2, QM3, and npn bipolar transistors QB1 and QB2. This circuit operates as follows. First, consider a state where both input and output are at high levels. At this time, QM2 and QM3 are off, and QM1 and QM4 are on. Therefore QB2 is off. Furthermore, since the load on the output OUT is capacitive, QB1 is also mostly off in a steady state. Under this condition, if the output OUT becomes low level for some reason (for example, leakage current from the load connected to the output), then it will pass through QM1.
Base current is supplied to QB1 and the output OUT is kept at a high level. Almost as long as OUT is at a high level
QB1 is off, so almost no current flows in steady state. Next, consider a situation where the input IN switches from high level to low level. Immediately after switching, the output OUT is still at a high level. In this state, QM2 and QM3 are on, and QM1 and QM4 are off. The charge accumulated in the base of QB1 is extracted by QM2 and QB1 is turned off.
On the other hand, QB2 is turned on because the base current is supplied through QM3. Therefore, a current h _FE times its base current flows through the collector of QB2, so that the output OUT quickly goes to a low level. When the output OUT goes to low level, QB is output from the output OUT.
The base current to QB2 is no longer supplied and QB2 is turned off. In this state, QM2 is also on, but the base charge of QB1 has already been extracted, so no current flows. In other words, even if both input and output are in a steady state with low levels, no current other than leak current flows. Next, consider the case where the input switches from low level to high level. Immediately after the input switches, the output is still at a low level. Therefore, QM1 is on, QM2 is off, QM3 is off, and QM4 is on, and the base current is supplied to QB1 via QM1, while the base charge of QB2 is extracted by QM4. Therefore, QB2
turns off rapidly, and the output OUT goes to a higher level due to QB1. When the output OUT reaches a completely high level, the base current no longer flows through QM1, returning to the state described at the beginning.

As explained above, in the circuit shown in Figure 3, as long as the input/output remains at a high or low level, only leakage current flows and the power consumption is almost zero, and power flows during the switching transition. Only. Therefore, overall power consumption is small;
You can think of it as the same as CMOS. On the other hand, when viewed from the output, the gm of the MOS transistor appears to be multiplied by h _FE (that is, approximately two orders of magnitude), so even if the output load capacitance is large, the speed can be sufficiently increased. In addition, for faster speed, QM1 (or QM3 in some cases)
) is preferably of the depletion type.

FIG. 4 shows a non-inverter type bipolar converter used in the embodiment of the present invention shown in FIGS. 9 and 10.
This shows another example of a CMOS composite buffer circuit. The difference between this circuit example and the circuit example in Figure 3 is that the
The only difference is that the drain of QM2 was connected to the base of OB2 in Figure 4. In the circuit of Figure 4, when the input switches from high level to low level, the charge drawn from the base of QB1 is QB2.
QB2 is supplied as a base current to QB2, and therefore the time for QB2 to turn on becomes earlier. Regarding other operations, FIG. 4 and FIG. 3 are the same.

By the way, in the circuit examples shown in FIGS. 3 and 4, it is desirable that QM1 be of the depletion type in order to increase the speed. This is because if the device is not of the depletion type, even if the input is at a high level, it will not be possible to supply enough base current to make the output at a sufficiently high level. Therefore, it is difficult to maintain the output at a sufficiently high level and to increase the speed. On the other hand, since the other MOS transistors shown in FIGS. 3 and 4 are generally enhancement type (of course, they can be made into depletion type if necessary), in the case of the circuit examples shown in FIGS. 3 and 4, In order to improve performance, it is necessary to use both enhancement type and depletion type MOS transistors, which makes the process somewhat complicated.

FIG. 5 shows another example of a non-inverter type bipolar/CMOS composite buffer circuit used in the embodiments of the present invention shown in FIGS. 9 and 10, which eliminates the above-mentioned drawbacks. It's dark.

The circuit in Figure 5 is a p-channel MOS transistor.
QM11, QM12 and QM13, n-channel
It consists of a MOS transistor QM14 and npn bipolar transistors QB11 and QB12.

The operation of this circuit will be briefly explained. First, consider a state where both input and output are at high levels. At this time, QM11, QM12, and QM13 are off,
Only QM14 is on. Therefore, QB1
Both QB1 and QB12 are off. Under this condition, if the output OUT becomes low level for some reason (for example, leakage current from the load connected to the output), QM12 turns on and QB11 connects the input terminal.
Base current is supplied from IN and the output OUT is kept at a high level. QB1 as long as OUT is at a high level
1 is off, and therefore almost no current flows in a steady state. Next, consider a situation where the input IN switches from high level to low level. Immediately after switching, the output OUT is still at a high level. In this state, QM11, QM13 are on, QM12, QM1
4 is off. The charge accumulated in the base of QB11 is extracted by QM11 and QB11 is turned off. On the other hand, QB12 is turned on because the base current is supplied through QM13. Therefore, the collector of QB12 has its base current h _FE
Since twice as much current flows, the output OUT quickly goes to a low level. When the output OUT becomes low level,
The base current from the output OUT to QB12 is no longer supplied, and QB12 is turned off. In this state
QM11 and QM12 are also on, but QB
Since the base charge of No. 11 has already been extracted, no current flows. In other words, even if both input and output are in a steady state with low levels, no current flows except for leakage current. Next, consider the case where the input changes from low level to high level. Immediately after the input switches, the output is still at a low level. Therefore,
QM11 is off, QM12 is on, QM13 is off, QM14 is on, and QB passes through QM12.
While the base current is supplied to QB11, it is extracted by the base charge QM14 of QB12. Therefore, QB12 turns off quickly and the output OUT becomes
Heading to a higher level with QB11. When the output OUT goes completely high, QM 12 turns off and returns to the state described at the beginning.

As explained above, even in the circuit shown in Figure 5, as long as the input and output remain at a high or low level, only leakage current flows and the power consumption is almost zero.
Power only flows during switching transients. Therefore, the power consumption as a whole can be considered to be the same as that of CMOS, as in the circuit examples shown in Figures 3 and 4, and it can be considered that the gm of the CMOS gate is effectively multiplied by h _FE . , the same as in the embodiments of FIGS. 3 and 4.

FIG. 6 shows a non-inverter type bipolar converter used in the embodiment of the present invention shown in FIGS. 9 and 10.
This shows another example of a CMOS composite buffer circuit. The difference between this circuit example and the circuit example in Figure 5 is that
The only point in FIG. 6 is that the drain of QM11 is connected to the base of QB12. In the circuit shown in Figure 6, when the input switches from high level to low level, the charge drawn from the base of QB11 is QB
QB 12 is supplied as a base current, therefore, the time at which QB 12 is turned on becomes earlier.
Regarding other operations, FIG. 6 and FIG. 5 are the same. In the circuits shown in FIGS. 5 and 6, the base current of QB1 must be supplied by the front-stage circuit, so that the front-stage circuit requires a somewhat larger driving capability than in the case of FIGS. 3 and 4.

FIG. 7 is a circuit diagram showing another example of a non-inverter type bipolar/CMOS composite buffer circuit used in the embodiment of the present invention shown in FIGS. 9 and 10. In this circuit example, the third and fourth
QM1, QM2 in the figure or Figures 5 and 6,
Alternatively, QM11 and QM12 are removed and the base of QB1 or QB11 is directly connected to the input terminal. In this case, QB1 is in the on state except when the input is at an extremely low level, so
It has the disadvantage that all the noise on the input appears on the output side. However, this circuit can be used if sufficient noise margin is ensured. Note that the operation of this circuit is clear from the explanation of the operation in FIGS. 3 to 6, so the explanation will be omitted.

A usage example using the circuit described above will be briefly described. FIG. 8 shows an example in which the 3-input CMOS NAND gate A and the circuit example B in FIG. 6 are combined, and the whole constitutes a 3-input NAND circuit. The delay time of this circuit is compared to the delay time of the ECL circuit, which is currently the most standard high-speed bipolar logic circuit.
Comparisons were made assuming processes at the same level. As a result, it was found that for a load capacitance of 1 pF, the delay time of the circuit shown in FIG. 8 was almost the same as that of ECL.
Also, the delay time in both parts A and B is almost equal.
Each delay time was about half of the ECL delay time. Furthermore, the power consumption at this time is extremely small, about 1/20 of ECL, assuming a switching cycle time of 50 ns. In other words, by using the circuit shown in Figure 8, it is possible to construct an LSI with approximately 20 times faster integration than ECL in terms of power consumption, and the delay time of the unit gate can be basically the same as ECL. Also,
In actual use, a combination of non-inverter type and inverter type will be used as the bipolar/CMOS composite buffer for the logic gate network, but in that case, the conventional inverter type buffer will be used. Any of the following may be used in combination with the buffer of the present invention.

FIG. 9 shows a block diagram of a semiconductor integrated circuit device according to an embodiment of the present invention, where A is a CMOS
It is a logic circuit network that combines multiple gates,
B, B', etc. are the bipolar/CMOS composite buffer circuits described above. In this case, the CMOS gate network A is grouped to the extent that the load capacitance of the output of each gate is considered to be sufficiently light, and each CMOS gate has a light load (that is, the load gates are placed close together). , low wiring capacitance, etc.). On the other hand, if the load capacitance is heavy due to applying an input to a gate located far away in the chip or due to a large fan-out, the signal is passed through bipolar/CMOS composite buffer circuits B, B', etc. It is transmitted by Therefore, the increase in delay time due to load is small.

FIG. 10 shows a block diagram of a semiconductor integrated circuit device according to another embodiment of the present invention. In this case, for example, the signal input from I2 is
It passes through CMOS gates A1, A3, and A4, is buffered by bipolar/CMOS composite buffer circuit B2, and goes out to output 02. In this case, A1, A3,
Since the load capacity of the output of A4 is light, each operates with a delay time about 1/2 that of ECL. In addition, even if the load on output 02 is heavy, the bipolar/CMOS composite buffer circuit B2 operates with a delay time that is approximately 1/2 of ECL, so the three stages of gates operate with a delay time that is twice ECL as a whole. become. This reduction in delay time becomes greater as the number of cascaded gates in the CMOS gate network increases. However, since the load generally increases as the number of gates increases, there is an optimum point somewhere. This optimum point is determined by the process technology used, the level of circuit design technology, etc.
In addition, in the case of the usage shown in Figure 9, the number of bipolar/CMOS buffers used is reduced, so
The increase in chip area due to the use of buffers can also be kept to a minimum. In addition, in actual use, a combination of both non-inverter type and inverter type will be used as a bipolar CMOS composite buffer for logic gate networks, but in that case, conventional inverter type buffers will be used. Any type of mold may be used in combination with the buffer of the present invention.

Further, although the circuit of the embodiment shown in FIG. 6 is used here as the bipolar/CMOS composite buffer circuit, the same effect can be obtained by configuring the circuit of the embodiment shown in FIGS. 3 to 7.

Note that in the present invention, V _TH of the MOS transistor
You can change the speed, power consumption, output level, etc. by changing the , but this is a matter of design.
It goes without saying that this is within the scope of the present invention.

Furthermore, it goes without saying that the same operation can be achieved by replacing the npn transistor with a pnp transistor and replacing the p-channel MOS transistor with the n-channel MOS transistor.

[Brief explanation of drawings]

Figure 1 shows a conventional bipolar/CMOS composite buffer circuit, and Figure 2a shows a bipolar/CMOS composite buffer circuit.
A conventional circuit configuration in which a load capacitance is driven by a CMOS composite buffer circuit is shown, and FIG. 2b shows a characteristic diagram for explaining the effect of the principle of the present invention.
3 to 7 show circuit examples of the bipolar/CMOS composite buffer circuit used in the embodiments of the present invention, FIG. 8 shows an example of the use of the bipolar/CMOS composite buffer circuit, and FIG. 9 shows an example of the use of the bipolar/CMOS composite buffer circuit. A block diagram of a semiconductor integrated circuit device according to an embodiment of the invention is shown, and FIG. 10 is a block diagram of a semiconductor integrated circuit device according to another embodiment of the invention.

Claims (1)

[Claims] 1. First, second, third and fourth CMOS gates each including at least a first polarity MOS transistor and a second polarity MOS transistor; and a first polarity MOS transistor; It includes at least a second polarity MOS transistor and a bipolar transistor provided at its output section.
A BiCMOS buffer is provided on the same semiconductor chip, and the output of the first CMOS gate is
Connect directly to the input of the BiCMOS buffer, and connect the output of the BiCMOS buffer to the second
Connect directly to the input of the CMOS gate, and connect the output of the third CMOS gate to the fourth
The load capacitance of the third CMOS gate is directly connected to the input of the CMOS gate.
The propagation delay time when driving with a CMOS gate is the load capacitance of the third CMOS gate above.
A semiconductor integrated circuit device set in a region smaller than a propagation delay time when driven by a BiCMOS buffer, and a load capacitance of the BiCMOS buffer is set to be larger than a load capacitance of the third CMOS gate. . 2. The bipolar transistor of the output section of the BiCMOS buffer includes a first bipolar transistor whose collector-emitter path is connected between a first operating potential point and the output of the output section;
2. The semiconductor integrated circuit device according to claim 1, wherein the collector-emitter path comprises a second bipolar transistor connected between the output and a second operating potential point. 3. The first bipolar transistor and the second bipolar transistor have the same polarity, and the base of the first bipolar transistor and the base of the second bipolar transistor are driven in opposite phases to each other. A semiconductor integrated circuit device according to claim 2.