JPH0566047B2 - - Google Patents
Info
- Publication number
- JPH0566047B2 JPH0566047B2 JP57136684A JP13668482A JPH0566047B2 JP H0566047 B2 JPH0566047 B2 JP H0566047B2 JP 57136684 A JP57136684 A JP 57136684A JP 13668482 A JP13668482 A JP 13668482A JP H0566047 B2 JPH0566047 B2 JP H0566047B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- voltage
- signal
- frequency
- voltage controlled
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
【発明の詳細な説明】
本発明は位相固定ループ(PLL,Phase
Locked Loop)等に用いられる電圧制御発振回
路に関する。本発明は電圧制御発振回路の特にフ
リーラン周波数の安定化を計つた回路に関する。[Detailed Description of the Invention] The present invention provides a phase-locked loop (PLL).
Related to voltage controlled oscillator circuits used in applications such as locked loops. The present invention relates to a voltage controlled oscillation circuit, particularly to a circuit designed to stabilize the free run frequency.
従来より電圧制御発振回路は非常に多く発表さ
れている。第3図に例としてPLL用1チツプ相
補MOS集積回路(CMOS・IC)に用いられてい
る電圧制御発振回路を揚げる。Nチヤネルトラン
ジスタN1のゲートに加えられる制御電圧により
コンデンサC1に流入する電流を制御し発振周波
数をコントロールする。抵抗R1,R2はそれぞれ
制御電圧感度係数、フリーラン周波数を決定す
る。 A large number of voltage controlled oscillator circuits have been published in the past. Figure 3 shows, as an example, a voltage controlled oscillator circuit used in a one-chip complementary MOS integrated circuit (CMOS IC) for PLL. A control voltage applied to the gate of the N-channel transistor N1 controls the current flowing into the capacitor C1 , thereby controlling the oscillation frequency. Resistors R 1 and R 2 determine the control voltage sensitivity coefficient and free run frequency, respectively.
また他の例として第4図には特開昭56−86509
号公報により公知の電圧制御発振回路を示す。該
回路はリングオシレータに流入する電流をソース
に接続されたトランジスタT41〜T46のゲート電
圧により制御し発振周波数を制御するものであ
る。この回路は第3図の回路に比較し外付部品が
不要で消費電力、実装スペースも小さい利点があ
るが正確で安定な発振回路は作りにくい。また第
3図の回路でも安定度は充分とは言えない。 As another example, Fig. 4 shows the
1 shows a voltage controlled oscillator circuit known from the publication No. This circuit controls the current flowing into the ring oscillator by the gate voltages of the transistors T 41 to T 46 connected to the sources, thereby controlling the oscillation frequency. Although this circuit has the advantage of requiring no external components and requiring less power consumption and mounting space than the circuit shown in FIG. 3, it is difficult to create an accurate and stable oscillation circuit. Further, even the circuit shown in FIG. 3 cannot be said to have sufficient stability.
一般に電圧制御発振回路にし安定度の要求され
るのはフリーラン周波数及び電圧制御感度係数で
ある。前者は電圧制御発振回路の制御端子に加え
られる電圧(制御電圧)が基準レベルのときの発
振周波数である。基準レベルは通常制御可能な入
力電圧範囲の中央、例えばCMOS・ICでは電源
電圧の1/2に選ばれ、制御電圧をVc、基準レベル
の電圧をVsとして△Vcを
△Vc=Vc−Vs ……(1)
と定義すればフリーラン周波数は△Vc=0のと
きの発振周波数と言い直しても良い。電圧制御感
度係数kvは
o=c+kv・△Vc ……(2)
として定義される。cはフリーラン周波数、o
は電圧制御発振回路の発振周波数である。 In general, stability requirements for a voltage controlled oscillator circuit include the free run frequency and the voltage control sensitivity coefficient. The former is the oscillation frequency when the voltage (control voltage) applied to the control terminal of the voltage controlled oscillation circuit is at the reference level. The reference level is usually selected at the center of the controllable input voltage range, for example, 1/2 of the power supply voltage for CMOS/IC, and where the control voltage is Vc and the reference level voltage is Vs, △Vc is △Vc = Vc - Vs... ...(1) If it is defined, the free run frequency can be rephrased as the oscillation frequency when △Vc=0. The voltage control sensitivity coefficient kv is defined as o=c+kv・△Vc...(2). c is free run frequency, o
is the oscillation frequency of the voltage controlled oscillation circuit.
フリーラン周波数cのドリフトはPLLにおい
ては系のキヤブチヤレンジのドリフトとなつて悪
影響があらわれる。また、回路部品定数のばらつ
きによるcのばらつきは無視できない程度に大き
く、従来はコスト高を覚悟した上で高精度部品を
用いるか、組立後に半固定抵抗や半固定コンデン
サにより調整、合せ込みをする必要があつた。ま
た電圧制御感度係数kvのドリフトはPLLを構成
した場合、系の応答速度のドリフトとなつて悪影
響があらわれる。 A drift in the free run frequency c becomes a drift in the cab range of the system in the PLL, and has an adverse effect. In addition, the variation in c due to variations in circuit component constants is too large to be ignored. Conventionally, high-precision components were used at the expense of high costs, or adjustment and matching was done using semi-fixed resistors or semi-fixed capacitors after assembly. The need arose. Furthermore, when a PLL is configured, a drift in the voltage control sensitivity coefficient kv results in a drift in the response speed of the system, which has an adverse effect.
これ等のドリフトの原因は周囲温度の変化、使
用電源の変動、部品定数の経時変化等である。特
にfcの変動はこれ等の要因により大きくドリフト
する。一方kvは回路の構成部品の相対精度によ
り決める様にすることができ半導体集積回路技術
等により素子値の絶対精度はなくとも相対的に充
分なトラツキング特性を持たせることによりその
変動を小さくできる。 The causes of these drifts include changes in ambient temperature, fluctuations in the power supply used, and changes in component constants over time. In particular, the fluctuation of fc drifts significantly due to these factors. On the other hand, kv can be determined by the relative precision of the circuit components, and even if the absolute precision of element values is not achieved through semiconductor integrated circuit technology, its fluctuation can be reduced by providing relatively sufficient tracking characteristics.
本発明は従来の電圧制御発振回路のドリフトを
押える回路方式に関するものであつて回路の構成
部品の定数のばらつき変動による発振回路の定数
(c・kv)の変動を小さくし回路の安定性を増大
することにある。 The present invention relates to a circuit system for suppressing the drift of conventional voltage controlled oscillator circuits, and increases the stability of the circuit by reducing fluctuations in the constants (c/kv) of the oscillator circuit due to variations in the constants of circuit components. It's about doing.
本発明の他の目的は回路定数の絶対精度に対し
ての変動を押えることにより集積回路化しやすい
電圧制御発振回路を提供することにある。 Another object of the present invention is to provide a voltage controlled oscillation circuit that can be easily integrated into an integrated circuit by suppressing fluctuations in absolute accuracy of circuit constants.
第1図は本発明の概念を示す図である。10
1,103は同一の特性を有する様に設計された
信号合成手段で例えば端子109に与えられる信
号(以下、電圧値として話をすすめる。電流値、
電荷値等他の物理量でも話は同じである。)を
V11、端子110に加わる信号電圧をV21、信号
合成手段101の出力端子114にあらわれる電
圧をV01とすると
V01=(v11,v21) ……(3)
は任意関数
の様な特性を有する回路である。以下、簡単のた
めに
v01=av11+bv21+c ……(4)
とする。(a,b,cは定数)
同様に端子111、端子112に加えられる電
圧をそれぞれV12,V22とし信号合成手段103
の出力端子115の電圧をV02としたとき
v02=av12+bv22+c ……(5)
とする。102,104は特性のそろつた電圧制
御発振回路であり出力信号の周波数F1,F2は
F1=Kv V01+d ……(6)
F2=Kv V02+d ……(7)
とする(dは定数)106は位相比較回路で電圧
制御発振回路104の出力と安定な周波数の発振
をする発振回路107(例えば水晶発振回路)の
出力信号と位相比較をしその位相差に比例した量
の信号を出力する。105はローパスフイルタ
(LPF)で位相比較回路の出力から希望する信号
成分のみをとり出すために通常入れられる。
LPF105の出力は第2の信号合成回路103
の第2の入力端子112に負帰還する。すなわち
第2の電圧制御発振回路104、位相比較回路1
06、LPF105、信号合成手段103はPLL
を構成し第2の電圧制御発振回路の発振周波数は
発振回路107の発振周波数refと等しくなる。
電圧制御発振回路104の出力周波数は位相比較
回路106、LPF105の特性によりrefと位相
まで完全に一致させることもできるし、またref
の突発的な変化に対しては追従しない様にするこ
ともできる。発振回路107は通常、充分安定な
発振をする回路を用いるので系の応答を速くして
も問題はない。また電圧制御発振回路104の出
力周波数とrefは周波数のみ追従し、位相は誤差
があつてもよいから回路の構成はかなり自由度が
ある。発振回路107が不安定でジツタ等を有す
る時は系の設計によりその影響を軽減できる。 FIG. 1 is a diagram showing the concept of the present invention. 10
1 and 103 are signal synthesis means designed to have the same characteristics, for example, a signal (hereinafter referred to as a voltage value, a current value, and a signal applied to a terminal 109).
The same story applies to other physical quantities such as electric charge value. )of
V 11 , the signal voltage applied to the terminal 110 is V 21 , and the voltage appearing at the output terminal 114 of the signal synthesis means 101 is V 01 , V 01 = (v 11 , v 21 ) ...(3) is like an arbitrary function. It is a circuit with characteristics. Hereinafter, for simplicity, it is assumed that v 01 =av 11 +bv 21 +c (4). (a, b, c are constants) Similarly, the voltages applied to the terminals 111 and 112 are V 12 and V 22 respectively, and the signal synthesis means 103
When the voltage at the output terminal 115 of is V 02 , v 02 =av 12 +bv 22 +c (5). 102 and 104 are voltage controlled oscillator circuits with uniform characteristics, and the frequencies F 1 and F 2 of the output signals are F 1 = Kv V 01 + d ……(6) F 2 = Kv V 02 + d ……(7) (d is a constant) 106 is a phase comparison circuit that compares the phase of the output of the voltage controlled oscillation circuit 104 with the output signal of the oscillation circuit 107 (for example, a crystal oscillation circuit) that oscillates at a stable frequency, and calculates an amount proportional to the phase difference. Outputs the signal. A low pass filter (LPF) 105 is normally inserted to extract only desired signal components from the output of the phase comparison circuit.
The output of the LPF 105 is sent to the second signal synthesis circuit 103
Negative feedback is provided to the second input terminal 112 of. That is, the second voltage controlled oscillation circuit 104 and the phase comparison circuit 1
06, LPF105, signal synthesis means 103 is PLL
The oscillation frequency of the second voltage controlled oscillation circuit is equal to the oscillation frequency ref of the oscillation circuit 107.
The output frequency of the voltage controlled oscillation circuit 104 can be made to completely match ref and the phase depending on the characteristics of the phase comparator circuit 106 and LPF 105.
It is also possible to not follow sudden changes in . Since the oscillation circuit 107 is normally a circuit that generates sufficiently stable oscillation, there is no problem even if the response of the system is made faster. Further, the output frequency and ref of the voltage controlled oscillation circuit 104 follow only the frequency, and there may be an error in the phase, so there is considerable freedom in the circuit configuration. If the oscillation circuit 107 is unstable and has jitter etc., the influence can be reduced by system design.
さて、電源電圧の変動、温度特性、経時変化等
により電圧制御発振回路104のフリーラン周波
数が変動した場合を考えよう。このとき系は自動
的に端子112に加わる電圧を上げ下げして電圧
制御発振回路104の発振周波数はrefを保つ。
また第2の信号合成手段103の第1の制御端子
111に任意の電圧値を与えた場合もその電圧値
にかかわらず第2の電圧制御発振回路の発振周波
数はrefとなる様、端子112の電圧は自動的に
調整される。 Now, let us consider a case where the free run frequency of the voltage controlled oscillation circuit 104 fluctuates due to fluctuations in power supply voltage, temperature characteristics, changes over time, and the like. At this time, the system automatically increases or decreases the voltage applied to the terminal 112 to maintain the oscillation frequency of the voltage controlled oscillation circuit 104 at ref.
Further, even if an arbitrary voltage value is applied to the first control terminal 111 of the second signal synthesis means 103, the oscillation frequency of the second voltage controlled oscillation circuit will be ref regardless of the voltage value. Voltage will be adjusted automatically.
従つて、第2の信号合成回路の第1の入力端子
111に基準となる電圧Vsを与えると第2の入
力端子112は自動的にレベル調整され電圧制御
発振回路104の発振周波数refに等しくなる。
第1図に示す様に第2の信号合成手段103の第
2の入力端子112の電圧を第1の信号合成手段
101の第2の入力端子110にも与えると第
1、第2の信号合成手段、電圧制御発振回路はそ
れぞれ特性がそろつているので第1の電圧制御発
振回路102の発振周波数は第1の信号合成手段
101の第1の入力端子109に与えられる電圧
がVsのときrefとなる。refを希望するフリーラ
ン周波数cに等しく設定しておけば端子109の
電圧がVsのとき電圧制御発振回路102の発振
周波数はcとなる。従つて第1図の回路全体を端
子109を制御端子、113を出力端子とする電
圧制御発振回路とすればフリーラン周波数がcの
電圧制御回路を実現できたことになる。 Therefore, when the reference voltage Vs is applied to the first input terminal 111 of the second signal synthesis circuit, the level of the second input terminal 112 is automatically adjusted to become equal to the oscillation frequency ref of the voltage controlled oscillation circuit 104. .
As shown in FIG. 1, when the voltage at the second input terminal 112 of the second signal synthesizing means 103 is also applied to the second input terminal 110 of the first signal synthesizing means 101, the first and second signals are synthesized. Since the means and the voltage controlled oscillation circuit have the same characteristics, the oscillation frequency of the first voltage controlled oscillation circuit 102 is equal to ref when the voltage applied to the first input terminal 109 of the first signal synthesizing means 101 is Vs. Become. If ref is set equal to the desired free run frequency c, the oscillation frequency of the voltage controlled oscillation circuit 102 will be c when the voltage at the terminal 109 is Vs. Therefore, if the entire circuit of FIG. 1 is made into a voltage controlled oscillator circuit with terminal 109 as a control terminal and terminal 113 as an output terminal, a voltage controlled circuit with a free run frequency of c can be realized.
回路内の2つの信号合成手段101,103、
電圧制御発振回路102,104の特性は等しい
と仮定して議論をしてきたが、この仮定は極めて
妥当なものである。特にモノリシツク集積回路化
した場合、各々は数ミリ角のチツプ上に高精度で
対称性よく作り込むことができる。各々の回路は
同時に製造されるため経時変化があつたとしても
同一の経過時間であり特性が各々で異つてくるこ
とは少ない。また電源電圧や温度変化に対しても
同一の電源にて使用されるし、また、きわめて近
い場所に配置されているため双方に温度差を生じ
特性が異つてくることも少ない。集積回路の設計
時に各々の回路の対称性を充分配慮しておけば、
各特性の変動は互いにキヤンセルしあつてドリフ
トの少ない安定な電圧制御発振回路を実現でき
る。 two signal synthesis means 101, 103 in the circuit;
The discussion has been made on the assumption that the voltage controlled oscillation circuits 102 and 104 have the same characteristics, and this assumption is extremely valid. In particular, when integrated into a monolithic circuit, each circuit can be fabricated with high precision and good symmetry on a chip of several millimeters square. Since each circuit is manufactured at the same time, even if there is a change over time, the elapsed time is the same, and the characteristics are unlikely to differ from each other. In addition, the same power source is used in response to changes in power supply voltage and temperature, and since they are located very close to each other, it is unlikely that temperature differences will occur between the two and the characteristics will differ. If you pay sufficient attention to the symmetry of each circuit when designing an integrated circuit,
Fluctuations in each characteristic cancel each other out, making it possible to realize a stable voltage-controlled oscillation circuit with little drift.
第2図は以上の本発明の考え方にもとづき半導
体集積回路により実現できる電圧制御発振回路の
具体例を示す図である。201は信号合成回路で
トランジスタT1及びT2のゲート電圧を変えるこ
とにより各々のドレイン電流を変える。T1,T2
のドレイン電流は合成(加算)されトランジスタ
T13に流れ込み電圧に変換される。この電圧は第
1の電圧制御発振回路の制御電圧であり、MOS
トランジスタで構成される電圧制御発振回路20
2に入力される。(4)愛器に式に示されるように
a,bの係数が入力信号に乗ぜられ、制御電圧を
決定するために、2つの入力信号に対し独立に感
度を設定することが可能となる。この回路はトラ
ンジスタT7,T10,T8,T11…T9,T12により構
成される奇数段のインバータによりリングオシレ
ータを構成し、各々のトランジスタのソースにさ
らにトランジスタT4,T5,…T6,T15,T16,…
T17を直列に入れ、これ等のトランジスタのゲー
ト電位を制御することによりリングオシレータに
電源より流入する電流を制御し発振周波数を制御
するものである。本発明の例では端子212,2
14の電位が低くなる程T13のドレイン電圧(電
圧制御発振回路202の制御電圧)が上昇し発振
周波数が上る。すなわち(4)式においてa,bが
負、(6)式においてkvが正の場合である。端子2
12,214のレベルが高いときに高い周波数で
発振させたければ例えば201,202の回路の
トランジスタの極性をすべて逆(Pチヤネルトラ
ンジスタをNチヤネルに、Nチヤネルトランジス
タをPチヤネルに)にすれば、a,bが負、kv
が負となり達成できる。205,206は出力を
得るためのバツフア回路である。 FIG. 2 is a diagram showing a specific example of a voltage controlled oscillation circuit that can be realized by a semiconductor integrated circuit based on the above idea of the present invention. 201 is a signal synthesis circuit which changes the drain current of each transistor by changing the gate voltage of the transistors T1 and T2 . T 1 , T 2
The drain currents of the transistors are combined (added)
It flows into T 13 and is converted into voltage. This voltage is the control voltage of the first voltage controlled oscillation circuit, and is the control voltage of the first voltage controlled oscillation circuit.
Voltage controlled oscillation circuit 20 composed of transistors
2 is input. (4) The coefficients a and b are multiplied by the input signal as shown in the formula for the beloved device, and it becomes possible to independently set the sensitivity for the two input signals in order to determine the control voltage. In this circuit, a ring oscillator is configured by an odd number of stages of inverters made up of transistors T 7 , T 10 , T 8 , T 11 . . . T 9 , T 12 , and transistors T 4 , T 5 , …T 6 , T 15 , T 16 ,…
By connecting T17 in series and controlling the gate potential of these transistors, the current flowing into the ring oscillator from the power supply is controlled, and the oscillation frequency is controlled. In the example of the present invention, the terminals 212, 2
As the potential of T 14 becomes lower, the drain voltage of T 13 (control voltage of voltage controlled oscillation circuit 202) increases, and the oscillation frequency increases. In other words, a and b are negative in equation (4), and kv is positive in equation (6). terminal 2
If you want to oscillate at a high frequency when the level of 12 and 214 is high, for example, if you reverse the polarity of all the transistors in the circuits of 201 and 202 (P channel transistor to N channel, N channel transistor to P channel), a, b are negative, kv
becomes negative and can be achieved. 205 and 206 are buffer circuits for obtaining outputs.
203,204はそれぞれ201,202と同
様の回路構成を持つ信号合成回路、電圧制御発振
回路である。内部構成は同じなので図では内部を
省略してある。第2の電圧制御発振回路の出力は
バツフア207を通し位相比較回路208に入力
される。211は水晶発振回路でフリーラン周波
数の基準となる周波数ref(=c)を発振する発
振回路である。通常はこの信号は位相比較回路2
08に入力され第2の電圧制御発振回路204の
出力と位相比較されるとともに他の回路のタイミ
ングクロツク、システムクロツクなどと共用され
る。もし他の回路の要求するクロツク信号等の周
波数と希望するcとが異る場合はノード219ま
たは218の一方か双方に分周回路や周波数変換
回路を入れることにより水晶発振回路211の発
振周波数の整数倍、整数分の1、それ等の差、整
数ぶんの整数等にcを設定することが可能であ
る。分周回路や周波数変換回路はデジタル回路で
構成でき半導体集積回路化に際して何ら障害は生
じない。217はローパスフイルタで位相比較回
路208の出力に含まれる高周波成分を除去す
る。出力は第2の信号合成回路203の第2の入
力端子215に帰還される。第1の入力端子21
3にはcを発振させたい入力信号レベル(基準レ
ベル)を与えるべく電源電圧を分圧する抵抗
R11,R12が接続されている。抵抗は半導体集積
回路内に正確なものは作りにくいが相対精度は非
常に高く作ることが可能である。この端子には例
えばツエナーダイオードによる基準電圧等のもつ
と正確な電圧源を接続しても良い。第1及び第2
の信号合成回路の第2の入力端子214,215
にはローパスフイルタ217内部の異つたところ
から信号をとり出し接続しているが抵抗R4は
PLL系の安定化のために必要な抵抗であつて第
1図の場合と本質的に異るものではない。 Reference numerals 203 and 204 are a signal synthesis circuit and a voltage controlled oscillation circuit having the same circuit configuration as 201 and 202, respectively. Since the internal configuration is the same, the internal parts are omitted in the figure. The output of the second voltage controlled oscillation circuit is input to the phase comparison circuit 208 through the buffer 207. Reference numeral 211 is a crystal oscillation circuit that oscillates a frequency ref (=c) that is a reference for the free run frequency. Normally, this signal is the phase comparator circuit 2
The clock signal is inputted to 08 and compared in phase with the output of the second voltage controlled oscillation circuit 204, and is also shared with the timing clock, system clock, etc. of other circuits. If the frequency of the clock signal, etc. required by other circuits is different from the desired c, the oscillation frequency of the crystal oscillator circuit 211 can be adjusted by inserting a frequency divider circuit or a frequency converter circuit into one or both of nodes 219 and 218. It is possible to set c to an integer multiple, an integer fraction, the difference between them, an integer equivalent to an integer, etc. The frequency dividing circuit and the frequency converting circuit can be constructed with digital circuits, and no problems will occur when they are integrated into semiconductor integrated circuits. A low-pass filter 217 removes high frequency components contained in the output of the phase comparison circuit 208. The output is fed back to the second input terminal 215 of the second signal synthesis circuit 203. First input terminal 21
3 is a resistor that divides the power supply voltage to give the input signal level (reference level) that you want c to oscillate.
R 11 and R 12 are connected. Although it is difficult to make a resistor accurately in a semiconductor integrated circuit, it is possible to make a resistor with very high relative accuracy. A highly accurate voltage source, such as a Zener diode reference voltage, may be connected to this terminal. 1st and 2nd
The second input terminals 214, 215 of the signal synthesis circuit of
The signals are extracted from different points inside the low-pass filter 217 and connected, but the resistor R4 is
This resistance is necessary for stabilizing the PLL system and is not essentially different from the case shown in FIG.
第2図の構成を見ると抵抗R11〜R15、コンデ
ンサC11〜C13、水晶発振子Xを除けばすべて
MOSトランジスタで構成されている。抵抗、コ
ンデンサは絶対精度が要求されることは無い。従
つて抵抗は半導体集積回路に内蔵できる。また必
要とする発振周波数のレンジによつても異るがコ
ンデンサC11も内蔵が可能であることが多い。低
い周波数が必要なときは出力端子216に分周回
路を接続することにより、PLL系は高い周波数
で発振させておけばC1も小容量で済み集積回路
化が容易となる。 Looking at the configuration in Figure 2, everything except resistors R 11 to R 15 , capacitors C 11 to C 13 , and crystal oscillator X
Consists of MOS transistors. Absolute precision is not required for resistors and capacitors. Therefore, the resistor can be built into the semiconductor integrated circuit. Although it depends on the required oscillation frequency range, it is often possible to incorporate a capacitor C11 . When a low frequency is required, by connecting a frequency dividing circuit to the output terminal 216, the PLL system can be caused to oscillate at a high frequency, and the capacitance of C1 can be reduced, making it easy to integrate the circuit.
以上述べた様に本発明によれば高精度部品を用
いることなくきわめて安定な電圧制御発振回路を
実現できる。高精度の部品を用いる必要が無いか
ら半導体集積回路化がきわめて容易となり実装
上、製造上のメリツトが大きい。 As described above, according to the present invention, an extremely stable voltage controlled oscillation circuit can be realized without using high precision components. Since there is no need to use high-precision parts, it is extremely easy to integrate semiconductor circuits, which has great advantages in terms of packaging and manufacturing.
本発明による例(第1,2図)と従来例(第
3,4図)を比較すると本発明の方はかなり複雑
になつており従来例に比較してあまりメリツトが
無い様に思われるかも知れない。しかし事実は逆
なのであつて半導体集積回路上に第2図の回路を
構成する場合そのチツプ上に占める面積はわずか
である。第3図の従来例の様に外付部品を必要と
するときは半導体集積回路上のボンデイングパツ
ドの面積や出力トランジスタ(例えば第3図のコ
ンデンサC1(外付)を駆動するP4,P5,N2,N3、
抵抗R1,R2(外付)を駆動するP1,N1)に大き
なものが必要となりそれ等の占める面積の方が本
発明の回路に比べはるかに大きくなつているので
ある。また本発明では水晶発振回路の様な安定な
発振回路を必要とするが、通常大規模集積回路で
は電圧制御発振回路の他に安定な基準パルス列が
必要な場合が多く、これと共用すれば良いので本
発明を実施するにあたつて障害とはならない。ま
た本発明では第1図のノード116または11
7、第2図のノード218,219に直列に分周
回路または周波数変換回路を入れ、その分周比等
を論理回路で制御することにより同一の回路で任
意にフリーラン周波数を設定することができる。 Comparing the example according to the present invention (Figs. 1 and 2) and the conventional example (Figs. 3 and 4), it may seem that the present invention is considerably more complicated and does not have much merit compared to the conventional example. I don't know. However, the opposite is true; when the circuit of FIG. 2 is constructed on a semiconductor integrated circuit, the area occupied on the chip is small. When external components are required, as in the conventional example shown in Fig. 3, the area of the bonding pad on the semiconductor integrated circuit and the output transistor (for example, P 4 that drives the capacitor C 1 (external) shown in Fig. 3), P5 , N2 , N3 ,
P 1 , N 1 ) that drive the resistors R 1 , R 2 (external) need to be large, and the area occupied by them is much larger than in the circuit of the present invention. In addition, the present invention requires a stable oscillation circuit such as a crystal oscillation circuit, but in large-scale integrated circuits, a stable reference pulse train is often required in addition to the voltage-controlled oscillation circuit, so it is sufficient to use it in combination with the voltage-controlled oscillation circuit. Therefore, this does not pose an obstacle to implementing the present invention. Further, in the present invention, the node 116 or 11 in FIG.
7. By inserting a frequency dividing circuit or a frequency converting circuit in series with nodes 218 and 219 in Fig. 2, and controlling the frequency division ratio etc. with a logic circuit, it is possible to arbitrarily set the free run frequency with the same circuit. can.
この様に本発明は集積回路化の容易な電圧制御
発振回路を安定化する方法を示し、デジタル集積
回路にも容易に組込める電圧制御発振回路を示し
た。本発明を実施すればコスト、実装スペースを
減少でき機器を実現していく上で大いに貢献でき
る。 In this way, the present invention has shown a method for stabilizing a voltage controlled oscillation circuit that can be easily integrated into an integrated circuit, and has shown a voltage controlled oscillation circuit that can be easily integrated into a digital integrated circuit. By implementing the present invention, costs and mounting space can be reduced and it can greatly contribute to the realization of devices.
即ち、本発明によれば第1の発振回路を変動要
因に対して安定に発振させることができる。ま
た、発振回路の制御電圧を電流に変換した後合成
し再び電圧に変換するために、PLLの特性を変
更せずに幅広い周波数に対応したPLLを提供す
ることができる。 That is, according to the present invention, the first oscillation circuit can be stably oscillated against fluctuation factors. Furthermore, since the control voltage of the oscillation circuit is converted into a current and then synthesized and converted back into a voltage, it is possible to provide a PLL that supports a wide range of frequencies without changing the characteristics of the PLL.
第1,2図は本発明の実施例を示す図、第3,
4図は従来の電圧制御発振回路を示す図である。
101,201……第1の信号合成回路、10
3,203……第2の信号合成回路、102,2
02……第1の電圧制御発振回路、104,20
4……第2の電圧制御発振回路、106,208
……位相比較回路、105,217……ローパス
フイルタ、107,211……基準周波数発振回
路、109,212……第1の信号合成回路の第
1の入力端子、制御端子、110,214……第
1の信号合成回路の第2の入力端子、111,2
13……第2の信号合成回路の第1の入力端子、
112,215……第2の信号合成回路の第2の
入力端子、113,216……出力端子。
1 and 2 are diagrams showing embodiments of the present invention;
FIG. 4 is a diagram showing a conventional voltage controlled oscillation circuit. 101, 201...first signal synthesis circuit, 10
3,203...second signal synthesis circuit, 102,2
02...First voltage controlled oscillation circuit, 104, 20
4...Second voltage controlled oscillation circuit, 106, 208
...Phase comparison circuit, 105,217...Low pass filter, 107,211...Reference frequency oscillation circuit, 109,212...First input terminal of first signal synthesis circuit, control terminal, 110,214... second input terminal of the first signal synthesis circuit, 111,2
13...first input terminal of the second signal synthesis circuit,
112, 215... Second input terminal of the second signal synthesis circuit, 113, 216... Output terminal.
Claims (1)
る第1の電圧制御発振器を有し入力信号に同期す
る第1の位相固定ループと、前記第1の電圧制御
発振器と同等の特性を有し第2の合成信号により
発振周波数が制御される第2の電圧制御発振器を
有し基準信号に同期する第2の位相固定ループと
を備える発振回路において、 第1の制御信号と前記第2の位相固定ループ内
で発生される前記第2の電圧制御発振器の出力と
前記基準信号を同期化させるために前記第2の位
相固定ループ内で発生される第2の制御信号とを
それぞれ電流に変換して加算し前記第1の合成信
号を出力する第1の信号加算回路と、 前記第2の制御信号と基準電圧とをそれぞれ電
流に変換して加算し前記第2の合成信号を出力す
る第2の信号加算回路とを有することを特徴とす
る発振回路。[Claims] 1. A first phase-locked loop that has a first voltage-controlled oscillator whose oscillation frequency is controlled by a first composite signal and is synchronized with an input signal, and a first phase-locked loop that is equivalent to the first voltage-controlled oscillator. In the oscillation circuit, the oscillation circuit includes a second voltage-controlled oscillator whose oscillation frequency is controlled by the second composite signal and a second phase-locked loop synchronized with the reference signal. a second control signal generated within the second phase-locked loop for synchronizing the reference signal with the output of the second voltage-controlled oscillator generated within the second phase-locked loop; a first signal addition circuit that converts each of the signals into currents and adds them to output the first composite signal; and a first signal addition circuit that converts each of the second control signal and the reference voltage to currents and adds them to output the first composite signal, and outputs the second composite signal. An oscillation circuit characterized in that it has a second signal addition circuit that outputs.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57136684A JPS5927615A (en) | 1982-08-05 | 1982-08-05 | voltage controlled oscillation circuit |
| GB08319600A GB2127636B (en) | 1982-08-05 | 1983-07-20 | Voltage controlled oscillator circuit |
| US06/520,270 US4567448A (en) | 1982-08-05 | 1983-08-04 | Variable frequency oscillator |
| DE19833328420 DE3328420A1 (en) | 1982-08-05 | 1983-08-05 | VOLTAGE CONTROLLED OSCILLATOR AND USE THEREOF IN A VARIABLE VARIABLE OSCILLATOR FOR A DISK STORAGE DRIVE |
| HK36988A HK36988A (en) | 1982-08-05 | 1988-05-19 | Voltage controlled oscillator circuit |
| US07/798,064 USRE34317E (en) | 1982-08-05 | 1991-11-27 | Variable frequency oscillator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57136684A JPS5927615A (en) | 1982-08-05 | 1982-08-05 | voltage controlled oscillation circuit |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3018748A Division JPH0770999B2 (en) | 1991-02-12 | 1991-02-12 | Voltage controlled oscillator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5927615A JPS5927615A (en) | 1984-02-14 |
| JPH0566047B2 true JPH0566047B2 (en) | 1993-09-21 |
Family
ID=15181052
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57136684A Granted JPS5927615A (en) | 1982-08-05 | 1982-08-05 | voltage controlled oscillation circuit |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPS5927615A (en) |
| GB (1) | GB2127636B (en) |
| HK (1) | HK36988A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61144929A (en) * | 1984-12-19 | 1986-07-02 | Nec Corp | Phase synchronous oscillating circuit |
| JPH0752838B2 (en) * | 1985-03-20 | 1995-06-05 | 株式会社日立製作所 | Integrated circuit |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4131861A (en) * | 1977-12-30 | 1978-12-26 | International Business Machines Corporation | Variable frequency oscillator system including two matched oscillators controlled by a phase locked loop |
| JPS5924191Y2 (en) * | 1979-07-13 | 1984-07-18 | 三洋電機株式会社 | Synthesizer-receiver AFC circuit |
| JPS57181232A (en) * | 1981-04-30 | 1982-11-08 | Fujitsu Ltd | Voltage-controlled oscillator circuit |
-
1982
- 1982-08-05 JP JP57136684A patent/JPS5927615A/en active Granted
-
1983
- 1983-07-20 GB GB08319600A patent/GB2127636B/en not_active Expired
-
1988
- 1988-05-19 HK HK36988A patent/HK36988A/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| HK36988A (en) | 1988-05-27 |
| GB2127636B (en) | 1986-04-23 |
| GB2127636A (en) | 1984-04-11 |
| GB8319600D0 (en) | 1983-08-24 |
| JPS5927615A (en) | 1984-02-14 |
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