JPH056647B2 - - Google Patents

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a rotary encoder.

[Conventional technology]

Rotary encoders that reduce power consumption in the electric circuit of optical or magnetic rotary encoders have already been proposed (for example, in Japanese Patent Application No. 73868/1989 proposed by the present application).
No. 59-73871, No. 59-73872). FIG. 2 shows a circuit diagram of these encoders. The electric circuit 10 of the encoder includes an oscillation circuit 100 that generates a clock pulse CLK ₀ , and a clock pulse for driving the circuit in response to the falling edge of the clock pulse CLK ₀ .
Monostable multivibrator 1 generating CLK ₁
01, an amplifier circuit 10 consisting of a transistor and a resistor that amplifies the signals of the photodiodes 4 and 5;
2,103, D-type flip-flops FF1 to FF4 and a decoder to detect the rise or fall of the A-phase signal SA and B-phase signal SB from the amplifier circuit.
A rising/falling detection circuit 104 in which DECDR is connected as shown, and an increasing signal S _U from the detection circuit.
Alternatively, OR gates 105 and 106 for guiding the decrease signal S _D to the up-down counter 107 are connected as shown. The power source of the light emitting diode 9 as the light source of the encoder is the clock pulse CLK _0.
It is given by Therefore, the light emitting diode 9 does not light up all the time like before, but lights up only when the clock pulse CLK ₀ is at a high level.
The A-phase and B-phase signals transmitted through the rotating slit plate and detected by the photodiodes 4 and 5 also correspond to the clock pulse CLK ₀ , and the power consumption of the battery 11 connected as a power source to these circuits is extremely low. It is becoming smaller.

The operation of the above circuit will be described below.

An exemplary circuit for the rise/fall detection circuit 104 of FIG. 2 is illustrated in FIG. That is, D-type flip-flops FF1 to FF4 and their outputs are received.
NAND gates G1, G7, G8, G14 and G
2, G4, G11, and G13 are connected as shown. A phase signal SA for FF1, B for FF3
These flip-flop signals SA1=2 ⁰ , SA1=2 ¹ , SB1=2 ² , SB2 are connected to the phase signal SB.
Let = 2 ³ . Then, as shown in Fig. 4, when the shaft rotates in the normal direction and SA is 90 degrees ahead of SB (Fig. 4 D, E), gates G1, G7,
An increase signal S _U is output via G8 and G14.
On the other hand, when the shaft is reversed, as shown in Figure 5,
A reduction signal S _D is outputted via gates G2, G4, G11, and G13.

Furthermore, in the encoder described above, in order to further reduce power consumption, the S _U and S _D signals are inputted through the OR gate 109 to calculate the timing at which these signals occur, and if the generation period of these signals is low, the clock pulse is A circuit 108 for lowering the oscillation frequency of CLK ₀ is provided. In other words, when the rotation of the encoder shaft decreases, the position of the shaft can be detected even with a low frequency clock pulse, and by using a low frequency clock pulse, the light emitting diode 9
The lighting time per certain period of time is shortened, and power consumption is reduced accordingly.

[Problem that the invention seeks to solve]

In general, the rotation of the shaft changes continuously when it increases or decreases, or even if the frequency of the clock pulse is changed according to the rotation of the shaft as described above, the position can usually be detected without any problem, and the power consumption is further reduced. can be reduced. Further, even when changing the frequency, there is a considerable margin, and there is no problem even if the rotational speed changes from a decreasing state to an increasing state. However, such a sudden change beyond what is normally expected occurs, for example, when a shaft that is rotating at a low speed or is stopped suddenly rotates instantaneously due to an impact, etc., and in response to that rotation, a forward rotation (increase) signal is generated. When the clock pulse CLK does not exist between the timings of detecting the S _U or the reversal (decrease) signal S _D , the rising/falling detection circuit 104 shown in FIG. Thus, S _U and S _D are output simultaneously from gates G7 and G4, respectively.

Therefore, a problem arises in that the rotation is treated as if it were not rotating. The above error is considered unacceptable due to the positioning accuracy required of the encoder.

[Means for solving the invention]

In the present invention, a light emitting element 9 that emits light in response to a clock pulse, and a light emitting element 9 that is provided opposite to the light emitting element 9 with a rotational code plate interposed therebetween, and a predetermined angular difference in response to the rotation of the rotation code plate. first and second light receiving elements 4 provided to output signals;
5, and a rise/fall detection circuit that detects the rise or fall of the output signals of the first and second light receiving elements 4 and 5 and outputs a forward or reverse rotation signal in response to the rotation of the rotation code plate. 104, a counter 107 that counts the forward rotation or reverse rotation signal, and an oscillation frequency calculation circuit 108 that changes the oscillation frequency of the clock pulse in response to the generation cycle of the forward rotation or reverse rotation signal.
In the encoder comprising, when the forward rotation and reverse rotation signals are output simultaneously, the simultaneous output of the forward and reverse signals is stored in the storage circuit 171, and the counter 107 is configured to output either the forward rotation or the reverse rotation signal. The present invention is characterized by further comprising a pulse correction circuit 110 which increases the clock frequency without being applied and inputs any one of the above signals to the counter in accordance with the forward rotation or reverse rotation signal generated at the next timing. , an encoder is provided.

[Effect]

That is, in the present invention, when forward rotation and reverse rotation signals are output at the same time, neither signal is applied to the counter at that time, and the fact that the forward rotation and reverse rotation signals are received at the same time is memorized. In such a case, the oscillation frequency of the clock pulse is increased so that forward or reverse rotation can be accurately detected in the next cycle. If the next cycle is detected as normal rotation due to the continuity of rotation, the stored contents are added as a normal rotation signal and output.

〔Example〕

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 illustrates an electric circuit section of an optical rotary encoder as an embodiment of the present invention. As is clear from the figure, the electric circuit of the present invention includes OR gates 105 and 106 and an up/down counter 107.
A pulse correction circuit 110 is provided between the normal rotation signal S _U or the reverse rotation signal _SD .
I am trying to output CB _U or CS _D. The rest is the same as in the case of FIG.

One embodiment of pulse correction circuit 110 is illustrated in FIG. Pulse correction circuit 110 shown in FIG.
is AND gate 10, 11, OR gate 12,
13, a miss pulse detection circuit 14, a timing detection circuit 15, a direction detection circuit 16, and a correction circuit 17 are connected as shown.

FIG. 8 shows an example of a circuit that more specifically realizes the circuit shown in FIG. 7.

AND gate 10, 11 and OR gate 12,
13 is the same as in FIG. The miss pulse detection circuit 14 includes an AND gate 141 and an inverter 1.
42 are connected as shown. Timing detection circuit 15, correction circuit 17, direction detection circuit 16
is ORGATE 151, JK flipflop 1
71-173, and gate 174, 175, 1
77, 178, 179, inverter 176, and
A JK flip-flop 161 is connected as shown.

Pulse correction circuit 11 shown in FIGS. 7 and 8
The operation of 0 will be explained.

First, a normal case will be described. in this case,
Since there is only one signal, S _U or S _D ,
The output of the AND gate 141 is "0", so the output S14 of the miss pulse detection circuit 14 via the inverter 142 becomes 1. Therefore, if there is a S _U signal, it will pass through the AND gate 10 and the OR gate 12.
_CSU in the same state as S _U is output. That is, in the normal case, the forward rotation or reverse rotation signal is output as is without being corrected as before.

Next, see Chapter 9 regarding cases where pulse correction is required.
This will be explained with reference to the figure.

FIG. 9 is a timing diagram when the A-phase signal SA1 (FIG. 9a) is 90 degrees ahead of the B-phase signal SB1 (FIG. 9b). When the oscillation frequency of clock pulse CLK ₀ becomes low because the rotation has stopped or decreased considerably, if it suddenly starts rotating due to an impact etc., there will be a change in SA1 and SB1 between clock pulses a and b as shown in the figure. If clock pulse a' was present, it would be possible to detect normal rotation, but normal rotation could not be detected and clock pulse b
In this case, S _D is also output along with S _U. However, since the output S14 of the miss pulse detection circuit 14 becomes 0, neither _CSU nor _CSD is output.

The AND gate 141 sends a signal S14a indicating that there is a duplicate pulse to the oscillation frequency calculation circuit 1.
Output on 08. This causes the circuit 108 to generate an oscillator 1 that increases the oscillation frequency of the clock pulse.
00, and the frequency of clock pulse CLK ₀ increases (c→d of clock pulse CLK ₀ ).

Normal rotation is correctly detected at C of the next clock pulse CLK ₀ . In this case, since S _U =1 and S _D =0, only C S _U is output. Also, the fact that there is a duplicate pulse is set in the JK flip-flop 171, and the output F3 becomes "1" (FIG. 9f). Furthermore, at d of the next clock pulse CLK ₀ , all the inputs of the AND gate 174 are "1", so the JK flip-flop 172 is set, and the output F4=1.
becomes. (Figure 9g).

At e of clock pulse CLK ₀ , S _U remains "1" and C S _U is output as is.
In this case, since the output of the NOR gate 176 is "0", the output of the AND gate 177 is "0", and therefore the JK flip-flop 173 remains unset.

At f of clock pulse CLK ₀ , S _U = “0”
Then, S _U = 0, S _D = 0, and OR gate 1
Output of 51 = "0", output of NOR gate 176 =
becomes “1”, and the output of AND gate 177 = “1”
So, the inputs of AND gates 178 and 179 =
It becomes "1". On the other hand, JK flip-flop 161
Since last time S _U = 1 and S _D = 0, Q output = 1 and "1" is output only from AND gate 178 to OR gate 12, and C S _U continues as shown by the intersection line in Figure 9h. is output. That is, the inverter 176 is used to detect idle time, and during this idle time, the contents stored in the flip-flop are
It outputs according to the direction specified by the JK flip-flop 161.

In addition, as the output of the AND gate 177 = "1", the JK flip-flop 173 is set,
The output of the AND gate 175 becomes "1", and the JK flip-flops 171 and 172 are set.

After that, counting is performed normally as before.

Although the above embodiments have been described with respect to optical rotary encoders, the same applies to magnetic rotary encoders.

``Effects of the Invention'' As described above, according to the present invention, the frequency of the clock pulse can be made variable in order to further reduce the power consumption of the electric circuit of the encoder. Even if there is a change, the position change at the time of the change is accurately detected, and the reliability of positioning accuracy is improved. Although there will be some time delay in detecting a positional change when there is a sudden change, this does not pose a problem in use.

[Brief explanation of the drawing]

FIG. 1 is an electric circuit diagram of an encoder as an embodiment of the present invention, FIG. 2 is an electric circuit diagram of a conventional encoder, FIG. 3 is a rise/fall detection circuit diagram of the circuit in FIG. 5 and 5 are operation timing diagrams of the circuit in FIG. 3, FIG. 6 is a timing diagram showing erroneous pulse generation in the circuit in FIG. 3, FIG. 7 is a block diagram of the pulse correction circuit in the circuit in FIG. 1, and FIG. 9 is a detailed circuit diagram of the circuit of FIG. 7, and FIG. 9 is a diagram showing the operation timing of the circuits of FIGS. 1, 7, and 8. Explanation of symbols, 100...Oscillation circuit, 101...
Monostable multivibrator, 102, 103...
Amplifier circuit, 104...Rise/fall detection circuit, 10
5,106...OR gate, 107...Up-down counter, 108...Oscillation frequency calculation circuit,
110... Pulse correction circuit, 10, 11... AND gate, 12, 13... OR gate, 14...
Miss pulse detection circuit, 15... timing detection circuit, 16... direction detection circuit, 17... correction circuit.

Claims (1)

[Scope of Claims] 1. A light-emitting element 9 that emits light in response to a clock pulse, and a light-emitting element 9 that is provided opposite to the light-emitting element 9 with a rotation code plate in between, and that emits light in response to rotation of the rotation code plate. The first and second light receiving elements 4 and 5 are provided to output an angular difference signal, and the rise or fall of the output signal of the first and second light receiving elements 4 and 5 is detected and the rotational sign is detected. A rise/fall detection circuit 104 that outputs a forward rotation or reverse rotation signal in response to the rotation of the plate, a counter 107 that counts the forward rotation or reverse rotation signal, and a counter 107 that outputs a forward rotation or reverse rotation signal in response to the generation cycle of the forward rotation or reverse rotation signal. In the oscillation frequency calculation circuit 108 which changes the oscillation frequency of the clock pulse by changing the oscillation frequency and the encoder provided, when the forward rotation and reverse rotation signals are output simultaneously, the simultaneous output of the forward rotation and reverse rotation signals is stored in the storage circuit 171, and the output of the forward and reverse rotation signals is stored in the storage circuit 171, Increase the clock frequency without applying either the forward or reverse rotation signal to
An encoder further comprising a pulse correction circuit 110 configured to input any of the above signals to the counter according to a forward rotation or reverse rotation signal generated at the next timing.