JPH0566742B2 - - Google Patents

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention provides fast operating speed vertical bipolar transistors such as nMOS FET, pMOS
It relates to an integrated circuit provided on the same semiconductor substrate as the FET.

(Prior Art) Conventionally, this type of integrated circuit has been constructed as shown in FIG. In the figure, 100 is a p ⁺ -based conductor substrate, 101 is an n ⁺ buried layer, 102 is a p ^- epitaxial layer, 103 is an n well layer, and 103' is an n ⁺
Collector layer, 104 is a p-type channel doped layer, 1
04' is a p-type base layer, 105 is an n ⁺ source, drain diffusion layer, 105' is an n ⁺ emitter, collector diffusion layer, 106 is a p ⁺ source, drain diffusion layer, 1
06' is a diffusion layer for p ⁺ base electrode, 107 is a diffusion layer for p ⁺ channel stopper, 108 is a field oxide film, 109 is an electrode, 110 is a p channel MOS
FET, 111 represents an n-channel MOS FET.

Here, 103 and 103', 104 and 104',
105 and 105', and 106 and 106' are made in the same process. In such a configuration, npn bipolar transistors, n MOS FETs, p
Since the MOS FETs are isolated from each other by the thick field oxide film 108 and the channel stopper diffusion layer 107, a parasitic npn lateral bipolar transistor is formed between the p-channel transistor n-well region 103 and the npn bipolar transistor collector region 103', for example. This parasitic transistor must be deactivated. Therefore, it is necessary to provide a large interval between 103 and 103', resulting in a reduction in the degree of integration. Further, the area of the base region of the npn bipolar transistor becomes large in a normal manufacturing process because the emitter diffusion layer 105' and the base diffusion layer 106' must be included in the base region. For example, minimum pattern size w, alignment margin s
If a manufacturing technology is used, the area of the base region is at least (2w + 7s) (w +
4s), which is 180μ ² in the process where w = s = 2μ. On the other hand, the emitter area is (w+2s) ² =36μ ² , and the ratio of the emitter area to the base area is a large value of 5, which causes a decrease in the current amplification factor.
Furthermore, the base resistance R _B is proportional to the distance between the center of the base diffusion layer and the center of the emitter diffusion layer, but since this distance is as large as w+4s=10μ, the transition frequency _T also decreases in the state of large current operation. Furthermore, since the base area is large, the collector-base capacitance is also large, and therefore the transition frequency
_T also decreases.

(Problems to be solved by the invention) As described above, in the conventional device, (a) it is difficult to achieve a high degree of integration, (b) it is difficult to achieve a high current amplification factor, and (c) the transition There were drawbacks such as the frequency being susceptible to drop. The present invention has been proposed to improve these drawbacks.

(Means for Solving the Problems) In order to eliminate these drawbacks, the present invention aims to reduce the base area and base resistance of the vertical bipolar transistor by digging thin grooves in the semiconductor substrate to isolate the elements. It is ivy.

In order to achieve the above objects, the present invention includes a highly doped second conductive type semiconductor region forming an emitter, a second conductive type semiconductor region forming a base, and In an integrated circuit device comprising at least a plurality of vertical bipolar transistors each having a first conductivity type semiconductor region forming a collector, the emitter region and the base region immediately below the emitter region are surrounded by a groove; The depth of the groove is the depth reached at the upper surface of the buried diffusion layer in contact with the lower part of the collector region, and the inside of the groove is filled with an insulating material in the portion in contact with the buried diffusion layer and the collector region, and the base region The gist of the invention is an integrated circuit device characterized in that a portion in contact with the base region is filled with a highly concentrated second conductivity type semiconductor or metal to maintain ohmic contact with the base region to form a base electrode. It is something.

Next, embodiments of the present invention will be described with reference to the accompanying drawings. It should be noted that the embodiments are merely illustrative, and it goes without saying that various changes and improvements can be made without departing from the spirit of the present invention.

1 and 2 show an embodiment of the integrated circuit device of the present invention, in which FIG. 1 shows a longitudinal sectional view and FIG. 2 shows a plan view.

In the figure, 100 is a p ⁺ type conductor substrate, 101
is an n ⁺ type buried layer, 102 is a p ^- type epitaxial layer, 103 is an n type well layer, 103 is an n ⁺ type collector layer (collector region), 104 is a p type channel doped layer, and 104' is a p ⁺ type base (base region), 105 is n ⁺ type source, drain diffusion layer, 1
05' is the n ⁺ type emitter diffusion layer (emitter region),
105'' is a collector diffusion layer, 106 is a p ⁺ type source and drain diffusion layer, 108 is a field oxide film, 109 is a gate electrode, and 110 is a p channel.
MOS transistors, 111 is an n-channel MOS transistor, and 112 is a vertical bipolar transistor.

120 is a trench for isolation between each element region, 121 is an npn
Groove for base electrode of bipolar transistor, 12
2 is a groove for reducing collector resistance. First groove 12
0, the inner surface is covered with SiO ₂ oxide or noidized polysilicon 123, and the inside of the groove is filled with high-resistance polysilicon 124. Second
The inner surface of the groove 121 deeper than the bottom surface of the transistor base layer 104' is covered with an oxide 123, and the inside of the groove is filled with high-resistance polysilicon or an insulator 125. On the contrary, base layer 10
The portion shallower than the bottom surface of the base layer 104' is filled with p ⁺ type low resistance polysilicon 126.
Ohmic contact has been made. The inside of the groove 122 is filled with n ⁺ type doped polysilicon 127.

An emitter layer 105' that constitutes a vertical bipolar transistor, a low resistance polysilicon layer, a collector diffusion layer 105'', and a source/drain layer 1 that constitutes a p-MOS FET transistor.
The semiconductor surface excluding the source/drain layer 105 constituting the 06,n MOS FET transistor is covered with a thick oxide film 108.

The surface of the element isolation trench 120 is completely covered with a thick oxide film 108, and the base electrode trench 120 is completely covered with a thick oxide film 108.
1 is disposed surrounding the emitter layer 105', and a portion of this groove is extended as shown in FIG. This part is indicated by 126. 106' indicates a base electrode.

Next, the manufacturing process of the bipolar transistor portion will be mainly described.

(a) Impurity ions are implanted into a p ⁺ semiconductor substrate 100 to form an n ⁺ buried layer 101 .

(b) Next, a p ^-epitaxial layer is formed on the entire surface by an epitaxial method. A layer identical to the layer indicated by 102 in FIG. 1 is formed on the buried layer 101.

(c) Next, etching is performed using a desired mask to form the groove 120.

(d) An oxide film is formed inside this trench, and then polysilicon 125 is filled inside the trench.

(e) Next, impurity ions are implanted into the previously formed epitaxial layer to form n-layers 103 and 103'.

(f) Next, groove 12 in this 103' layer in the same way as before.
Make 1,122.

(g) After masking the trench 122 and forming an oxide film inside the trench 121, the inside of the trench is filled with high-resistance polysilicon 125 or an insulator.

(h) Next, the filled high-resistance polysilicon and inner oxide film are removed by etching to a predetermined thickness, and then high-concentration polysilicon 126 is filled.

(i) Next, regarding groove 122, there is a high concentration of n ⁺ inside.
Filled with polysilicon 127.

(j) Next, the base layer 10 is formed by epitaxial method.
4' is formed.

(k) Next, a mask is applied to a predetermined location, and after etching, an oxide layer 108 is formed.

(l) Next, emitter layer 105', collector electrode layer 1
05″ is formed.

(Function) Due to the structure described above, the npn bipolar transistor, n MOS FET transistor, and p MOS FET transistor are separated by a narrow and deep trench filled with an insulator, so they are different from conventional The area of the separation regions required in this type of device can be reduced and therefore higher densities are possible.

Furthermore, since the base electrode groove whose upper half is filled with low-resistance polysilicon surrounds the emitter electrode, the distance from the center of the emitter electrode that determines the base resistance to the center of the base electrode is equivalently (w+
s)/4, making it possible to reduce the base resistance to about 1/10 compared to a transistor with a conventional structure.

Furthermore, the area of the emitter electrode and the area of the effective base region are almost equal, so the current amplification factor can be higher than that of the conventional structure, and the capacitance between the base and collector can also be significantly reduced, and the transition frequency can also be reduced. do.

Furthermore, if the collector resistance reduction groove 122 is provided, it can be formed by the same groove forming process as the base electrode groove 121, and the collector electrode on the surface and the buried layer in contact with the collector region are made of n ⁺ polysilicon. Connection is now possible. Normally, the specific resistance of an n-well is several Ωcm, while the specific resistance of n ⁺ polysilicon is about 1/1000 of that. Therefore, the collector resistance can be significantly reduced, and the area of the collector electrode on the surface can also be reduced.

In addition, the n ⁺ diffusion layer 105 is used as an emitter, the p ^- type epitaxial layer 102 and the p ⁺ semiconductor substrate 100
an npn bipolar transistor with the n ⁺ buried layer 101 and the n-type well layer 103 as the base, the p ⁺ diffusion layer 106 as the emitter, the n ⁺ buried layer 101 and the n-type well layer 103 as the base,
In a parasitic thyristor consisting of a pnp bipolar transistor with a p ⁺ semiconductor substrate 100 and a p ^- type epitaxial layer 102 as a collector, 120 deep grooves are formed in this structure. The base width becomes longer, and the current amplification factor h _fe of both transistors can be reduced. 100
Since 101 and 101 are highly concentrated, the resistance between the base and emitter of both transistors can be reduced. This 2
This effect makes it difficult for the parasitic thyristor to turn off and prevents latch-up.

(Effects of the Invention) According to the present invention, in an integrated circuit device, the periphery of the emitter region and the base region immediately below the emitter region is surrounded by a groove, and the depth of the groove is equal to the depth of the buried diffusion layer in contact with the lower part of the collector region. The trench is deep enough to reach the upper surface, and the inside of the trench is filled with an insulating material in the portion in contact with the buried diffusion layer and the collector region.
The portion in contact with the base region is filled with a highly concentrated semiconductor or metal of the second conductivity type, and is configured to maintain ohmic contact with the base region to form a base electrode (a) Integrated circuit. (b) The base resistance of the bipolar transistor can be reduced (c) The current amplification factor can be increased and the transition frequency can be lowered (d) Furthermore, it has the advantage of being able to almost completely prevent latch-up in CMOS and bipolar circuits.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of the integrated circuit device of the present invention, and FIG.
The figure shows a plan view, FIG. 3 shows a sectional view of a conventional integrated circuit device, and FIG. 4 shows a plan view. 100... p ⁺ semiconductor substrate, 101... n ⁺ type buried layer, 102... p ^- type epitaxial layer,
103...n type well layer, 103'...n ⁺ type collector layer, 104...p type channel doped layer, 10
4'...p ⁺ type base layer, 105...n ⁺ type source layer
Drain diffusion layer, 105'...n ⁺ type emitter diffusion layer, 105''...collector diffusion layer, 106...p ⁺
type source/drain diffusion layer, 108... field oxide film, 109... gate electrode, 110... p channel MOS transistor, 111... n channel MOS transistor, 112... vertical bipolar transistor, 120... trench for isolation between elements, 121...
... Base electrode groove, 122 ... Collector resistance reduction groove, 125 ... Non-doped polysilicon or insulator, 126 ... p ⁺ doped polysilicon,
127...n ⁺ doped polysilicon.

Claims (1)

[Claims] 1. From the surface of the integrated circuit device toward the substrate,
Reduce the number of vertical bipolar transistors each having a highly concentrated first conductivity type semiconductor region forming an emitter, a second conductivity type semiconductor region forming a base, and a first conductivity type semiconductor region forming a collector. In the integrated circuit device, the emitter region and the base region immediately below the emitter region are surrounded by a groove, and the trench has a depth that reaches the upper surface of the buried diffusion layer in contact with the lower part of the collector region. The inside of the trench is filled with an insulator in a portion contacting the buried diffusion layer and the collector region, and filled with a highly concentrated second conductivity type semiconductor or metal in a portion contacting the base region. , an integrated circuit device comprising: maintaining ohmic contact with the base region and forming a base electrode. 2. A second groove is formed at a position apart from the groove surrounding the emitter region, base region, and collector region, and the inside of the groove is filled with a highly concentrated semiconductor or metal of the second conductivity type, and the groove is 2. The integrated circuit device according to claim 1, wherein the lower portion is connected to the collector through a semiconductor layer, and the upper portion is formed as a collector electrode. 3. Forming a third trench surrounding each field effect transistor formed in the integrated circuit device, coating the inside of the trench with an oxide, and further filling the inside with a high-resistance material or insulator. An integrated circuit device according to claim 1.