JPH0566773B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention is a voltage controlled oscillator circuit (VCO) that is used in a PLL (Phase Locked Loop) frequency synthesizer, etc., and generates a signal with a frequency corresponding to an input voltage. Controlled Oscillator).

[Technical background of the invention and its problems]

In PLL frequency synthesizers and the like, it is necessary to always keep the set frequency of the output signal constant, and voltage controlled oscillator circuits are used for such applications.

Conventionally, this type of voltage controlled oscillator circuit is
The one described in Japanese Patent Application Laid-Open No. 59-62215 is well known.

FIGS. 13 and 14 are circuit diagrams of conventional voltage controlled oscillation circuits described in the above-mentioned publication, respectively. In the voltage controlled oscillator circuit of FIG.
A current corresponding to the input voltage V _io supplied to the input terminal 1 is passed through the input N-channel MOS transistor 2 . The current of this transistor 2 is supplied to a P-channel MOS transistor 3. This transistor 3 constitutes a current mirror circuit together with another P-channel MOS transistor 4, and the transistor 4 serves as a current source that generates a current _I4 corresponding to the input voltage _Vio . The output current _I4 of the current source transistor 4 causes a P channel to flow as indicated by the solid or broken arrow in the figure.
Capacitor 9 is alternately charged from different directions via MOS transistor 5 and N-channel MOS transistor 8 or P-channel MOS transistor 7 and N-channel MOS transistor 6, respectively. The potential across the capacitor 9 is supplied to voltage comparators 10 and 11 each consisting of an inverting circuit or a differential circuit, and the output of one voltage comparator 10 is used as a set input to the other voltage comparator 11. The output is provided to flip-flop 12 as a reset input. The Q output of this flip-flop 12 controls the transistors 5 and 6, and the output controls the transistors 7 and 8.

In such a circuit, flip-flop 1
When the Q output of transistor 2 is set to "1" level and the output is set to "0" level, transistors 7 and 6
is turned on, the capacitor 9 is charged by the output current I ₄ of the transistor 4 along the path indicated by the solid arrow in the figure. During this charging, when the charging potential at one end of the capacitor 9 reaches the threshold voltage of the voltage comparator 11, the output state of the flip-flop 12 is reversed, and the Q output becomes "0" level and the output becomes "1" level. Ru. Then, transistors 5 and 8 are turned on, so that capacitor 9 is charged by the current I ₄ along the path indicated by the broken arrow in the figure. During this charging, capacitor 9
When the charging potential at the other end reaches the threshold voltage of voltage comparator 10, the state of flip-flop 12 is reversed and the Q output and output return to their initial states.

In this way, the capacitor 9 is charged alternately from different directions, and the charging potential at that time is measured by the voltage comparator 1.
0 and 11, and by controlling the flip-flop 12 with this comparison output, an oscillation signal having a frequency corresponding to the input voltage V _io is output from the output terminal 14 of the inverter 13 to which the output of the flip-flop 12 is input. is output.

The circuit shown in FIG. 14 uses two capacitors 15 and 16 instead of the capacitor 9 in order to improve the accuracy of the circuit shown in FIG.

By the way, the voltage controlled oscillation circuits shown in FIGS. 13 and 14 above have the values of capacitors 9, 15, and 16
C ₁ , the threshold voltage of voltage comparators 10 and 11 is V ₁
Then, the frequency of the oscillation signal is approximately given by the following equation.

=I ₄ /2・C ₁・V ₁ ...1 Here, if the process parameters during manufacturing vary, for example, if the oxide film thickness varies, the capacitor value C1 will vary. Furthermore, if the threshold voltage V _th or gate length of the transistor varies, the value of the current I ₄ will vary. As described above, in the circuits shown in FIGS. 13 and 14, various factors that determine the oscillation frequency will vary if the process parameters vary during integration. As a result, variations occur in the oscillation frequency, resulting in a reduction in manufacturing yield.

Furthermore, conventionally, in order to eliminate the influence of the above-mentioned process parameters on the oscillation frequency, a voltage controlled oscillation circuit as described in Japanese Patent Application Laid-Open No. 59-29209 has been invented. 15th
The figure is a block diagram showing its configuration. In the figure, 21 and 22 are first and second phase comparators (PD),
23 and 24 are first and second low-pass filters (LPF), and 25 and 26 are first and second voltage controlled oscillators (with two voltage input terminals CONT and OFFSET, respectively, and having the same circuit configuration and the same circuit pattern). VCO). Both voltage controlled oscillators 25 and 26 have two voltage input terminals CONT and 26, respectively.
It oscillates at a frequency corresponding to the sum of the voltages supplied to OFFSET, and one voltage input terminal CONT of the second voltage controlled oscillator 26 has a reference voltage divided by a pair of resistors. V _ref is supplied. Further, the signal IN _ref of the reference frequency _ref is supplied to one input terminal of the phase comparator 22, and the output signal of the second voltage controlled oscillator 26 is supplied to the other input terminal. is the voltage input terminal OFFSET of the second voltage controlled oscillator 26 via the second low-pass filter 24.
is supplied to. That is, the second voltage controlled oscillator 26 is connected to the second phase comparator 22 and the second voltage controlled oscillator 26.
together with the low pass filter 24 of the reference frequency _ref
It constitutes a phase-locked loop circuit (PLL) that oscillates at .

Also, the voltage input terminal of the first voltage controlled oscillator 25
The output voltage of the first low-pass filter 23 is input to CONT as the input voltage _Vio , and the voltage input terminal OFFSET
are respectively supplied with the output of the second low-pass filter 24. Therefore, the reference voltage is applied to the voltage input terminal CONT of the first voltage controlled oscillator 25.
When a voltage equal to V _ref is supplied, this voltage controlled oscillator 25 also oscillates at the same frequency as the second voltage controlled oscillator 26 .

The circuit shown in FIG. 15 is controlled by such a method to oscillate at the reference frequency when the input voltage to the first voltage controlled oscillator 25 is the reference voltage, regardless of variations in process parameters. In this way, even if the process parameters vary, the circuit shown in FIG. 15 always oscillates at a constant frequency _ref as long as the input voltage is set to the reference voltage.

However, when the input voltage is set to a value other than the reference voltage, variations occur in the output frequency, that is, the frequency of the output signal _Vput of the first voltage controlled oscillator 25. This will be explained in detail next. FIG. 16 is a circuit diagram specifically showing the first and second voltage controlled oscillators 25, 26. This voltage controlled oscillator determines the oscillation frequency by controlling the source current of each inverter of a ring oscillator OSC, which is configured by a plurality of inverters each consisting of a P channel MOS transistor T _p and an N channel MOS transistor T _o . ing. The value of this source current is controlled as follows. First, N-channel MOS transistors T1 and T2 whose respective gates are connected to the two voltage input terminals CONT and OFFSET
The sum of the input currents flowing through the P-channel MOS transistor T3 is passed through the P-channel MOS transistor T3. This transistor T3 constitutes a current mirror circuit together with a plurality of P channel MOS transistors T4.
A current proportional to the current flowing through the transistor T3 is caused to flow through each of these transistors T4 to the P channel MOS transistor _Tp of each inverter.
Similarly, the transistor T3 constitutes a current mirror circuit together with a plurality of N-channel MOS transistors T5, and a current proportional to the current flowing through the transistor T3 passes through each transistor T5 to the N-channel MOS transistors of each inverter. The current is passed through the MOS transistor T _o . In this way, the source current of each inverter is controlled, and the ring oscillator OSC outputs a signal with a frequency that corresponds to the value of the input voltage. This output signal is supplied to the flip-flop FF as a clock signal, and this Q output signal is used as the final oscillation signal.

In a circuit with such a configuration, the frequency of the oscillation signal is proportional to the current flowing through the transistor T3. Now, the value of the input capacitance of one inverter in the ring oscillator OSC is C ₂ , and the value of the source current is I _S
Then, the signal delay time T _pd in one inverter is approximately expressed by the following equation.

T _pd ≒C ₂ ·V _DD /I _S ...2 Here, the oscillation frequency when m inverters are provided in the ring oscillator OSC is as follows.

=1/2m・T _pd =I _S /2m・C ₂・V _DD ……3 Here, the current flowing through the transistor T1 is I _CONT ,
If the current flowing through transistor T2 is I _OFFSET , then
Even if the process parameters vary, I _CONT + I _OFFSET must remain constant when V _io = V _ref .
Here, the threshold voltage of the transistor increases due to variations in process parameters, and as a result, when the threshold voltage of the transistor T1 increases, I _CONT decreases and I _OFFSET increases. Therefore, the G _n value of the transistor T1 becomes small, the change in the current I _CONT +I _OFFSET with respect to the change in the input voltage becomes small, and the change in the oscillation frequency becomes small. Contrary to the above, when the threshold voltage of transistor T1 decreases due to variations in process parameters, the G _n value of transistor T1 increases, and the above current I _CONT + I _OFFSET with respect to input voltage change increases.
As the change in oscillation frequency becomes large, the change in oscillation frequency becomes large. Therefore, if the standard characteristic showing the relationship between the input voltage V _io and the frequency _put of the output signal V _put is represented by the curve in FIG. 17, then
A curve occurs when the threshold voltage of the transistor increases, and a curve occurs when the threshold voltage of the transistor decreases.

In this way, in the circuit shown in Figure 15 above, if the process parameters vary, the gain given by the ratio of the change in oscillation frequency to the change in input voltage will vary, so the loop gain of the PLL will vary, and the PLL
The disadvantage is that there are variations in the response characteristics, especially important characteristics such as damping and pull-in characteristics.

[Purpose of the invention]

This invention has been made in consideration of the above circumstances, and its purpose is to provide a voltage controlled oscillation circuit that does not cause variations in the frequency characteristics of input voltage versus output signal even if process parameters vary. be.

[Summary of the invention]

In order to achieve the above object, the voltage controlled oscillation circuit of the present invention has first to third input terminals, and the frequency of the output signal is equal to the voltage supplied to the first and second input terminals. First to third voltage controlled oscillators each having equivalent input/output characteristics proportional to the result of multiplying the sum value by a gain corresponding to the voltage supplied to the third input terminal are provided, A first reference voltage is supplied to a first input terminal of the voltage controlled oscillator, and a first reference voltage corresponding to the phase difference between the frequency of the output signal of the first voltage controlled oscillator and the first reference frequency signal is supplied. 1 voltage as the 1st
a second input terminal of the voltage controlled oscillator, and a second input terminal of the second voltage controlled oscillator.
A second voltage corresponding to the phase difference between the frequency of the output signal of the second voltage controlled oscillator and the second reference frequency signal is supplied to the second voltage controlled oscillator. and supplying a third voltage corresponding to the difference between the first voltage and the second voltage to each third input terminal of the first to third voltage controlled oscillators in parallel; The first voltage or the second voltage is supplied to the second input terminal of the third voltage controlled oscillator, and the frequency of the oscillation output signal is controlled to the first input terminal of the third voltage controlled oscillator. It is designed to supply input voltage for

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the structure of an embodiment of a voltage controlled oscillation circuit according to the present invention. In the figure, 31, 32, and 33 are first to third voltage controlled oscillators having a first input terminal (CONT), a second input terminal (OFFSET), and a third input terminal (GAIN), respectively. Each of these voltage controlled oscillators 3
1, 32, and 33 have the same circuit configuration and the same circuit pattern when integrated, and the voltages V _CONT and 33 supplied to the first to third input terminals are the same.
V _OFFSET and V _GAIN vs frequency of output signal VCO _put
Assume that there is the following proportional relationship with _put .

(V _CONT +V _OFFSET )× _{V GAIN∝put} ...4 The voltage controlled oscillators 31, 32, and 33 will be described in detail later.

A first reference voltage V _L is supplied to a first input terminal of the first voltage controlled oscillator (VCO) 31 . The output signal VCO _put 1 of the first voltage controlled oscillator 31 is supplied to a first phase comparator (PD) 34 . This first phase comparator 34 is supplied with a first reference frequency signal _L having a constant frequency, and the phase comparator 34 is configured to compare the frequency _put 1 of the signal VCO _put 1 with the first reference frequency signal _L. A pulse signal is generated in which a period of high level or low level is set depending on the phase difference between the pulse signals. This pulse signal is smoothed by a first low-pass filter (LPF) 35 and converted into a DC voltage V ₁ , and then supplied to the second input terminal of the first voltage-controlled oscillator 31 .

A first input terminal of the second voltage controlled oscillator 32 is supplied with a second reference voltage _VH having a value greater than the first reference voltage _VL . This second
The output signal VCO _put 2 of the voltage controlled oscillator 32 is supplied to a second phase comparator 36 . This second
The phase comparator 36 receives a second reference frequency signal _H which is constant and has _a higher value than the first reference frequency signal L.
is supplied, and the phase comparator 36 receives the above signal.
VCO _put 2 frequency _put 2 and second reference frequency signal
A _pulse signal is generated whose period of high level or low level is set depending on the phase difference between the pulse signal and the high level.
After this pulse signal is smoothed by the second low-pass filter 37 and converted into a DC voltage _V2 ,
It is supplied to the second input terminal of the second voltage controlled oscillator 32.

Output voltage of the first low-pass filter 35
V ₁ is also supplied to the inverting input terminal of the operational amplifier 38, and the output voltage V ₂ of the second low-pass filter 37 is supplied to the non-inverting input terminal. This operational amplifier 38 amplifies and outputs the voltage difference between the voltages supplied to its inverting input terminal and non-inverting input terminal with a predetermined gain, and its output voltage V ₃ is amplified by a predetermined gain. voltage controlled oscillator 3
1, 32, and 33 in parallel.

The first input terminal of the third voltage controlled oscillator 33 is supplied with an input voltage V _io for controlling the frequency of the oscillation signal to be output from this circuit.
Further, the output voltage V ₂ of the second low-pass filter 37 is supplied to the second input terminal of the third voltage controlled oscillator 33, and the output signal VCO _put 3 having a predetermined frequency is output from the output terminal. Output.

In such a configuration, the first voltage controlled oscillator 31 constitutes a first PLL circuit together with the first phase comparator 34 and the first low-pass filter 35. And in this first PLL circuit, the PLL
When the operation is stable, the voltage controlled oscillator 31 oscillates at frequency _L. At this time, if the value of the voltage V _CONT supplied to the first input terminal is changed without changing the voltage at the second input terminal, then As shown by the straight line, the frequency _put 1 of the output signal VCO _put 1 increases or decreases in proportion to V _CONT . Similarly, the second voltage controlled oscillator 32 constitutes a second PLL circuit together with a second phase comparator 36 and a second low-pass filter 37,
The voltage controlled oscillator 32 oscillates at frequency _H when the PLL operation is stable. At this time, if the value of the voltage V _CONT supplied to the first input terminal is changed without changing the voltage at the second input terminal, then As shown by the straight line, the frequency _put 2 of the output signal VCO _put 2 increases or decreases in proportion to V _CONT .

Now, let us consider a case where the value of the output voltage V ₃ of the operational amplifier 38 is set to be relatively small. At this time, it is assumed that the input/output characteristics of the first and second voltage controlled oscillators 31 and 32 are as shown by the straight line in FIG. Note that the input/output characteristics of both oscillators 31 and 32 are different because the values of the input voltages at the second input terminals are different. That is, if the same voltage is supplied to the first input terminals _of the voltage controlled oscillators 31 _{and 32} , as is clear from _FIG . exists. Therefore, according to the fourth equation, the voltage _V2 supplied to the second input terminal of the second voltage controlled oscillator 32 is supplied to the second input terminal of the first voltage controlled oscillator 31. It is considered that the voltage is set to be higher than the voltage _V1 . At this time, the output voltage V ₃ of the operational amplifier 38 becomes a high level voltage, and thereby the gains of the first and second voltage controlled oscillators 31 and 32 are set to relatively high values. As a result, the characteristics shown by the straight line in FIG. 2 approach the characteristics shown by the straight line.

On the other hand, let us now consider the case where the value of the output voltage V ₃ of the operational amplifier 38 is relatively large. At this time, the first and second voltage controlled oscillators 3
It is assumed that the input/output characteristics of 1 and 32 are as shown in the straight line in FIG. That is, the voltage controlled oscillator 3
If the same voltage is supplied to the first input terminals 1 and 32, the oscillation frequency _put
There exists a relationship between put 1 and _put 2: _put 1> _put 2. Therefore, in this case, voltage V ₁ is considered to be higher than voltage V ₂ . At this time, the output voltage V ₃ of the operational amplifier 38 becomes a low level voltage, and thereby the gains of the first and second voltage controlled oscillators 31 and 32 are set to relatively low values. As a result, in FIG. 3 as well, the characteristic shown by the straight line , approaches the characteristic shown by the straight line .

As described above, the first and second voltage controlled oscillators 3
The input/output characteristics of 1 and 32 are both set to the characteristics shown by straight lines in FIG. 2 or 3. At this time, the second and third input terminals of the third voltage controlled oscillator 33 are connected to the first and second voltage controlled oscillators 3.
The same voltage as that supplied to the second and third input terminals 1 and 32 is supplied. Therefore, the input/output characteristics of this voltage controlled oscillator 33 are shown by the straight lines in FIG. 2 or 3, and are set to characteristics that pass through the coordinate points (V _L , _L ) and (V _H , _H ). Ru.

Here, the first to third voltage controlled oscillators 3
1, 32, and 33 all have the same circuit configuration and the same circuit pattern, so their input/output characteristics are equivalent. As a result, even if there are variations in process parameters during the manufacturing process, the input voltage V There is no variation in the frequency _put3 of the output signal VCO _put3 for _io .

FIG. 4 is a circuit diagram showing the detailed structure of the first to third voltage controlled oscillators 31, 32, and 33. In the figure, 41 is an N-channel MOS transistor whose gate is connected to the third input terminal and which generates a current according to the voltage _V3 supplied thereto. The source of this transistor 41
One end between the drains is connected to the ground voltage via a resistor 42.
It is connected to the _Vss (0V) application point, and the other end between the source and drain is connected to the gate and drain of the P channel MOS transistor 43 whose gate and drain are connected.
Connected to the drain common connection point. The source of this transistor 43 is connected to the positive polarity power supply voltage V _DD application point. In addition, the transistor 4
The gate of another P-channel MOS transistor 44 is connected to the gate of No. 3, and the source of this transistor 44 is connected to the V _DD application point. That is, both the transistors 43 and 44 constitute a current mirror circuit, and the current flowing through the transistor 41 is supplied as an input current, and a current I _put having a value corresponding to this input current is supplied.
is output from the drain side of the transistor 44.

The gates are commonly connected between the drain of the transistor 44 and the V _SS application point, and the sources and drains of a P-channel MOS transistor 45 and an N-channel MOS transistor 46, each functioning as a switch, are inserted in series. There is. Similarly, the drain of transistor 44 and V _SS
Between the application point and the P-channel MOS, the gates are connected in common and each acts as a switch.
The sources and drains of transistor 47 and N-channel MOS transistor 48 are inserted in series. A capacitor 50 is connected between the series connection point 49 of the transistors 45 and 46 and the V _SS application point.
is inserted. The above transistors 47, 48
A capacitor 52 is inserted between the series connection point 51 and the V _SS application point. Above capacitor 50
The voltage VA at the terminal of the capacitor 52 is applied to the non-inverting input terminal of the first comparator 53.
VB is supplied to each non-inverting input terminal of the second comparator 54. Both comparators 5 above
The output voltage V _ref of the voltage adder circuit 55 is supplied in parallel to each of the inverting input terminals 3 and 54 . The output signal of the first comparator 53 and the second
The output signal of the comparator 54 is sent to the RS flip-flop 5 consisting of two NOR gates 56 and 57.
8 as set and reset inputs. The output signal of the NOR gate 57 in the flip-flop 58 is transferred to the flip-flop 58.
This Q output signal is supplied to the common gate of the transistors 45 and 46. The output signal of the NOR gate 56 in the flip-flop 58 is used as the output signal of the flip-flop 58, and this output signal is supplied to the common gate of the transistors 47 and 48. The output signal VCO _put is obtained as an output signal of an inverter 59 to which the Q output signal of the flip-flop 58 is supplied.

The voltage adding circuit 55 is a well-known circuit that includes an operational amplifier 61 and resistors 62, 63, 64, etc., and adds the voltages supplied to the first and second input terminals and inverts the level thereof. The resulting voltage is supplied to both the comparators 53 and 54 as a reference voltage V _ref .

FIG. 5 is a timing chart showing the operation of the voltage controlled oscillator shown in detail in FIG. 4. First, when the flip-flop 58 is in the reset state, and the Q output signal is at the "0" level and the output signal is at the "1" level, the transistors 46 and 47 are off, and the transistors 45 and 4 are turned off.
8 is turned on. Therefore, the current flowing through the transistor 44 is supplied to the capacitor 50 via the transistor 45 which is turned on. The capacitor 50 is thereby charged by this current. Then, the potential difference between both ends of the capacitor 50 gradually increases, and the terminal voltage VA rises at a constant slope. On the other hand, the capacitor 52 is discharged by the transistor 48, the potential difference across it becomes 0, and the terminal voltage VB becomes 0, that is, the ground potential. If the reference voltage V _ref is now higher than the V _SS voltage, the output signal of the comparator 54 is set to a low level. Further, when charging the capacitor 50, the output signal of the comparator 53 is kept at a low level until the charging voltage VA reaches the reference voltage _Vref , and when it reaches the voltage _Vref , it is inverted to a high level. When the output signal of the comparator 53 is inverted to high level, the flip-flop 58 is set, and the Q output signal is inverted to the "1" level and the output signal is inverted to the "0" level. Then, this time,
Transistors 45 and 46 are off, transistor 4
6 and 47 are turned on, and the capacitor 52 is charged by the current flowing through the transistor 44. Then, the potential difference across the capacitor 52 gradually increases, and the terminal voltage VB rises at the same constant slope as the voltage VA. On the other hand, the capacitor 50
is discharged by the transistor 46, the potential difference across it becomes 0, and the terminal voltage VA is brought to the ground potential. When charging the capacitor 52, the output signal of the comparator 54 is kept at a low level until its charging voltage VB reaches the reference voltage _Vref , and is inverted to a high level when it reaches the voltage _Vref . When the output signal of the comparator 54 becomes high level, the flip-flop 58 is reset, and the Q output signal is again inverted to the "0" level and the output signal is inverted to the "1" level. Thereafter, by repeating the same operation, the Q output signal and the output signal of the flip-flop 58 become oscillation signals having a predetermined frequency.

The circuit shown in FIG. 4 repeats the above operation to oscillate. In this voltage controlled oscillator, a current I _put flows through the capacitor 50 and the terminal voltage VA changes from 0 to V _ref , and a current I _put flows through the capacitor 52 and the terminal voltage VB changes from 0 to V _ref . It oscillates with the sum of time as one period. Therefore, the oscillation frequency _put is given by the following equation. _put =1/C ₁₁・V _ref /I _put +C ₁₂・V _ref /I _put =I _put
/V _ref (C ₁₁ +C ₁₂ )...5 Here, if the values C ₁₁ and C ₁₂ of capacitors 50 and 52 are set to be equal to C, the above fifth equation becomes the following sixth equation.

_put =I _put 2・C・V _ref ……6 The relationship of this formula 6 is like the curve in the characteristic diagram of FIG. Next, in the characteristics shown in FIG. 6, the relationship between V _ref and I _put and frequency _put in a minute range is determined. Now, the operating point of this voltage controlled oscillator is
Considering that V _ref = near V, the characteristic curve given by the above equation 6 is approximated by a straight line like the straight line in FIG. First, by differentiating the above equation 6, the following equation 7 is obtained.

′ _put = −I _put /2C・(V _ref ) ² ...7 Therefore, the equation of the above straight line becomes the following equation 8. However, in this eighth equation, K is a constant.

_{put = −I put} /2・C・V ² _{V ref} +K .

_put = I _put /2・C・V ² (V _CONT +V _OFFSET ) + K...9 Here, C and V are constants, and I _put is the above V _CONT
Since the value is proportional to , the above 9th equation becomes the following 10th equation.
It can be rewritten as Eq.

_put∝ (V _CONT +V _OFFSET )×V _GAIN ...10 This 10th equation matches the 4th equation above.

FIG. 7 is a circuit diagram showing a specific configuration of the first and second phase comparators 34 and 36 used in the above embodiment circuit. This phase comparator is connected to two D, which are always supplied with a "1" level signal as a data input and each supplied with an output signal of the voltage controlled oscillator or a reference frequency signal as a clock signal.
A phase difference detection circuit 74 includes a type flip-flop 71, 72 and an AND gate 73 to which the Q output signals of both flip-flops 71, 72 are supplied in parallel and forms a reset signal for both flip-flops 71, 72, and a power supply voltage _VDD
A P circuit is inserted in series between the application point and the ground voltage V _SS application point, and a signal obtained by inverting the Q output of the flip-flop 71 by an inverting circuit 78 and a Q output signal of the flip-flop 72 are supplied to each gate. This is a well-known circuit composed of a charge pump circuit 77 consisting of a channel MOS transistor 75 and an N-channel MOS transistor 76.

FIGS. 8 to 10 show the first and second low-pass filters 3 used in the above embodiment circuit, respectively.
FIG. 5 is a circuit diagram showing a specific configuration of components No.

The low-pass filter shown in FIG.
A resistor 83 is inserted between the output terminal 1 and the output terminal 82, and a series circuit of a resistor 84 and a capacitor 85 is inserted between the output terminal 82 and the point where the ground voltage V _SS is applied.

The low-pass filter shown in FIG.
A series circuit consisting of a resistor 86, a resistor 87, and a capacitor 88 is connected in parallel between 1 and the output terminal 82, and a series circuit consisting of a resistor 89 and a capacitor 90 is connected between the output terminal 82 and the point where the ground voltage V _SS is applied. This is what was inserted.

The low-pass filter shown in FIG. 10 is the simplest one, in which a resistor 91 is inserted between the input terminal 81 and the output terminal 82, and the output terminal 82 and the ground voltage are
A capacitor 92 is inserted between the V SS application point and the V _SS application point.

FIGS. 11 and 12 are circuit diagrams showing specific configurations of the operational amplifier 38 or the comparators 53 and 54, respectively.

The one in FIG. 11 has a differential amplifier pair 103 composed of two N-channel MOS transistors 101 and 102, and two P-channel MOS transistors 104 and 105 that act as a load for this differential amplifier pair 103.
a current mirror circuit 106 composed of a current mirror circuit 106, an N-channel MOS transistor 107 for a current source that supplies an operating current to the differential amplifier pair 103, and a P-channel MOS transistor 107 whose gate is supplied with the output signal from the differential amplifier pair 103. Transistor 108, N channel serving as current load of this transistor 108
This is a well-known device consisting of a MOS transistor 109 and a DC voltage source 110 that supplies a constant bias to the gates of the transistors 107 and 109. The gate of the transistor 101 is made a non-inverting input terminal, and V ₂ is supplied thereto by the output from the second low-pass filter 37.
The gate of the transistor 102 is set as an inverting input terminal, and the output voltage V ₁ from the first low-pass filter 35 is supplied thereto, and the output voltage V ₃ is taken out from the series connection point of the transistors 108 and 109. Note that the operational amplifier 38 has such a configuration, and the comparators 53 and 5
No. 4 differs from this only in circuit constants, and has a similar circuit configuration. In addition, comparator 5
3 and 54, the phase correction capacitor 111 in FIG. 11 is omitted.

The one in FIG. 12 is a differential amplifier pair 123 consisting of two N-channel MOS transistors 121 and 122, a constant bias is supplied to the gate, and a current source for supplying operating current to the differential amplifier pair 123. An N-channel MOS transistor 124, whose gate and source are connected to each other and serves as a load for the transistors 121 and 122, P-channel MOS transistors 125 and 126, whose gate is connected to the gate of the P-channel MOS transistor 125, and which acts as a current mirror together with this transistor 125. A P-channel MOS transistor 123 that constitutes the circuit 127, a P-channel MOS transistor 130 whose gate is connected to the gate of the P-channel MOS transistor 126, and which constitutes a current mirror circuit 129 together with this transistor 126;
It consists of a current mirror circuit 133 made up of channel MOS transistors 131 and 132 and supplied with the current flowing to the transistor 128, and the output terminals of the current mirror circuits 129 and 133 are commonly connected. The gate of the transistor 122 is set as a non-inverting input terminal, to which the output voltage V 2 from the second low-pass filter 37 is supplied, and the gate of the transistor 121 is set as an inverting input terminal, to which the output voltage V ₂ from the second low-pass filter 37 is supplied. The output voltage V ₁ from the low-pass filter 35 is supplied,
The output voltage V ₃ is taken out from the common output terminal of the current mirror circuits 129 and 133. It should be noted that the operational amplifier 38 has such a configuration, and the comparators 53 and 54 have the same circuit configuration except for the circuit constants.

It goes without saying that the present invention is not limited to the above-mentioned embodiments and can be modified in various ways. For example, in each of the circuits of the above embodiments, the polarity of each transistor may be reversed.

Furthermore, in the above embodiment circuit, the case where the voltage V ₂ outputted from the second low-pass filter 37 is supplied to the second input terminal (OFFSET) of the third voltage controlled oscillator 33 has been described; The configuration may be such that the voltage V ₁ output from the low-pass filter 35 is supplied.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide a voltage controlled oscillation circuit that does not cause variations in the characteristics of the input voltage versus the frequency of the output signal even if the process parameters vary.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a circuit according to an embodiment of the present invention, FIGS. 2 and 3 are characteristic diagrams for explaining the operation of the circuit according to the embodiment, and FIG. 4 is a partial circuit of the circuit according to the embodiment described above. FIG. 5 is a timing chart showing the operation of the circuit shown in FIG. 4, FIG. 6 is a characteristic diagram for explaining the circuit of the embodiment, and FIG. FIGS. 8 to 10 are circuit diagrams specifically showing other parts of the above embodiment circuit, and FIGS. 11 and 12 are circuit diagrams specifically showing the above embodiment circuit. Circuit diagram showing the specific configuration of the operational amplifier or comparator used, 1st
3 and 14 are circuit diagrams of conventional voltage controlled oscillation circuits, FIG. 15 is a block diagram of a conventional voltage controlled oscillation circuit different from the above, and FIG. 16 shows a part of the circuit shown in FIG. 15 above. A detailed circuit diagram,
FIG. 17 is an input/output characteristic diagram of the circuit shown in FIG. 15. 31, 32, 33...voltage controlled oscillator, 34,
36... Phase comparator, 35, 37... Low pass filter, 38... Operational amplifier.

Claims (1)

[Claims] 1 each having first to third input terminals,
equivalent inputs such that the frequency of the output signal is proportional to the sum of the voltages supplied to the first and second input terminals multiplied by a gain corresponding to the voltage supplied to the third input terminal. first to third voltage controlled oscillators having output characteristics; first means for supplying a first reference voltage to a first input terminal of the first voltage controlled oscillator; and the first voltage controlled oscillator. generating a first voltage corresponding to the phase difference between the frequency of the output signal of the oscillator and the first reference frequency signal and applying the first voltage to the second input terminal of the first voltage controlled oscillator; 2, and third means for supplying a second reference voltage to the first input terminal of the second voltage controlled oscillator, and a frequency of the output signal of the second voltage controlled oscillator and a second reference. generates a second voltage corresponding to the phase difference between the frequency signal and the second voltage;
fourth means for supplying a voltage of said first voltage and a second voltage to a second input terminal of said second voltage controlled oscillator;
fifth means for generating a third voltage according to the difference between the voltage and the voltage and supplying the third voltage in parallel to each third input terminal of the first to third voltage controlled oscillators; a sixth means for supplying the first voltage or the second voltage to a second input terminal of the third voltage controlled oscillator;
and seventh means for supplying an input voltage for controlling the frequency of the oscillation output signal to the input terminal of the voltage controlled oscillation circuit. 2. Each of the first to third voltage controlled oscillators includes voltage adding means for adding the voltages supplied to the first and second input terminals to obtain a third voltage; Current generating means that generates a current according to the supplied voltage, and capacitor charging means that alternately supplies the current generated by the current generating means to the first and second capacitors via a switch to charge the capacitors. , the first and second
1. second voltage comparison means for comparing the voltage at the terminal when the capacitor is charged with the third voltage;
It is constituted by a bistable circuit that is set and reset in accordance with the output signals of the first and second voltage comparison means, uses the output signal as an oscillation output signal, and controls the operation of the switch in accordance with this oscillation output signal. A voltage controlled oscillation circuit according to claim 1. 3. Each of the second and fourth means generates a high level according to a phase difference between the frequency of the output signal of the first or second voltage controlled oscillator and the first or second reference frequency signal. Alternatively, a phase comparator that outputs a pulse signal having a low level period, a low-pass filter to which the pulse signal output from this phase comparator is supplied, and the output voltage of this low-pass filter is applied to the first or second voltage controlled oscillator. 2. The voltage controlled oscillation circuit according to claim 1, further comprising means for feeding back the first or second voltage to a second input terminal.