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JPH0567051B2 - - Google Patents
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JPH0567051B2 - - Google Patents

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Publication number
JPH0567051B2
JPH0567051B2 JP5187686A JP5187686A JPH0567051B2 JP H0567051 B2 JPH0567051 B2 JP H0567051B2 JP 5187686 A JP5187686 A JP 5187686A JP 5187686 A JP5187686 A JP 5187686A JP H0567051 B2 JPH0567051 B2 JP H0567051B2
Authority
JP
Japan
Prior art keywords
cut
insulating film
semiconductor substrate
passivation film
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP5187686A
Other languages
Japanese (ja)
Other versions
JPS62209828A (en
Inventor
Yoshuki Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Components Co Ltd
Original Assignee
Toshiba Components Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Components Co Ltd filed Critical Toshiba Components Co Ltd
Priority to JP61051876A priority Critical patent/JPS62209828A/en
Publication of JPS62209828A publication Critical patent/JPS62209828A/en
Publication of JPH0567051B2 publication Critical patent/JPH0567051B2/ja
Granted legal-status Critical Current

Links

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  • Weting (AREA)
  • Dicing (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の製造方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a semiconductor device.

〔従来の技術〕[Conventional technology]

従来、メサ面にパツシベーシヨン膜を披着した
半導体装置の製造は、例えば第2図に示す如く、
半導体基板1の所定領域に所望の素子2を形成す
ると共に、各々の素子2を分離し分割後にメサ面
となる湾曲溝3を形成する。次いで、湾曲溝3上
にパツシベーシヨン膜4を形成する。然る後、湾
曲溝3の被切断領域をダイヤモンドスクラバーや
レーザスクラバー或はシングルプレートダイサー
等の切断刃によつてパツシベーシヨン膜4ごとに
切断して個々の素子からなる半導体装置を製造し
ていた。
Conventionally, the manufacturing of a semiconductor device in which a passivation film is applied to a mesa surface is performed as shown in FIG. 2, for example.
Desired elements 2 are formed in a predetermined region of a semiconductor substrate 1, and curved grooves 3 that become mesa surfaces after separating each element 2 are formed. Next, a passivation film 4 is formed on the curved groove 3. Thereafter, the cut region of the curved groove 3 is cut into individual passivation films 4 using a cutting blade such as a diamond scrubber, a laser scrubber, or a single plate dicer to manufacture a semiconductor device consisting of individual elements.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら、このような従来の半導体装置の
製造方法によるものでは、パツシベーシヨン膜4
等をダイヤモンドスクラバーで切断する場合は、
パツシベーシヨン膜4にクラツクや欠け等の損傷
が発生し易い。また、レーザスクラバーによつて
パツシベーシヨン膜4等を切断するものでは、レ
ーザによつてパツシベーシヨン膜4を溶解させ熱
歪を発生させ易いと共に、パツシベーシヨン膜4
の蒸気が半導体基板1に付着して汚染を起こし易
い。更に、ブレードダイサーにてパツシベーシヨ
ン膜4等を切断するものの場合もパツシベーシヨ
ン膜4にクラツク等の損傷が発生し易い。その結
果、信頼性の高い半導体装置を高歩留りで得るこ
とができない問題があつた。
However, in this conventional semiconductor device manufacturing method, the passivation film 4
When cutting etc. with a diamond scrubber,
Damage such as cracks and chips is likely to occur in the passivation film 4. In addition, in the case where the passivation film 4 and the like are cut by a laser scrubber, the passivation film 4 is easily melted by the laser and thermal strain is generated.
The vapor tends to adhere to the semiconductor substrate 1 and cause contamination. Furthermore, when the passivation film 4 and the like are cut with a blade dicer, damage such as cracks is likely to occur in the passivation film 4. As a result, there was a problem in that highly reliable semiconductor devices could not be obtained at a high yield.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、複数個の素子を形成した半導体基板
の該各々の素子を分離すると共にメサ面となる湾
曲溝の被切断領域上に所定パターンの絶縁膜を形
成する工程と、該絶縁膜を除く前記湾曲溝の露出
面を覆うパツシベーシヨン膜を形成する工程と、
前記被切断領域の所定部分を露出する開口部を前
記絶縁膜に形成する工程と、該開口部を介して露
出した被切断領域に切断刃を当接して前記半導体
基板を各々の前記素子毎の領域に分割する工程と
を具備する半導体装置の製造方法である。
The present invention includes a step of separating each element of a semiconductor substrate on which a plurality of elements are formed and forming an insulating film in a predetermined pattern on a region to be cut of a curved groove that becomes a mesa surface, and removing the insulating film. forming a passivation film covering the exposed surface of the curved groove;
forming an opening in the insulating film that exposes a predetermined portion of the region to be cut, and cutting the semiconductor substrate into individual elements by bringing a cutting blade into contact with the region to be cut exposed through the opening; A method of manufacturing a semiconductor device includes a step of dividing the semiconductor device into regions.

ここで、切断刃としては、ダイヤモンドスクラ
バー、レーザスクラバー、シングルブレーウドダ
イサー等如何なるものを使用しても良い。
Here, any cutting blade may be used, such as a diamond scrubber, a laser scrubber, a single-braided dicer, etc.

また、絶縁膜は、SiO2膜等で形成し、その開
口部は選択エツチングにより形成する。絶縁膜の
膜厚及び形状は、被切断領域を完全に覆うもので
あれば良い。
Further, the insulating film is formed of a SiO 2 film or the like, and its opening is formed by selective etching. The thickness and shape of the insulating film may be such that it completely covers the area to be cut.

また、半導体基板に形成する素子は、メサ構造
を有するものであれば如何なるものでも良い。
Furthermore, any element may be formed on the semiconductor substrate as long as it has a mesa structure.

〔作用〕[Effect]

本発明に係る半導体装置の製造方法によれば、
メサ面となる湾曲溝の被切断領域の所定部分を絶
縁膜に形成した開口部によつて露出させ、露出し
た領域を切断刃で切断する。このため、メタ面上
に残存するパツシベーシヨン膜にクラツク等の損
傷が発生するのを防止して、半導体基板の個々の
素子毎の領域に正確に分割することができる。
According to the method for manufacturing a semiconductor device according to the present invention,
A predetermined portion of the region to be cut of the curved groove, which becomes the mesa surface, is exposed through an opening formed in the insulating film, and the exposed region is cut with a cutting blade. Therefore, damage such as cracks to the passivation film remaining on the meta-plane can be prevented from occurring, and the semiconductor substrate can be accurately divided into regions for each individual element.

〔実施例〕〔Example〕

以下、本発明の実施例について図面を参照して
説明する。
Embodiments of the present invention will be described below with reference to the drawings.

先ず、第1図aに示す如く、例えば半導体基板
10にサイリスタを構成する互に導電型の異なる
半導体層を4層交互に積層した素子11を複数個
形成する。次いで、各々の素子11を分離すると
共に、メサ面となる湾曲溝12を半導体基板10
に例えば選択エツチングにて形成する。次いで、
湾曲溝12上に例えばSiO2膜からなる絶縁膜1
3を形成し、これに選択エツチングを施して湾曲
溝12の被切断領域を覆うパターンの絶縁膜13
を残存させる。
First, as shown in FIG. 1A, a plurality of elements 11 are formed, for example, on a semiconductor substrate 10, in which four semiconductor layers of different conductivity types are alternately laminated to constitute a thyristor. Next, each element 11 is separated, and a curved groove 12 serving as a mesa surface is formed on the semiconductor substrate 10.
For example, it is formed by selective etching. Then,
An insulating film 1 made of, for example, SiO 2 film is placed on the curved groove 12.
3 is formed and selectively etched thereto to form a patterned insulating film 13 covering the area to be cut of the curved groove 12.
remain.

次に、第1図Bに示す如く、短存した絶縁膜1
3の部分を除く湾曲溝12の露出面を例えば電気
泳動法によりガラスパツシベーシヨン膜14で覆
う。
Next, as shown in FIG. 1B, the short-lived insulating film 1
The exposed surface of the curved groove 12 except for the portion 3 is covered with a glass pinning film 14 by, for example, electrophoresis.

次に、第1図Cに示す如く、絶縁膜13に選択
エツチングを施して被切断領域の所定部分を露出
する開口部15を形成する。
Next, as shown in FIG. 1C, the insulating film 13 is selectively etched to form an opening 15 exposing a predetermined portion of the region to be cut.

然る後、開口部15にて露出した被切断領域に
例えばダイヤモンドスクラバーの切断刃を当接し
て半導体基板10を各々の素子11毎に分割して
半導体装置を得る。この場合、ダイヤモンドスク
ラバーが接触する部分にはパツシベーシヨン膜1
4が存在せず、しかもパツシベーシヨン膜14の
端部は絶縁膜13で保護されているので、パツシ
ベーシヨン膜14にクラツクや欠けが発生するの
を防止して、個々の半導体装置を容易に得ること
ができる。得られた半導体装置は、メサ面がクラ
ツク等の存在しない高品質のパツシベーシヨン膜
14で覆われているので、高い信頼性及び素子特
性を発揮することができる。
Thereafter, a cutting blade of, for example, a diamond scrubber is brought into contact with the region to be cut exposed in the opening 15 to divide the semiconductor substrate 10 into each element 11 to obtain a semiconductor device. In this case, a passivation film 1 is applied to the area in contact with the diamond scrubber.
4 does not exist, and the ends of the passivation film 14 are protected by the insulating film 13, cracks and chips can be prevented from occurring in the passivation film 14, and individual semiconductor devices can be easily obtained. can. The obtained semiconductor device can exhibit high reliability and device characteristics because the mesa surface is covered with a high quality passivation film 14 free of cracks and the like.

また、シングルプレードダイサやレーザスクラ
バーで半導体基板10を切断する際にも、開口部
15にて露出した被切断領域を直接切断できると
共に、パツシベーシヨン膜14にはこれらの切断
刃が全く接触せず、しかもパツシベーシヨン膜1
4の端部が絶縁膜13で覆われているので、高品
質のパツシベーシヨン膜14をメサ面上に残した
半導体装置を容易に得ることができる。
Furthermore, when cutting the semiconductor substrate 10 with a single blade dicer or laser scrubber, the area to be cut exposed through the opening 15 can be directly cut, and these cutting blades do not come into contact with the passivation film 14 at all. Moreover, the passivation film 1
Since the end portions of 4 are covered with the insulating film 13, it is possible to easily obtain a semiconductor device in which the high quality passivation film 14 remains on the mesa surface.

〔発明の効果〕〔Effect of the invention〕

以上説明した如く、本発明に係る半導体装置の
製造方法によれば、パツシベーシヨン膜にクラツ
ク等の損傷が発生するのを防止して、半導体基板
を個々の素子毎の領域に正確に分割することによ
り、信頼性の高い半導体装置を高歩留りで得るこ
とができるものである。
As explained above, according to the method for manufacturing a semiconductor device according to the present invention, damage such as cracks is prevented from occurring in the passivation film, and the semiconductor substrate is accurately divided into regions for each individual element. , it is possible to obtain highly reliable semiconductor devices at a high yield.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明の実施例を工程順に示す説明
図、第2図は、従来の半導体装置の製造方法の説
明図である。 10……半導体基板、11……素子、12……
湾曲溝、13……絶縁膜、14……パツシベーシ
ヨン膜、15……開口部。
FIG. 1 is an explanatory diagram showing an embodiment of the present invention in the order of steps, and FIG. 2 is an explanatory diagram of a conventional method of manufacturing a semiconductor device. 10...Semiconductor substrate, 11...Element, 12...
Curved groove, 13... Insulating film, 14... Passivation film, 15... Opening.

Claims (1)

【特許請求の範囲】[Claims] 1 複数個の素子を形成した半導体基板の該各々
の素子を分離すると共にメサ面となる湾曲溝の被
切断領域上に所定パターンの絶縁膜を形成する工
程と、該絶縁膜を除く前記湾曲溝の露出面を覆う
パツシベーシヨン膜を形成する工程と、前記被切
断領域の所定部分を露出する開口部を前記絶縁膜
に形成する工程と、該開口部を介して露出した被
切断領域に切断刃を当接して前記半導体基板を
各々の前記素子毎の領域に分割する工程とを具備
することを特徴とする半導体装置の製造方法。
1. A step of separating each element of a semiconductor substrate on which a plurality of elements are formed and forming an insulating film in a predetermined pattern on a region to be cut of a curved groove that becomes a mesa surface, and cutting the curved groove excluding the insulating film. forming a passivation film to cover the exposed surface of the insulating film, forming an opening in the insulating film to expose a predetermined portion of the region to be cut, and applying a cutting blade to the region to be cut exposed through the opening. A method of manufacturing a semiconductor device, comprising the step of abutting the semiconductor substrate to divide the semiconductor substrate into regions for each of the elements.
JP61051876A 1986-03-10 1986-03-10 Manufacture of semiconductor device Granted JPS62209828A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61051876A JPS62209828A (en) 1986-03-10 1986-03-10 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61051876A JPS62209828A (en) 1986-03-10 1986-03-10 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS62209828A JPS62209828A (en) 1987-09-16
JPH0567051B2 true JPH0567051B2 (en) 1993-09-24

Family

ID=12899081

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61051876A Granted JPS62209828A (en) 1986-03-10 1986-03-10 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS62209828A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1093169A4 (en) * 1999-03-31 2002-11-20 Seiko Epson Corp METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, NARROW GAP CONNECTOR, ELECTROSTATIC ACTUATOR, PIEZOELECTRIC ACTUATOR, INK JET PRINTHEAD, INK JET PRINTER, MICROMACHINE, PANEL '' LIQUID CRYSTAL DISPLAY AND DEVICE
JP6254765B2 (en) * 2013-03-22 2017-12-27 新電元工業株式会社 Mesa type semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
JPS62209828A (en) 1987-09-16

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