JPH0567969B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a one-chip microcomputer.

Conventionally, in single-chip microcomputers that have read-only memory (hereinafter referred to as ROM) built into the chip as program memory, the program start address value and interrupt program start address value are fixed, and the built-in
Some items can only be started from within the ROM, and some can be activated by setting the switching input terminal before starting.
There is an example of starting by disabling the ROM and replacing the external program memory with the address range of the internal ROM. Figure 1 is a schematic diagram of the conventional example, where program start address value 1 and interrupt program start address value 2 are hexadecimal ``0000'' and ``0040'', respectively.
Booting starts from ROM3, and in (b) the built-in ROM3 becomes invalid, and the booting address value comes to indicate external program memory 4, so that booting occurs from external program memory 4.

Generally speaking, one-chip microcomputers with built-in ROM are said to have the advantage of lower costs from the user's perspective than microcomputers without built-in ROM. However, this means that the ROM mask cost required to write an individual user's program to the built-in ROM of a 1-chip microcomputer is sufficiently low as the cost per unit. This is true when using a large amount of
For users who are only expected to use a small amount of ROM, the cost per ROM mask becomes too high, making it impossible to use a 1-chip microcomputer. For small-volume users, conventional models that can only be booted from the internal ROM require a ROM mask fee, resulting in high costs, and even those that can be booted from external program memory do not use the internal ROM at all. It becomes necessary to custom-order a ROM mask. For devices that can be booted from external program memory, it is possible that the manufacturer will supply one with the built-in ROM disabled and the user will not have to pay for the ROM mask, but in this case, a general microcomputer Similarly, products are now made up of multiple chips, and the advantages of single-chip microcomputers are lost.

As mentioned above, conventional 1-chip microcomputers are unsuitable for users who use small quantities, and for this reason, 1-chip microcomputers are used for products that are mass-produced, and multi-chip microcomputers are used for products that are only produced in small quantities. As computers were used differently, it became necessary to develop separate software for each.

The present invention eliminates the drawback of the conventional one-chip microcomputer, which is its unsuitability for users who use small quantities, and provides a one-chip microcomputer that can reduce software development costs by using the same microcomputer for both mass-produced products and small-volume products. The purpose is to provide a microcomputer.

The present invention will be described in detail below based on Examples.

FIG. 2 is a schematic diagram of an embodiment of the present invention, and 1
is a program start address value expressed in hexadecimal, 2 is an interrupt program start address value expressed in hexadecimal, 3 is an internal ROM, and 4 is an external program memory.

From now on, the address value will be expressed in hexadecimal, and the address value will be expressed as a hexadecimal number.
The address range (first address area) to which external program memory 4 is allocated is from address "0000" to address "0FFF", and the address range (second address area) to which external program memory 4 is allocated is "1000".
From address to "FFFF" address.

In Figure 2 A, the program start address value 1 is "0000" and the interrupt program start address value 2 is "0040" to start from the built-in ROM 3.
It is said that In Figure 2 B, the program start address value 1 is set to ``1000'' so that the program starts from the external program memory 4, and the interrupt program start address value 2 is set to ``1040'' so that it can be used without disabling the built-in ROM 3. There is.

FIG. 3 shows a specific example of the schematic diagram in FIG. 2, where 30 indicates a part of a one-chip microcomputer consisting of the built-in ROM 3 and its peripheral circuits, 1 is the program start address value, and 1a is the internal ROM 3. 1b is the program start address value set to indicate the memory in external program memory 4 ("1000"), 2 is the interrupt program start The address value 2a is the interrupt program start address value ("0040") set to indicate the memory in the internal ROM 3, and 2b is the interrupt program start address value ("0040") set to indicate the memory in the external program memory 4. 1040''), 3
is built-in ROM, 4 is external program memory, 5 is
6 is a change control signal generating means, 7 is a change control signal, 8 is a program counter (hereinafter referred to as PC), 9 is a PC input bus, 10 is a PC output bus, 11 is a PC decoder,
12 is the instruction bus, 13, 14, 1
5 and 16 are AND gates (hereinafter referred to as AND gates), 17 and 18 are inverters, 19 is an OR gate (hereinafter referred to as OR gate), 20, 21,
22 and 23 are output buffers, 24 is a reset signal, 25 is an interrupt signal, 26 is a PC latch signal, 27 is a program memory selection signal, 28
is a switch, and 29 is a pull-up resistor.

First, program start address value 1 and interrupt program start address value 2 are built-in.
The state set in ROM3 will be explained. When the switch 28 of the change control signal generating means 6 is closed, the change control signal 7, which had been at logic "1" (hereinafter referred to as "1") due to the pull-up resistor, becomes logic "0".
(hereinafter referred to as "0"). As a result, the outputs of AND gates 13 and 15 are fixed at "0". The output of inverter 17 becomes “1”
The outputs of AND gates 14 and 16 become the logic values of reset signal 24 and interrupt signal 25, respectively. Now, when the reset signal 24 becomes "1", the output of the AND gate 14 becomes "1", putting the output buffer 20 in the output state and outputting the program starting address value 1a to the PC input bus 9. It is connected to the reset signal 24 or OR gate 19 and sets the PC latch signal 26 to "1". When the PC latch signal 26 becomes "1", the PC 8 latches the PC input bus 9, so that the program start address value 1a outputted to the PC input bus 9 is taken into the PC 8 and outputted to the PC output bus 10. After the reset is released (after startup), the address value generated in response to the execution of an instruction in the internal or external program memory is PC8, just like a normal microcomputer.
The data are sequentially taken in and output to the PC output bus 10. PC output bus 10 is connected to built-in ROM 3, external program memory 4 and PC decoder 11. PC decoder 11 is PC output bus 1
A value of 0 is decoded and a program memory selection signal 27 is output.

In this embodiment, if the PC output bus has a value from "0000" to "0FFF", the program memory selection signal 27 is set to "1" to select the built-in ROM 3.
So, if there is a value between “1000” and “FFFF”, it will be “0” to select external program memory 4.
becomes. Since the current value of PC output bus 10 is "0000", program memory selection signal 27 is built-in.
The built-in ROM 3 outputs the memory contents at address "0000" to the instruction bus 12 according to the value on the PC output bus 10.
At this time, the external program memory 4 is in a non-selected state because it is supplied with the memory selection signal 27 through the inverter 18.

Next, consider the case where the interrupt signal 25 becomes "1" while the switch 28 remains closed. When the interrupt signal 25 becomes “1”, AND gate 1
The output of 6 becomes "1", puts the output buffer 22 into the output state, and outputs the interrupt program start address value 2a to the PC input bus 9. Interrupt signal 25 is also connected to OR gate 19 and causes PC latch signal 26 to be "1". Thereafter, the memory contents at address "0040" in the built-in ROM 3 are output to the instruction bus 12 in the same manner as in the case of the reset signal.

Next, the state in which the program start address value 1 and the interrupt program start address value 2 are set in the external program memory 4 will be explained.
When the switch 28 of the change control signal generating means 6 is opened, the change control signal 7 is set to "1" by the pull-up resistor 29. As a result, the output of inverter 17 becomes "0" and AND gates 14 and 16
The output of is fixed to "0". Since the change control signal 7 is “1”, AND gates 13 and 15
The outputs thereof become the logic values of the reset signal 24 and interrupt signal 25, respectively. Now, when the reset signal 24 becomes "1", the output of the AND gate 13 becomes "1", putting the output buffer 21 in the output state and outputting the program starting address value 1b to the PC input bus 9. The reset signal 24 also sets the PC latch signal 26 to "1", causing the PC 8 to latch the program starting address value 1b. The program start address value 1b latched to PC8 is PC
The value is output to the output bus 10, and the PC decoder 11 decodes the value and outputs the program memory selection signal 27. In this case, since the program start address value 1b is "1000", the program memory selection signal 27 becomes "0" and the output of the inverter 18 becomes "1", so that the external program memory 4 is selected. . The external program memory 4 outputs the memory contents at address "1000" to the instruction bus 12 in accordance with the value on the PC output bus 10. At this time, the built-in program is in a non-selected state.

Next, consider the case where the interrupt signal 25 becomes "1" while the switch 28 remains open. When the interrupt signal 25 becomes “1”, AND gate 1
5 becomes "1", putting the output buffer 23 into the output state and outputting the interrupt program starting address value 2b to the PC input bus 9. The interrupt signal 25 also sets the PC latch signal 26 to "1", causing the PC 8 to latch the interrupt program start address value 2b and output it to the PC output bus 10. The PC decoder 11 decodes the value "1040" of the interrupt program start address value 2b. Then, the program memory selection signal 27 is set to "0". As a result, the external program memory 4 outputs the memory contents at address "1040" to the instruction bus 12.

In the above embodiment, the built-in ROM 3 is selected or unselected depending on the address value of the PC 8, and it is possible to execute the program in the built-in ROM 3 regardless of the logical value of the change control signal 7. It's summery.

In the embodiment of FIG. 3, the switch 28 may be an equivalent switch based on a pattern on the chip, and the change control signal generating means 6 may be a flip-flop that can be set and reset by a program. Also, when you want to prepare multiple interrupt program startup addresses 2, interrupt program startup addresses 2a, 2b, AND gate 15,
16 and the output buffers 22 and 23 as one set and the number may be increased.

As described above, according to the present invention, the program in the built-in ROM can be executed even if the program start address value and the interrupt program start address value are within the range of either the built-in ROM or the external program memory.

In other words, programs in the built-in ROM can be executed even when booted from external program memory.For example, if the built-in ROM has a chip containing subroutines of programs that are commonly used in various applications. This means that the chip can be shared by many users.

In this case, the user writes an independently developed program to external program memory, but since the program in the built-in ROM can be used at this time, compared to existing microcomputers configured with multiple chips, the user can save program development time and write the external program memory. You can expect the effect of saving memory.
Also, from the manufacturer's point of view, such chips
The cost per unit of ROM mask can be estimated to be small, which leads to eliminating the cost disadvantage for users who use small quantities, which existed with existing 1-chip microcomputers. That is, the present invention can eliminate the unsuitability of existing one-chip microcomputers for users who use them in small quantities. As a result, if the one-chip microcomputer according to the present invention is used from large-volume users to small-volume users, the effects of software accumulation (accumulation of programs, accumulation of human ability, etc.) and the standardization of development systems will be achieved. etc.,
This also has the effect of reducing software development costs.

Furthermore, the present invention changes the startup sequence in a fixed program storage area such as an internal program memory to a variable program storage area such as an external program memory by changing the program startup address value at the time of an interrupt after a reset. You can take it to the area, so
In other words, important parts that determine the character and function of the system, such as initialization after initialization and routines corresponding to interrupts, can be stored in the variable area, which has the effect of making it easier to change the system.

Furthermore, for example, if you store a subroutine set or the main software of the OS in the internal program memory built into the chip, you can store the BIOS and other software that needs to be characterized for each product in the external program memory, allowing you to use various products. You can also make one. In this case, by preparing a one-chip microcomputer with built-in common software, a significant cost reduction can be achieved.

In the above explanation, we have described the case where the manufacturer prepares the built-in ROM, but in the case of a user who handles several types of products, the user can create a one-chip microcomputer with a built-in standard program by standardizing the programs used by each product. It can be said that the user's form wear is fixed on the chip.

[Brief explanation of drawings]

Figures 1A and 2B are a schematic diagram of the conventional program start address value and interrupt program start address value changing between built-in ROM and external program memory, and Figure 2A and 2B are the program start address value and interrupt program of the present invention. FIG. 3 is a schematic diagram of changing the starting address value between the built-in ROM and the external program memory, and is a diagram showing an embodiment of the present invention. 1 is program start address value, 2 is interrupt program start address value, 3 is built-in
ROM, 4 is an external program memory, 5 is program start address value and interrupt program start address value changing means, 6 is change control signal generating means, and 7 is a change control signal.

Claims (1)

[Scope of Claims] 1. In a one-chip microcomputer in which a read-only memory is built into a chip as an internal program memory, a first memory to which the internal program memory is allocated is provided.
An internal program start address value indicating a first address in an address area of the chip and an external program start address value indicating a second address in a second address area to which an external program memory provided separately from the chip is allocated are set. a plurality of internal interrupt program start address values indicating a third address in the first address area and a plurality of external interrupt program start address values indicating a fourth address in the second address area; The internal program starting address value and the external program are set in response to a change control signal output from an interrupt program starting address value setting means in which an address area value is set, and a reset signal input and an address value change control signal generating means. a first output buffer that outputs one of the program startup address values; and a first output buffer that outputs one of the program startup address values, and the interrupt program startup address value in response to a change control signal from a program startup address value change control signal generation means when an interrupt signal is input. a second output buffer for outputting a value indicating one address corresponding to the interrupt signal, either the third address or the fourth address, from the setting means to the program counter input bus; and when the reset signal is input or When the interrupt signal is input, the first, second, third, or fourth address on the program counter input bus is latched, and when the reset signal is input or the interrupt signal is input, the first address area or the fourth address is latched. a program counter that latches an address in the second address area; and a program memory selection signal that decodes the address latched in the program counter to determine whether the internal program memory or the external program memory responds. 1. A one-chip microcomputer comprising: a decoder for generating the program counter; and an output bus for outputting the address latched in the program counter to the internal program memory, the external program memory, and the decoder.