JPH0568032B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention uses a digital magnetic recording and reproducing device to track jitter and skew that occur when each digital data of a multitrack is reproduced. The present invention relates to a deskew circuit that removes the jitter and skew by sequentially storing reproduced data in a memory.

[Conventional technology]

Conventionally, there has been a device of this type as shown in FIG. In FIG. 2, reproduction heads 1 ₁ , 1
The reproduced analog waveforms read from the tape by ₂ ,...In are sent to digital signal reproduction circuits 21, _2, ...In, respectively.
Frame synchronization detectors 3 ₁ , 3 ₂ , ... 3n detect the start of each frame of the signal digitized by 2 ₂ , . Regenerated clock generators 4 ₁ , 4 ₂ , which extract clock information from the clock information (self-clocking)
. . 4n are input to each of S/P converters 5 ₁ , 5 ₂ , . Also, synchronization signals extracted from the reproduced digital data series by frame synchronization detectors 3 ₁ , 3 ₂ , ... 3n
x ₁ , x ₂ , . . . These synchronization signals x ₁ , x ₂ , . . . xn increment the frame address counters _{6 1 , 6 2 ,} . On the other hand, the reproduced clocks y ₁ , y ₂ ,... extracted from the reproduced data series by the reproduced clock generator are
yn is word address counter 7 ₁ , 7 ₂ ,...7n
is incremented, and the S/P converter 5
₁ , 5 ₂ , . . . 5n shift clocks. S/P
The reproduced data D ₁ , D ₂ , ...Dn converted word by word into parallel signals by the converters 5 ₁ , 5 ₂ , ...5n are as follows:
The data are stored at predetermined addresses in the RAMs _{8 1 ,} 8 ₂ , . . . 8n using the frame address A 1 and word address A ₂ .

[Problem that the invention seeks to solve]

The dequeue circuit in the multi-track magnetic recording/reproducing device described above is configured as described above.
In the above configuration, as the number of tracks increases, a correspondingly large number of frame address counters are required, resulting in uneconomical performance and increased costs due to increased circuit scale.

[Means for solving problems]

This invention was made by focusing on such a problem, and by limiting the maximum value of the skew amount within a certain range, the frame address counter is driven as one counter regardless of the number of tracks, and the circuit The aim is to reduce the scale of the project. That is, the present invention provides a frame synchronization detector for detecting a frame synchronization signal from a reproduced data sequence of each track in a multi-track magnetic recording and reproducing apparatus that distributes binary information to a plurality of tracks and records it on a tape.
A regenerated clock generator extracts a regenerated clock from the regenerated data sequence, a synchronization gate adds signals of each track output from the frame synchronization detector, and converts the pulse sequence output from the synchronization gate into one frame. A hold circuit that adjusts the pulse width so that one pulse is output, a frame address counter that counts signals common to each track output from the hold circuit and creates a frame address, and a regenerated clock generator that outputs the clock. A word address counter that counts the reproduced clock in fixed word units for each track, and a serial signal and a parallel signal for each word of reproduced data based on the respective outputs of the word address counter and the reproduced clock generator. It has an S/P converter that converts the playback data to , the reproduced data output in word units from the S/P converter is stored in a predetermined memory.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to FIG. 1, using the same reference numerals for the same parts as in FIG.

In FIG. 1, frame synchronization detectors 3 ₁ , 3 ₂ ,
The synchronous signals x ₁ , x ₂ , . . . In the circuit 100, it is converted into an MM synchronization signal Z as shown in FIG. 3, which generates a pulse once per frame. This hold circuit 100
The time constant t ₁ of is made longer than the maximum range t.
To create the MM synchronization signal Z, it is not necessarily necessary to use a one-shot multivibrator.
For example, it can be configured with an RS latch or the like. The frame address counter 60 is incremented by the MM synchronization signal Z and outputs a frame address _A3 common to each track. In this way S/
The reproduced data D ₁ , D ₂ , ... Dn subjected to S/P conversion word by word by the P converters 5 ₁ , 5 ₂ , ... 5n are as follows:
A frame address A ₃ common to each track as shown in Figure 3, and a word address A ₂ for each track.
The data are stored at predetermined addresses in the RAMs 8 ₁ , 8 ₂ , . . . , 8n. In this example, RAM8 ₁ , 8 ₂ ,...
8n is used exclusively for each track, but it is also possible to share the data of each track with one RAM.

〔effect〕

As described above, the deskew circuit according to the present invention is
By sharing the frame address counters 6 ₁ , 6 _{2 .} . . 6n that existed for each track with one frame address counter 60, the maximum value of the skew amount can be kept within a certain range t, for example, 20 to 30 bits. The multi-track magnetic recording and reproducing apparatus, which is currently available, is economical because it is possible to specify addresses in memory without being affected by skew, and it is possible to suppress an increase in circuit scale due to an increase in the number of tracks.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a deskew circuit showing an embodiment of the present invention, FIG. 2 is a block diagram showing an example of a deskew circuit of a conventional multitrack magnetic recording/reproducing apparatus, and FIG. 3 is an operation of this embodiment. It is a time chart diagram for explanation. x ₁ , x ₂ ,...xn...frame synchronization signal, 3 ₁ , 3
₂ ,...3n...Frame _{synchronization} detector, _41,42 ,
...4n...Regenerated clock generator, 90...Synchronization gate, 100...Hold circuit, _A3 ...Frame address, 60...Frame address counter, ₇₁ , ₇₂ ,...7n...Word address counter, 5 ₁ , 5 ₂ ,...5n...S/P converter, 8 ₁ ,
8 ₂ ,...8n...Memory.

Claims (1)

[Claims] 1. In a multi-track magnetic recording/reproducing device that distributes binary information to a plurality of tracks and records it on a tape, a frame synchronization detector detects a frame synchronization signal from the reproduction data series of each track, and the reproduction data series A regenerated clock generator extracts a regenerated clock from the frame, a synchronization gate adds the signals of each track output from the frame synchronization detector, and a pulse is generated once per frame from the pulse sequence output from the synchronization gate. A hold circuit that adjusts the pulse width so that the pulse width is output, a frame address counter that counts signals common to each track output from the hold circuit and creates a frame address, and a regenerated clock outputted by the regenerated clock generator. A word address counter that counts the data in fixed word units for each track, and an S that converts serial signals into parallel signals for each word of the reproduced data based on the respective outputs of the word address counter and the reproduced clock generator. It has an S/P converter and a memory for storing playback data, and uses the frame address common to each track outputted from the frame address counter and the word address for each track outputted from the word address counter. A deskew circuit in a multi-track magnetic recording and reproducing apparatus is configured to store reproduced data output in units of words from a P converter in a predetermined memory.