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JPH0568868B2 - - Google Patents
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JPH0568868B2 - - Google Patents

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Publication number
JPH0568868B2
JPH0568868B2 JP60027238A JP2723885A JPH0568868B2 JP H0568868 B2 JPH0568868 B2 JP H0568868B2 JP 60027238 A JP60027238 A JP 60027238A JP 2723885 A JP2723885 A JP 2723885A JP H0568868 B2 JPH0568868 B2 JP H0568868B2
Authority
JP
Japan
Prior art keywords
region
regions
conductivity type
semiconductor substrate
opposite conductivity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60027238A
Other languages
Japanese (ja)
Other versions
JPS61185979A (en
Inventor
Yutaka Hayashi
Yoshimitsu Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology, Matsushita Electric Works Ltd filed Critical Agency of Industrial Science and Technology
Priority to JP60027238A priority Critical patent/JPS61185979A/en
Publication of JPS61185979A publication Critical patent/JPS61185979A/en
Publication of JPH0568868B2 publication Critical patent/JPH0568868B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10FINORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F30/00Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors
    • H10F30/20Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors

Landscapes

  • Light Receiving Elements (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Description

【発明の詳細な説明】 〔技術分野〕 この発明は、光電変換素子、殊に高電圧の発生
が可能な集積型変換素子に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a photoelectric conversion element, and particularly to an integrated type conversion element capable of generating high voltage.

〔背景技術〕[Background technology]

フオトダイオードを第1図のように半導体基板
中に集積する場合、たとえば、第2図のような複
数個のPNダイオードを、半導基板4表面の絶縁
膜上の導電膜6で、第2図および第3図のように
接続する方法が考えられるが、この場合にはバイ
ポーラトランジスタのダーリントン接続となり、
出力電圧・電流がわずかしか得られなかつた。
When photodiodes are integrated into a semiconductor substrate as shown in FIG. 1, for example, a plurality of PN diodes as shown in FIG. A connection method as shown in Figure 3 can be considered, but in this case, it is a Darlington connection of bipolar transistors,
Only a small amount of output voltage and current could be obtained.

〔発明の目的〕[Purpose of the invention]

そこで、この発明は、寄生バイポーラトランジ
スタによるもれ電流を解消し、効率良く高電圧を
発生させることを目的とするものである。
Therefore, an object of the present invention is to eliminate the leakage current caused by the parasitic bipolar transistor and efficiently generate high voltage.

〔発明の開示〕[Disclosure of the invention]

上記目的を達成するため、この発明は、第一導
電型半導体基板と、この基板表面部分に離間して
形成された複数個の逆導電型の第一領域と、これ
ら逆導電型の第一領域中に形成された第一導電型
を第二領域と、各第二領域の表面に形成された逆
導電型の第三領域と、前記半導体基板表面に形成
された絶縁膜と、絶縁膜上に設けられ前記第一領
域のひとつおよびその表面に形成された第二領域
を電気接続するとともに、これを、これらから離
間した他の第一領域中に形成された第三領域に電
気接続する導電膜とをそれぞれ備え、前記第一領
域の前記半導体基板との接合深さをxj1、前記第
二領域の前記第一領域との接合深さをxj2、前記
第三領域の前記第二領域との接合深さをxj3とし、
互いに接続される第一の領域の数をnとし、入射
光の吸収係数をαとするとき、これらが、 1>exp(−α・xj1+xj2/2) +nexp(−α・xj2+xj3/2) なる関係式を満足するように、前記の各接合深さ
xj1、xj2、xj3が定められていることを特徴とする
集積型光電変換素子を要旨とする。
In order to achieve the above object, the present invention provides a semiconductor substrate of a first conductivity type, a plurality of first regions of opposite conductivity type formed at intervals on a surface portion of the substrate, and first regions of the opposite conductivity type. a third region of the opposite conductivity type formed on the surface of each second region; an insulating film formed on the surface of the semiconductor substrate; a conductive film that electrically connects one of the first regions and a second region formed on the surface thereof, and electrically connects this to a third region formed in another first region spaced apart from these; and x j1 is the junction depth of the first region with the semiconductor substrate, x j2 is the junction depth of the second region with the first region, and x j2 is the junction depth of the second region with the semiconductor substrate, and Let the junction depth of be x j3 ,
When the number of first regions connected to each other is n and the absorption coefficient of incident light is α, these are as follows: 1>exp(−α・x j1 +x j2 /2) +nexp(−α・x j2 +x j3 /2) Each of the above welding depths is adjusted so as to satisfy the relational expression:
The gist of the present invention is an integrated photoelectric conversion element characterized in that x j1 , x j2 , and x j3 are determined.

以下に、この発明を、その実施例をあらわす図
面に基いて、詳しく説明する。第4図はこの発明
の実施例の断面を示し、1,1aはN型の第一領
域であつて、P型の基板4の表面部分において互
いに離間するよう形成されている。2,2aは第
一領域1,1a表面に形成されたP型領域であ
る。3,3aは第二領域2,2aの表面に形成さ
れたP型の第三領域である。これら三つの領域
1,1a,2,2a,3,3aは、P型基板4に
対してN−P−N三重拡散で形成される。5は基
板4の表面に形成された絶縁膜、7,7はチヤネ
ルストツパーのP+拡散領域であり、8,8aは
チヤネルストツパーとのオーミツク接触のための
N+拡散領域である。6は絶縁膜5上に設けられ
た導電薄膜であり、一方では第一領域1aおよび
その表面に形成された第二領域2aを電気的に接
続するとともに、他方では、これらの領域1a,
2aを、これらから離間して形成された第一領域
1内の第三領域3に電気的に接続している。
Hereinafter, the present invention will be explained in detail based on drawings showing embodiments thereof. FIG. 4 shows a cross section of an embodiment of the present invention, in which numerals 1 and 1a are N-type first regions, which are formed so as to be spaced apart from each other on the surface portion of a P-type substrate 4. FIG. 2 and 2a are P-type regions formed on the surfaces of the first regions 1 and 1a. 3 and 3a are P-type third regions formed on the surfaces of the second regions 2 and 2a. These three regions 1, 1a, 2, 2a, 3, 3a are formed in the P-type substrate 4 by N-P-N triple diffusion. 5 is an insulating film formed on the surface of the substrate 4, 7, 7 are P + diffusion regions of the channel stopper, and 8, 8a are for ohmic contact with the channel stopper.
N + diffusion region. Reference numeral 6 denotes a conductive thin film provided on the insulating film 5, which electrically connects the first region 1a and the second region 2a formed on the surface thereof on the one hand, and connects these regions 1a,
2a is electrically connected to a third region 3 in the first region 1 formed apart from these.

第5図は、この発明の第二の実施例の断面を示
し、N+埋込拡散層9,9aを有するP型基板4
上にN型のエピタキシヤル成長層が形成され、そ
の中に、P型の分離拡散層7,7aによつて互い
に離間された第一領域1,1aが形成されてい
る。P型の第二領域2,2aおよびN型の第三領
域3,3aは、第一領域1,1a内に二重拡散で
形成されている。8,8aはチヤネルストツパー
およびオーミツク接触のために設けられたN+
である。6は絶縁膜5上に形成された導電薄膜で
あり、離間された第三領域3と第二領域2aを電
気的に接続するとともに、第一領域と第二領域と
を、領域8と2および8aと2aというように電
気的に接続している。
FIG. 5 shows a cross section of a second embodiment of the invention, in which a P-type substrate 4 having N + buried diffusion layers 9, 9a is shown.
An N-type epitaxial growth layer is formed thereon, and first regions 1, 1a are formed therein, separated from each other by P-type isolation diffusion layers 7, 7a. The P-type second regions 2, 2a and the N-type third regions 3, 3a are formed in the first regions 1, 1a by double diffusion. 8 and 8a are N + layers provided for channel stoppers and ohmic contacts. Reference numeral 6 denotes a conductive thin film formed on the insulating film 5, which electrically connects the separated third region 3 and second region 2a, and connects the first region and second region to regions 8, 2, and 8a and 2a are electrically connected.

第6図は上記実施例の断面をあらわすものであ
つて、xj1、xj2、xj3はそれぞれ第一領域1,1
a、第二領域2,2a、第三領域3,3aの接合
深さ(拡散深さ)である。
FIG. 6 shows a cross section of the above embodiment, where x j1 , x j2 , and x j3 are first regions 1 and 1, respectively.
a is the junction depth (diffusion depth) of the second regions 2, 2a and the third regions 3, 3a.

第一領域と第二領域2と第三領域3とから形成
されるNPN接合において、第一領域1と第二領
域2が電気的に接続されているため、これら三つ
の領域から寄生的なバイポーラトランジスタは形
成されない。同様に、基板4と第一領域1と第二
領域2とから形成されるPNP接合においても、
寄生的なバイポーラトランジスタは形成されな
い。
In the NPN junction formed from the first region, the second region 2, and the third region 3, since the first region 1 and the second region 2 are electrically connected, parasitic bipolar No transistor is formed. Similarly, in the PNP junction formed from the substrate 4, the first region 1, and the second region 2,
No parasitic bipolar transistors are formed.

したがつて、この発明の素子構造の等価回路
は、第3図に示したようなトランジスタを含む回
路ではなく、第7図に示したようなダイオードだ
けから構成される回路となり、従来例で問題とさ
れていたような、トランジスタを介して増幅され
るもれ電流が解消される。
Therefore, the equivalent circuit of the element structure of the present invention is not a circuit including transistors as shown in FIG. 3, but a circuit consisting only of diodes as shown in FIG. 7, which eliminates the problems in the conventional example. This eliminates the leakage current that is amplified through transistors, which was thought to be the case.

この発明の素子構造では、ダイオードからの漏
れ電流(第4図のIL)を少なくすることが必要で
ある。
In the device structure of the present invention, it is necessary to reduce leakage current from the diode ( IL in FIG. 4).

いま、第三領域3,3aの表面に波長λの光が
密度Φ0で入射すると、その吸収係数をαとすれ
ば、光電流IPは、 IP=Φ0{1−exp(−αxj1+xj2/2)} ……(1) で与えられるが、同時に、基板4側へのもれ電流
ILも、 IL=Φ0exp(−αxj2+xj3/2) ……(2) だけ存在することになる。
Now, when light with a wavelength λ is incident on the surface of the third region 3, 3a at a density Φ 0 , and its absorption coefficient is α, the photocurrent I P is I P0 {1−exp(−αx j1 + x j2 /2)} ...(1) However, at the same time, the leakage current to the board 4 side
I L also exists by I L = Φ 0 exp (−αx j2 + x j3 /2) ... (2).

第6図に示した構造からなるフオトダイオード
を、第4図または第5図のごとくにしてn個直列
接続した場合の等価回路を第7図に示す。この回
路の端子間から光電流を得るためには、 IP>nIL となることが必要であり、したがつて、前記(1)、
(2)式より、 1>exp(−αxj1+xj2/2) +nexp(−αxj2+xj3/2) ……(3) なる関係式の満たされることが必要となるのであ
る。
FIG. 7 shows an equivalent circuit when n photodiodes having the structure shown in FIG. 6 are connected in series as shown in FIG. 4 or 5. In order to obtain a photocurrent between the terminals of this circuit, it is necessary that I P > nI L , and therefore, (1) above,
From equation (2), it is necessary that the following relational expression 1>exp(-αx j1 +x j2 /2) +nexp(-αx j2 +x j3 /2)...(3) be satisfied.

たとえば、xj1=16μm、xj2=14μm、xj3=9μm
として、フオトダイオードを10個直列接続した場
合(n=10)、赤色の入射光λ=700nmに対して
α=2×103cm-1であるから、これを上記関係式
(3)の右辺に代入して計算すると約0.59となり、左
辺の1より小であるから、関係式(3)を満足するよ
うになる。すなわち、所望の光電流を得ることが
できる。
For example, x j1 = 16 μm, x j2 = 14 μm, x j3 = 9 μm
If 10 photodiodes are connected in series (n = 10), α = 2 × 10 3 cm -1 for red incident light λ = 700 nm, so this can be expressed as the above relational expression.
When calculated by substituting it into the right-hand side of (3), it is approximately 0.59, which is smaller than 1 on the left-hand side, so it satisfies relational expression (3). That is, a desired photocurrent can be obtained.

実施例の導電型P、Nが逆転したものも、この
発明に含まれる。
The present invention also includes those in which the conductivity types P and N of the embodiments are reversed.

〔発明の効果〕 この発明にかかる集積型光電変換素子は、以上
のごとく構成されているから、これによれは、モ
ノリシツク基板上で直列接続配置されたダイオー
ドから、接続個数分昇圧された高い開放電圧を有
する光起電力が得られる。
[Effects of the Invention] Since the integrated photoelectric conversion element according to the present invention is configured as described above, it is possible to obtain a high open circuit voltage boosted by the number of diodes connected in series on a monolithic substrate. A photovoltaic force with voltage is obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は直列接続されたダイオードを示す説明
図、第2図は第1図のダイオード直列回路を実現
した集積型光電変換素子をあらわす断面図、第3
図は第2図の素子の等価回路をあらわす説明図、
第4図はこの発明の第一実施例をあらわす部分的
断面図、第5図は第二実施例をあらわす部分的断
面図、第6図は実施例の要部簡略断面図、第7図
は実施例の等価回路をあらわす説明図である。 1,1a……N型の第一領域、2,2a……P
型の第二領域、3,3a……N型の第三領域、5
……絶縁膜、6……導電膜。
Fig. 1 is an explanatory diagram showing diodes connected in series, Fig. 2 is a cross-sectional view showing an integrated photoelectric conversion element that realizes the diode series circuit of Fig. 1, and Fig. 3 is an explanatory diagram showing diodes connected in series.
The figure is an explanatory diagram showing the equivalent circuit of the element in Figure 2,
4 is a partial sectional view showing the first embodiment of this invention, FIG. 5 is a partial sectional view showing the second embodiment, FIG. 6 is a simplified sectional view of the main part of the embodiment, and FIG. 7 is a partial sectional view showing the second embodiment. It is an explanatory diagram showing an equivalent circuit of an example. 1, 1a...N-type first region, 2, 2a...P
Second region of type, 3, 3a...Third region of N type, 5
...Insulating film, 6...Conductive film.

Claims (1)

【特許請求の範囲】 1 第一導電型半導体基板と、この基板表面部分
に離間して形成された複数個の逆導電型の第一領
域と、これら逆導電型の第一領域中に形成された
第一導電型の第二領域と、各第二領域の表面に形
成された逆導電型の第三領域と、前記半導体基板
表面に形成された絶縁膜と、絶縁膜上に設けられ
前記第一領域のひとつおよびその表面に形成され
た第二領域を電気接続するとともに、これらを、
これらから離間した他の第一領域中に形成された
第三領域に電気接続する導電膜とをそれぞれ備
え、前記第一領域の前記半導体基板との接合深さ
をxj1、前記第二領域の前記第一領域との接合深
さをxj2、前記第三領域の前記第二領域との接合
深さをxj3とし、互いに接続される第一の領域の
数をnとし、入射光の吸収係数をαとするとき、
これらが、 1>exp(−α・xj1+xj2/2) +nexp(−α・xj2+xj3/2) なる関係式を満足するように、前記の各接合深さ
xj1、xj2、xj3が定められていることを特徴とする
集積型光電変換素子。
[Claims] 1. A semiconductor substrate of a first conductivity type, a plurality of first regions of opposite conductivity type formed at intervals on a surface portion of the substrate, and a plurality of first regions of opposite conductivity type formed in these first regions of opposite conductivity type. a second region of a first conductivity type formed on the surface of each second region; a third region of an opposite conductivity type formed on the surface of each second region; an insulating film formed on the surface of the semiconductor substrate; electrically connecting one of the regions and a second region formed on the surface thereof;
a conductive film electrically connected to a third region formed in another first region spaced apart from these, the junction depth of the first region with the semiconductor substrate is x j1 , and the depth of the junction of the second region with the semiconductor substrate is x j1 . The junction depth with the first region is x j2 , the junction depth of the third region with the second region is x j3 , the number of first regions connected to each other is n, and the absorption of incident light is When the coefficient is α,
The depths of each of the above joints are adjusted so that these satisfy the following relational expressions: 1>exp(-α・x j1 +x j2 /2) +nexp(−α・x j2 +x j3 /2)
An integrated photoelectric conversion element characterized in that x j1 , x j2 , and x j3 are determined.
JP60027238A 1985-02-13 1985-02-13 Integrated photoelectric conversion element Granted JPS61185979A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60027238A JPS61185979A (en) 1985-02-13 1985-02-13 Integrated photoelectric conversion element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60027238A JPS61185979A (en) 1985-02-13 1985-02-13 Integrated photoelectric conversion element

Publications (2)

Publication Number Publication Date
JPS61185979A JPS61185979A (en) 1986-08-19
JPH0568868B2 true JPH0568868B2 (en) 1993-09-29

Family

ID=12215491

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60027238A Granted JPS61185979A (en) 1985-02-13 1985-02-13 Integrated photoelectric conversion element

Country Status (1)

Country Link
JP (1) JPS61185979A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6216567A (en) * 1985-07-15 1987-01-24 Sharp Corp Light-receiving element incorporated in circuit
US5162887A (en) * 1988-10-31 1992-11-10 Texas Instruments Incorporated Buried junction photodiode
EP0579045B1 (en) * 1992-07-16 1995-02-22 Landis & Gyr Technology Innovation AG Device with an integrated colour selective photodiode and an amplifier connected to the photodiode

Also Published As

Publication number Publication date
JPS61185979A (en) 1986-08-19

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