JPH0569232B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a character generating device that has a simple circuit configuration and can perform bold processing in a short processing time.

(Prior Art) Electronic printers and display devices have been widely used as peripheral devices for office automation and as output devices for information processing devices.
There are various display formats for characters, codes, numbers, etc. (hereinafter referred to as "characters") displayed on these devices in response to society's needs for diversification of expression. One of them is to increase the width of characters. There is a form called bold character that expresses.

In a raster scan type character generating device, one raster image as shown in FIG. 8B obtained by raster scanning a normal character pattern as shown in FIG. When outputting as serial dot data as shown in Figure C, if only the dots representing black are latched and output as latch data as shown in Figure D, the bolded characters as shown in Figure E will be output. generated.

On the other hand, as disclosed in Japanese Patent Application Laid-Open No. 59-41052,
In a character generating device having an image memory, a method has been proposed in which a bold character pattern is formed from the character pattern stored in the image memory, and bold processing is performed by combining the two.

However, if you want to bold only a certain character among multiple generated characters, in the former method, it is necessary to latch only the pixel data corresponding to the width and height of the character you want to bold. The control circuit for enable control becomes complicated.

In addition, in the latter method, the character pattern data stored in the image memory is read out and slightly shifted to generate a bold character pattern, and after combining both character patterns, it is written again to the image memory, which takes processing time. The problem is that it is long. In order to shorten this processing time, a method of preparing a separate memory for storing bold character patterns has been proposed, but this increases the memory capacity and increases cost.

(Objective and Structure of the Invention) The present invention has been made in view of the above points, and is capable of performing bold processing for any character size in a short processing time without increasing the amount of memory with a simple circuit configuration. In order to achieve this purpose, the character pattern data of the character to be printed or displayed is read out in predetermined multiple bit units from the character pattern memory that stores the character pattern data of multiple characters, and Some bits of the character pattern data consisting of bits are held until the next readout, and when the bold processing finger is touched, the bits held during the previous readout and the data bus of the character pattern data currently being read are It is configured to take the logical sum of adjacent bits of .

(Example) The present invention will be explained below based on the drawings.

FIG. 1 is a block diagram of an embodiment of a character generating device according to the present invention, and the portion surrounded by a broken line is the character generating device according to the present invention.

In the figure, 1 is a host device such as a host computer that transmits a character signal including code data of a character to be printed and attribute data such as emphasis for that character; 2 is a character generator according to the present invention;
3 is a printer.

In the character generator 2, 21 is the host device 1
An interface circuit 22 receives character signals sent from the interface circuit 21 and processes them into a format necessary for internal control of the device based on the data received via the interface circuit 21. A microprocessor 23 is a text buffer memory 2 that stores data sent from the host device 1 in the form of internal codes and control codes of the device.
4 is a character pattern memory storing character pattern data; 25 is a direct memory access controller for transmitting the character pattern data stored in the character pattern memory 24 to the printer 3;
26 is a bold processing circuit for performing bold processing on character patterns, 27 is a memory for storing character pattern data transmitted from the direct memory access controller 25 in the form of a dot image to be output to the printer 3, and 28 is a printer. This is a printer interface for outputting data to be printed on the printer.

FIG. 2 shows an example of the bold processing circuit 26, in which a latch circuit 4 and AND circuits 5 to 8 are used to perform bold processing on the character pattern data read from the character pattern memory 24 as necessary.
and OR circuits 9 to 12 are connected as shown. The latch circuit 4 has a reset terminal R to which a reset command "0" is input for each predetermined bit, and an enable terminal E to which a bold command "1" included in the attribute data transmitted from the host device 1 is input. is provided.

Next, bold processing according to the present invention will be explained.

A character signal transmitted from the host device 1 is input through the interface circuit 21, processed by the microprocessor 22 into the form shown in FIG. 3, and stored in the text buffer 23.
b shown in FIG. 3 represents a code corresponding to a character; for example, code 20 is the alphabet character “ ” (space), code 41 is the alphabet letter “A”, code 42 is “B”, and code 43 is “C”. ”. On the other hand, a shown in FIG. 3 represents attribute data for each character. For example, data "00" represents a regular printing command, data "01"
indicates bold printing. FIG. 3C is an example of printed characters.

After a certain amount (for example, one line or one page) of character pattern data is stored in the text buffer memory 23, the direct memory access controller 25 stores the contents of the text buffer memory 23 and the address data of the character pattern memory 24. The direct memory access controller 25 reads the character pattern data stored in the character pattern memory 24 via the bold control circuit 26 in units of a predetermined plurality of bits and transfers it to the read memory 27.

Here, the bold processing by the bold processing circuit 26 will be explained.

Now, let us consider the case where the character signal from the host device 1 is processed and, as a result, the alphanumeric character "A" is subjected to bold processing. Assuming that the character pattern of the alphabet "A" stored in the character pattern memory 24 is as shown in FIG. 4, and focusing on the character pattern data D _o (X ₂ , Y ₆ ), for example,
Character pattern data _Do − ₁ (X ₁ , Y ₆ ) _Do (X ₂ ,
Y ₆ ), D _o + ₁ (X ₃ , Y ₆ ) are as shown in Figure 5.

Character pattern data as shown in FIG. 5 is input to the input terminal of the bold processing circuit 26 shown in FIG.
When D _o − ₁ , D _o , and D _o + ₁ are input, the enable terminal E is active (“1”) at this time, so the logical sum of the four data buses and each adjacent data bus is Be taken. In this case, the 4 bits that make up the character pattern data D _o (X ₂ , Y ₆ )
Among b ₀ , b ₁ , b ₂ , and b ₃ , the data of bit b ₃ is the same as the data of bit b ₀ of the 4 bits that make up the immediately preceding character pattern data D _o − ₁ (X ₁ , Y ₆ ). Since it is latched in the latch circuit 4, the sum of the data is calculated. Thereafter, the latch circuit 4 latches the data of bit _b0 of the character pattern data D _o (X ₂ , Y ₆ ). As a result, the next character pattern data D _o + ₁
During the bold processing of (X ₁ , Y ₆ ), the data of bit b ₃ and the data of bit b ₀ of the character pattern data D _o latched in the latch circuit 4 are logically summed. Note that a reset signal is input to the reset terminal R of the latch circuit 4 every three bytes to clear the data latched up to that point.

In this way, the character pattern data shown in Figure 5
The character pattern data D' _o - ₁ , _{D' o} , _and D' _o + ₁ obtained as a result of bold processing D0-1, _D0 , and D0 ₊₁ are shown in FIG.

As a result of performing similar bold processing on all character pattern data of the alphabet "A", a character pattern as shown in FIG. 7 is obtained. Looking at this character pattern, it can be seen that the character pattern shown in FIG. 4 has been subjected to bold processing. When printing according to the attribute data shown in FIG. 3a, only the alphanumeric character "A" is bolded as shown in FIG. 3c.

In the above embodiment, the data bus has a 4-bit configuration, and the horizontal shift width due to bold processing is 1 bit, but these may be arbitrary.

(Effects of the Invention) As explained above, in the present invention, character pattern data of a character to be printed or displayed is read out in units of a predetermined plurality of bits from a character pattern memory that stores character pattern data of a plurality of characters. The data of the most significant bit or the least significant bit of the character pattern data unit is held until the next readout, and when the bold processing finger is touched, the logical sum of adjacent bits of the data bus of the character pattern data is calculated. With this configuration, bold printing and bold display of any character size is possible with a simple circuit configuration and short processing time without increasing memory capacity.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of a character generating device according to the present invention, FIG. 2 is an embodiment of a bold processing circuit, FIG. 3 is a diagram showing the contents of a character signal and a printing form, and FIG. An example of a character pattern before bold processing, FIG. 5 is an example of character pattern data before bold processing, FIG. 6 is an example of character pattern data after bold processing, FIG. 7 is an example of a character pattern after bold processing, FIG. 8 is a diagram illustrating conventional bold processing. 1...Host device, 2...Character generator, 21
...Interface circuit, 22...Microprocessor, 23...Text buffer, 24...
Character pattern memory, 25... Direct memory access controller, 26... Bold processing circuit, 3... Printer, 4... Latch circuit.

Claims (1)

[Claims] 1. A character pattern memory that stores character pattern data, a readout control circuit that reads out the character pattern data of the character to be printed or displayed in units of a predetermined plurality of bits, and a part of the readout character pattern data consisting of the plurality of bits. and a bold processing circuit which, when a bold processing command is issued, takes the logical sum of the bits held during the previous reading and the adjacent bits of the data bus of the character pattern data currently being read. Character generator.