JPH0570178B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a duplex program system having duplex processors and a backboard on which these duplex processors are mounted.
More specifically, the present invention relates to a duplex processor system in which it is possible to easily determine which side of duplex processors should be the main system.

(Prior Art) FIG. 3 is a conceptual diagram showing the configuration of a conventional dual processor system. In the figure, PC1,
PC2 is a duplicated processor, and BB is a duplicated processor. PC1 and PC2 are, for example,
This is a backboard that is mounted via a connector. This system is configured such that the processor that becomes operational first becomes the main system and executes control, while the other processor becomes the slave system and enters a standby state.

That is, when the processors PC1 and PC2 become operational, they send ready signals RDY1 and RDY2.
is active, and at that time, if the control permission signal (IOCE1, IOCE2) transmitted from the other side via the lead wire on the bug board BB is inactive, the control permission signal (IOCE1, IOCE2) transmitted from the other side via the lead wire on the bug board BB is inactive, the control permission signal is sent via the gate (AG1, AG2) and driver (DR1, DR2). Then, the control permission signal for the main system itself is made active.

As a result, if you activate the ready signal first, you can activate the control permission signal, and if you activate the ready signal later,
Since the control permission signal from the other party is already active, it cannot make its own control permission signal active and becomes a slave system.

(Problems to be Solved by the Invention) In the conventional duplex processor system configured as described above, if there is a large delay in the path of the control permission signal being transmitted via the lead wire on the bug board BB, ( (due to gate, driver propagation delays, bug board capacitance),
When two processors activate their ready signals at the same time (within a time sufficiently shorter than the propagation time from activating their own control permission signal to closing the driver that outputs the other party's control permission signal), the two processors A problem arises in that the control permission signal becomes oscillated and its level is not fixed.

Although such an oscillation state will naturally subside after a certain amount of time, it will take some time for one of the processors to return to stable main system operation.

The present invention was made in view of these problems, and its purpose is to control duplexing to determine which side of the duplexed processors should be the main system when two processors compete with each other. However, the objective is to realize a redundant processor system that makes decisions in a short time and operates stably.

(Means for Solving the Problems) The present invention, which solves the above-mentioned problems, transmits a control permission signal to itself according to its own ready signal (RDY) and a control permission signal from the other party. Duplicated first and second processors are equipped with drivers (DRV) that output IOCE1 and IOCE2), and these duplicated first and second processors are implemented, with one being the master and the other being the slave. A duplex processor system comprising a bag board on which lead wires are arranged for mutually transmitting a control permission signal for making a system, and the duplex first and second processors each have their outputs one to one. Two NAND gates (NG
1, NG2), and a NOR gate (NOR) which inputs the signal from the flip-flop and the signal (LOC1, LOC2) indicating the mounting position of the processor from the backboard.

(Function) When ready signals are output from two processors at the same time, the control permission signals IOCE1 and IOCE2 become active once, but the NOR gate NG
Since signals indicating the positions of processors at different levels are applied to one input terminal of NOR gates 1 and NG2, only one of the NOR gates becomes active. As a result, the control permission signal from the driver whose output from the NOR gate has become active becomes active.

(Example) Examples of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, PC1 and PC2 are redundant first and second processors, each of which sends a control permission signal to itself (IOCE1, IOCE2) according to its own ready signal RDY and a control permission signal from the other side. ) is equipped with a driver (DRV) that outputs.

BB is equipped with these redundant first and second processors PC1 and PC2, and receives control permission signals IOCE1 and IOCE to make one the main system and the other one the slave system.
Lead wire L1 for mutually transmitting IOCE2,
This is a bag board on which L2 is arranged.

Duplicated first and second processors PC1,
In PC2, AG1 and AG2 are AND gates and send their own ready signals (RDY1,
RDY2) and inverter IV1,
Control permission signals (IOCE2, IOCE1) from the other side are input to each other via IV2. NG1,
NG2 is a NAND gate constituting a flip-flop FF. NAND gate NG1 inputs its own ready signal and the output signal of NAND gate NG2, and NAND gate NG2 inputs a control permission signal from the other side via inverter IV1.
NOR is a NOR gate that inputs the signal from the flip-flop FF and the signal (LOC1, LOC2) indicating the mounting position of the processor from the backboard BB. Here, the signal IOC1 indicating the mounting position of the first processor PC1 is a low level signal from the line L3 whose one end is grounded on the bag board BB, and the signal LOC2 indicating the mounting position of the second processor PC2 is On the bugboard, this is a high level signal with one end connected to +5V.

OR is an OR gate, which inputs the signal from AND gate AG and the signal from NOR gate NOR,
The output is given to the driver DR. The output signal of this driver-DR becomes a control permission signal for determining whether or not it is the main system, and is applied to its own processor, and is also sent to the other processor side via the lead wire on the bug board BB. transmitted.

The operation of the device configured as described above will be explained below, dividing it into a normal state and a competitive operation.

(Normal operation; when ready signal RDY1 becomes active before RDY2) Ready signal RDY1 and ready signal RDY2 are
Both are inactive at the beginning, and each processor
On the PC1 and PC2 sides, AND gate AG1,
The outputs of AG2 and NOR gates NOR1 and NOR2 are all inactive. For this reason, at first,
Output IOCE1 of each driver DR1, DR2,
Both IOCE2 are inactive.

Here, when the ready signal RDY1 becomes active before RDY2, since the control permission signal IOCE2 from the second processor PC2 side is inactive, the inverter IV2 on the processor PC1 side
The output becomes high level (active), and the control permission signal IOCE1 from the driver DR1 becomes active. This allows the first processor
PC1 will act as the main system.

After that, the ready signal RDY2 on the second processor PC2 side becomes active, but the inverter on the second processor PC2 side is
Since the output of IV2 is at a low level, the output of AND gate AG2 is not active, and therefore processor PC2 is in a standby state as a slave system.

Note that in this state, the NOR gate NOR2 is closed, and one input of the OR gate OR2 is not activated.

(Normal operation: When ready signal RDY2 becomes active before RDY1) In this case, the same operation as described above is performed.

At this time, in the first processor PC1, when the ready signal RDY1 becomes active later than RDY2, the two inputs of the OR gate OR1 are both at low level due to the control permission signal IOCE2, which has become active earlier, and the driver DR
1 does not activate its control permission signal IOCE1.

(Conflict operation; when ready signals RDY1 and RDY2 become active almost simultaneously) In this case, when both control permission signals IOCE1 and IOCE2 go from being inactive to ready signals RDY1 and RDY2 becoming active almost simultaneously,
The two control permission signals ICOE1 and IOCE2 become active once. At this time, the first processor PC
The NOR gate on the 1 side also receives the mounting position signal LOC.
1 is set to active, so it will be active once.

Next, since the two control permission signals IOCE1 and IOCE2 both became active, each processor
On the PC1 and PC2 sides, the output of inverter IV2 becomes low level, and each AND gate AG1,
The output of AG2 now becomes inactive.

At this time, if the output of the NAND gate NG1 of the flip-flop FF1 becomes low level and the input of the NAND gate 13 is determined, it would be better than if the control permission signal IOCE2 becomes active and the output of the inverter IV becomes high level. If it's fast,
The output of the NAND gate NG1 is determined to be low level, and the output of the NAND gate NOR1 is determined to be active. This causes the driver DR1 to activate the control permission signal IOCE1. On the second processor PC2 side, the two inputs of the OR gate OR2 are both inactive, so the control permission signal IOCE2 is made inactive and maintained in that state.

FIG. 3 shows operating waveforms when the ready signal RDY2 becomes active slightly faster than the ready signal RDY1. In Figure 3, a is a ready signal.
RDY1 and e indicate changes in the ready signal RDY2.
In this case, the output of NAND gate NG1 that constitutes flip-flop FF1 (this change is shown in b)
On the side that is to be made active, the output of inverter IV1 becomes high level as shown in c before it is confirmed, and the output of NAND gate NG1 is made high level, and the output of each driver DR1 and DR2 is made inactive. do. As a result, AND gates AG1 and AG2 become active again.
The control permission signals IOCE1 and IOCE2 are activated, but this time flip-flop FF1 is determined to activate the control permission signal IOCE1, so the control permission signal is activated as shown in d and f.
IOCE1 is kept active and control permission signal IOCE2 is kept inactive.

Due to this operation, ready signals RDY1,
If RDY2 becomes active at almost the same time,
In this case, due to the difference in the level of the signal LOC indicating the mounting position of the processor,
The PC1 side operates as the main system.

Note that in the above explanation, the first processor PC
Although the case where the second processor PC2 is the main system has been described, the case can be easily changed by changing the level of the signal LOC indicating the mounting position.

(Effects of the Invention) As described above in detail, according to the present invention, a dual processor system having the following features can be realized with a simple configuration.

(a) It is possible to decide in a short time which processor will operate as the main system.

(b) After each processor outputs a ready signal, it judges the level of an input control permission signal, and the waiting time can be shortened.

(c) Duplicated processors operate asymmetrically depending on their mounting position, but the operation settings can be made from the bug board, so it is possible to use two processors with the same configuration. can.

[Brief explanation of the drawing]

FIG. 1 is a configuration block diagram showing one embodiment of the present invention, FIG. 2 is an operation waveform diagram showing an example of operation, and FIG.
The figure is a conceptual diagram of the configuration of a conventional dual processor system. PC1...first processor, PC2...second processor, BB...bug board, FF1, FF2...flip-flop, AG1, AG2...and gate,
DR1, DR2...driver, NOR1, NOR2...
Noah Gate, IV1, IV2...Inverter.

Claims (1)

[Scope of Claims] 1. Duplex device equipped with a driver (DRV) that outputs a control permission signal (IOCE1, IOCE2) to itself according to its own ready signal (RDY) and a control permission signal from the other side. The redundant first and second processors are mounted, and leads are used to mutually transmit control permission signals to make one the main system and the other the slave system. It is a duplex processor system consisting of a backboard on which lines are arranged, and the duplex first and second processors each receive one of their outputs, one receives its own ready signal, and the other receives the other party's ready signal. Two NAND gates (NG1,
NG2), and a NOR gate (NOR) that inputs the signal from the flip-flop and the signal (LOC1, LOC2) indicating the mounting position of the processor from the backboard, and when the output of the NOR gate is active. 1. A duplex processor system, wherein a control permission signal from said driver to itself is activated at certain times.