JPH0570306B2 - - Google Patents
Info
- Publication number
- JPH0570306B2 JPH0570306B2 JP62256945A JP25694587A JPH0570306B2 JP H0570306 B2 JPH0570306 B2 JP H0570306B2 JP 62256945 A JP62256945 A JP 62256945A JP 25694587 A JP25694587 A JP 25694587A JP H0570306 B2 JPH0570306 B2 JP H0570306B2
- Authority
- JP
- Japan
- Prior art keywords
- sputtering
- temperature
- resistance
- thin film
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/201—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits
- H10D84/204—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors
- H10D84/209—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors of only resistors
Landscapes
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体基板上にクロムシリコンから
なる薄膜抵抗体を有する半導体装置の製造方法に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device having a thin film resistor made of chromium silicon on a semiconductor substrate.
半導体基板上に形成される高精度かつ高信頼性
を有する薄膜抵抗体として、従来からニツケルク
ロムNi−Cr、窒化タンタルTa2Ｎ、クロムシリ
コンCr−Siなどがあり、集積回路等に用いられ
ている。これらの各種抵抗体のうち、最も高抵抗
な薄膜抵抗としてはCr28±５原子％のCr−Siが
用いられている。このCr−Si膜形成法として、
従来は電子ビーム蒸着法、高周波ダイオードスパ
ツタ法、直流ダイオードスパツタ法等が用いられ
てきた。しかしながら、電子ビーム蒸着法では、
Cr−SiのCrとSiの組成比が安定しないという問
題点がある。また、高周波ダイオードスパツタ法
や直流ダイオードスパツタ法では、基板に与える
損傷が大きいスパツタ工程中の基板の温度上昇が
高い、スパツタ速度が遅い等の問題があつた。そ
こで基板への損傷が少なく、かつスパツタ速度の
速い直流マグネトロンスパツタ法を用いること
が、例えば雑誌「シン・ソリツド・フイルムズ
（Thin Solid Films）128巻（1985年）149〜151
ページ等に記載されている。
Conventionally, nickel chromium Ni-Cr, tantalum nitride Ta 2 N, chromium silicon Cr-Si, etc. have been used as thin film resistors with high precision and high reliability formed on semiconductor substrates, and they are used in integrated circuits, etc. There is. Among these various resistors, Cr--Si containing Cr28±5 atomic % is used as the thin film resistor with the highest resistance. As this Cr-Si film formation method,
Conventionally, electron beam evaporation, high frequency diode sputtering, direct current diode sputtering, etc. have been used. However, in the electron beam evaporation method,
There is a problem that the composition ratio of Cr and Si in Cr-Si is not stable. In addition, the high frequency diode sputtering method and the DC diode sputtering method have problems such as a high temperature rise of the substrate during the sputtering step which causes great damage to the substrate, and a slow sputtering speed. Therefore, it is recommended to use the DC magnetron sputtering method, which causes less damage to the substrate and has a faster sputtering speed, as described in the magazine "Thin Solid Films" Vol. 128 (1985) 149-151.
It is written on the page etc.
直流マグネトロンスパツタ法を用いてCr−Si
薄膜抵抗体を作成する場合の最適のスパツタ条件
はまだ明らかでない。
Cr-Si using DC magnetron sputtering method
The optimal sputtering conditions for making thin film resistors are not yet clear.
本発明の目的は、半導体基板上に直流マグネト
ロンスパツタ法を用いて形成された抵抗温度係数
の充分に小さいCr−Si薄膜抵抗をもつ半導体装
置の製造方法を提供することにある。 An object of the present invention is to provide a method for manufacturing a semiconductor device having a Cr--Si thin film resistor with a sufficiently small temperature coefficient of resistance formed on a semiconductor substrate using a DC magnetron sputtering method.
上記の目的を達成するために、本発明の方法
は、275〜375℃に加熱した半導体基板上にアルゴ
ン圧力10mTorr以上での直流マグネトロンスパ
ツタ法によりCr−Si薄膜を成膜し、425〜475℃
の温度でアニールしてCr−Si薄膜抵抗体を形成
するものとする。
In order to achieve the above object, the method of the present invention involves forming a Cr-Si thin film on a semiconductor substrate heated to 275 to 375°C by direct current magnetron sputtering at an argon pressure of 10 mTorr or more. ℃
A Cr--Si thin film resistor is formed by annealing at a temperature of .
上述の条件で作成したCr−Si薄膜の抵抗温度
係数は±100ppm／℃以内に入る。
The resistance temperature coefficient of the Cr-Si thin film produced under the above conditions is within ±100 ppm/°C.
直流マグネトロンスパツタ法で28±５原子％の
Cr−Si膜を成膜するためのターゲツトとしては、
Cr：Siのモル比が28：72のものを用いることが
適当である。このようなターゲートを使用した直
流マグネトロンスパツタ装置に1μｍの厚さの
SiO2膜を被覆したシリコン基板を装着し、約200
Åの厚さにCr−Si膜を形成した。スパツタ条件
として、Ar圧力を2mTorr，8mTorrおよび
13mTorrと変え、それぞれに対する直流電力を
1.1kw，1.2kwおよび1.2kw、スパツタ時間を６
秒、６秒および７秒とした。基板はスパツタ前に
200℃，250℃，300℃，350℃，400℃に加熱した
ものおよび室温のままのものを用いた。
28±5 atomic% by DC magnetron sputtering method.
The target for forming the Cr-Si film is
It is appropriate to use one with a Cr:Si molar ratio of 28:72. A DC magnetron sputtering device using such a target has a thickness of 1 μm.
A silicon substrate coated with a SiO 2 film is attached, and approximately 200
A Cr-Si film was formed to a thickness of Å. The sputtering conditions were Ar pressure of 2mTorr, 8mTorr and
13mTorr and the DC power for each
1.1kw, 1.2kw and 1.2kw, sputtering time 6
seconds, 6 seconds and 7 seconds. Before sputtering the board
Those heated to 200°C, 250°C, 300°C, 350°C, and 400°C and those left at room temperature were used.
Cr−Si膜を成膜後エツチングによりパターニ
ングし、さらにAl膜を1.6μｍの厚さにスパツタ
し、エツチングにより電極配線をパターニングし
た。次いで、このようなCr−Si膜、Al電極配線
をSiO2膜上に形成した基板を窒素雰囲気中で
400，425，450，475，500℃の温度でそれぞれ20
分間アニールした。最後にパツシベーシヨン膜と
して通常よく使用されているプラズマ窒化膜を堆
積し、エツチングによりパターニングして半導体
装置を製造した。 After the Cr--Si film was formed, it was patterned by etching, and an Al film was sputtered to a thickness of 1.6 μm, and electrode wiring was patterned by etching. Next, the substrate with such a Cr-Si film and Al electrode wiring formed on the SiO 2 film was placed in a nitrogen atmosphere.
20 respectively at temperatures of 400, 425, 450, 475, 500℃
Annealed for minutes. Finally, a plasma nitride film, which is commonly used as a passivation film, was deposited and patterned by etching to manufacture a semiconductor device.
以上の工程で製造された半導体装置のCr−Si
抵抗体のシート抵抗値は1.7〜2.2kΩ／□の範囲で
あり、27℃と125℃の温度での安定した抵抗値を
測定することにより抵抗温度係数を求めた。 Cr-Si of semiconductor devices manufactured by the above process
The sheet resistance value of the resistor was in the range of 1.7 to 2.2 kΩ/□, and the temperature coefficient of resistance was determined by measuring stable resistance values at temperatures of 27°C and 125°C.
第１図、第２図はアニール条件をN2雰囲気中、
475℃，20分間の場合のAr圧力をパラメータとし
た抵抗温度係数とスパツタ前基板温度との関係、
スパツタ前基板温度をパラメータとした抵抗温度
係数とAr圧力との関係をそれぞれ示す。第１、
第２図より、Ar圧力が高い程抵抗温度係数が小
さくなり、スパツタ前の基板加熱温度が300℃に
おいて最も低く、この結果からAr圧力が
13mTorrの時には250〜400℃の範囲で、Ar圧力
8mTorrの時には300℃のときに抵抗温度係数は
100ppm／℃以内に入つていることがわかる。 Figures 1 and 2 show annealing conditions in N2 atmosphere.
Relationship between temperature coefficient of resistance and substrate temperature before sputtering using Ar pressure as a parameter at 475℃ for 20 minutes.
The relationship between the resistance temperature coefficient and Ar pressure with the substrate temperature before sputtering as a parameter is shown. First,
From Figure 2, the higher the Ar pressure, the smaller the temperature coefficient of resistance becomes, and the lowest temperature when the substrate heating temperature before sputtering is 300℃.From this result, the Ar pressure increases.
Ar pressure in the range of 250 to 400℃ at 13mTorr
At 8mTorr and 300℃, the temperature coefficient of resistance is
It can be seen that it is within 100ppm/℃.
第３図は、スパツタ時のAr圧力を2mTorr、ア
ニール温度を400〜500℃、アニール時間を20分と
した場合における室温、200℃、300℃のスパツタ
前基板温度をパラメータとした抵抗温度係数とア
ニール温度との関係を示す。第３図から、アニー
ル温度が低い方が抵抗温度係数が小さいが400℃
でアニールした半導体装置ではAl配線とCr−Si
抵抗体との間の接触抵抗が高くなるため、半導体
装置の特性上問題がでることがわかつた。 Figure 3 shows the temperature coefficient of resistance and the temperature coefficient of resistance using room temperature, pre-sputtering substrate temperatures of 200°C and 300°C as parameters when the Ar pressure during sputtering is 2 mTorr, the annealing temperature is 400 to 500°C, and the annealing time is 20 minutes. The relationship with annealing temperature is shown. From Figure 3, the temperature coefficient of resistance is smaller when the annealing temperature is lower than 400°C.
In semiconductor devices annealed with
It has been found that the contact resistance between the resistor and the resistor becomes high, which causes problems in terms of the characteristics of the semiconductor device.
これらの結果より、直流マグネトロンスパツタ
前の半導体基板加熱温度を275〜375℃、スパツタ
時のAr圧力を10mTorr以上、成膜後のアニール
温度を425〜475℃とすることにより、半導体装置
の他の特性を満たすと共にCr−Si薄膜抵抗体の
抵抗温度係数を100ppm以内とすることができる
ことがわかつた。 From these results, by setting the semiconductor substrate heating temperature before DC magnetron sputtering to 275 to 375°C, the Ar pressure during sputtering to 10 mTorr or more, and the annealing temperature after film formation to 425 to 475°C, semiconductor devices and other It was found that the resistance temperature coefficient of the Cr-Si thin film resistor can be made within 100 ppm while satisfying the following characteristics.
本発明によれば、Cr−Si薄膜抵抗を基板を損
傷することが少なく、スパツタ速度の速い直流マ
グネトロンスパツタにより形成する場合に、基板
温度を275〜375℃、スパツタ時のAr雰囲気圧力
を10mTorr以上、スパツタ後のアニール条件を
425〜475℃とすることによりシート抵抗値が1.7
〜2.2kΩ／□で抵抗温度係数が±100ppm／℃以
内の範囲にある薄膜抵抗体を有する半導体装置を
得ることができる。
According to the present invention, when forming a Cr-Si thin film resistor using DC magnetron sputtering, which causes less damage to the substrate and has a high sputtering speed, the substrate temperature is 275 to 375°C, and the Ar atmosphere pressure during sputtering is 10 mTorr. Above are the annealing conditions after sputtering.
By setting the temperature to 425 to 475℃, the sheet resistance value is 1.7
A semiconductor device having a thin film resistor having a resistance temperature coefficient of ˜2.2 kΩ/□ and within ±100 ppm/° C. can be obtained.
第１図はスパツタ時Ar圧力をパラメータとし
てCr−Si薄膜抵抗温度係数とスパツタ前基板温
度の関係線図、第２図はスパツタ前基板温度をパ
ラメータとしたCr−Si薄膜抵抗温度係数とAr圧
力の関係線図、第３図はスパツタ前基板温度をパ
ラメータとしたCr−Si薄膜抵抗温度係数とアニ
ール温度の関係線図である。
Figure 1 is a relationship diagram between Cr-Si thin film resistance temperature coefficient and substrate temperature before sputtering using Ar pressure during sputtering as a parameter. Figure 2 is a relationship diagram between Cr-Si thin film resistance temperature coefficient and Ar pressure using sputtering front substrate temperature as a parameter. FIG. 3 is a diagram showing the relationship between the temperature coefficient of resistance of the Cr--Si thin film and the annealing temperature with the temperature of the substrate before sputtering as a parameter.
Claims (1)
ン圧10mTorr以上での直流マグネトロンスパツ
タ法によりクロム・シリコン薄膜を成膜し、425
〜475℃の温度でアニールしてクロム・シリコン
薄膜抵抗体を形成することを特徴とする半導体装
置の製造方法。1 A chromium-silicon thin film is deposited on a semiconductor substrate heated to 275 to 375°C by direct current magnetron sputtering at an argon pressure of 10 mTorr or more, and
A method for manufacturing a semiconductor device, comprising forming a chromium-silicon thin film resistor by annealing at a temperature of ~475°C.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62256945A JPH0199250A (en) | 1987-10-12 | 1987-10-12 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62256945A JPH0199250A (en) | 1987-10-12 | 1987-10-12 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0199250A JPH0199250A (en) | 1989-04-18 |
| JPH0570306B2 true JPH0570306B2 (en) | 1993-10-04 |
Family
ID=17299541
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62256945A Granted JPH0199250A (en) | 1987-10-12 | 1987-10-12 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0199250A (en) |
-
1987
- 1987-10-12 JP JP62256945A patent/JPH0199250A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0199250A (en) | 1989-04-18 |
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