JPH0570328B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an operational amplifier circuit configured on an integrated circuit, and in particular to an operational amplifier that has a large and symmetrical load driving capacity in both positive and negative directions and that can output two balanced outputs. Regarding.

[Conventional technology and its problems]

Conventionally, the circuit shown in FIG. 3 has been known as an operational amplifier that provides a balanced output. This circuit was created in 1983
ISSCC'85DIGEST OF TECH-
This is the circuit described on page 314 of NICAL PAPERS). This circuit consists of an N-channel transistor with a constant voltage 113 applied to the gate electrode.
MN109 (hereinafter written as MN109)
And MN101 and MN
102 and balanced inputs 103 and 1
A pair of differential amplification transistors having gates 04 and 04 are connected to each other. The drain electrode, which is the output of this differential amplifier, is a P-channel MOS transistor.
MP101 and MP102 (hereinafter referred to as MP101,
The transistors are connected to the source electrodes of a pair of folded cascode transistors (denoted as MP102), respectively. The drain electrode of this folded cascode transistor pair is connected to the N-channel transistor MN103.
It is connected to a constant current source constituted by MN 106, and a high gain is obtained by using this constant current source as a load. In FIG. 3, N-channel transistors MN107 and MN108 are added to determine the center of operation of balanced outputs 107 and 108. Note that terminals 110-1
13 are each kept at a constant voltage.

This circuit basically has one amplification stage, and gains are achieved by increasing the load resistance. Therefore, when driving a capacitive load, its ability to drive a large capacitance is limited by the mutual conductance of the input differential transistor pair and the load capacitance, so it lacks the ability to drive a large capacitance. Also, the speed at which the output voltage decreases, that is, the slew rate, is limited by the current of the constant current source that serves as the bias current of this operational amplifier, so in order to increase the slew rate, it is necessary to flow a large amount of current. Yes, the current consumption also increases.
Since the number of transistors connected in series between the first voltage source 101 and the second voltage source 102 is large, the voltage range that can be output is also small. These drawbacks are fatal to operational amplifiers used in large-scale integrated circuits.

In order to increase the gain and increase the output drive capability, an operational amplifier with two gain stages is preferable. Although Figure 4 is not a balanced operational amplifier, it was published in 1984 in the IEEE Journal of Solid-State Circuits.
This is the circuit published in Vol. SC-19, page 920 of Vol. In FIG. 4, a constant current source transistor is formed by applying a constant voltage 211 to the gate electrode.
A differential transistor pair MP201 and MP202 whose source electrodes are commonly connected to the constant current source is connected to MP209. Input terminals 203 and 204 are connected to MP201 and MP202, gate electrodes of the drain electrodes of the differential transistor pair are commonly connected to a terminal 205 for inputting a reference voltage, and the drain electrodes are connected to the first power supply line 2.
MP205 and MP20 with 01 as reference voltage
MN used in a folded cascode stage formed by connecting a current mirror formed by 6.
203 and the source electrodes of MN204. The current mirrors mentioned here are each
It is connected to a constant current source with reference to the second voltage source 202 produced by MN 207 and MN 208 .

Output 206 of the folded cascode stage
uses MP208 as the driving transistor, and MN2
The signal is further amplified by an inverting amplifier using 06 as a constant current load, and is output from an output terminal 207. Fourth
Cc in the figure is the phase compensation capacitor. This circuit has the advantage that the input voltage range can be widened and the output voltage range can output up to a voltage approximately equal to the negative power supply 202 for the lowest voltage. Note that a predetermined voltage is applied to the terminal 208.

However, in the circuit of FIG. 4, when a large capacitive load is connected and a signal with a large amplitude is output, especially when the voltage decreases, the slew rate when the voltage decreases is limited by the current flowing through the MN 206. Therefore, in order to speed up this process, it is necessary to increase the current flowing through the MN 206. This means that the current consumed by the circuit increases. Furthermore, when the current is increased, the upper limit of the output voltage is determined by this current and the on-resistance of the MP208, making it impossible to increase the power supply voltage to its full potential. These drawbacks are unacceptable for operational amplifiers implemented on large scale integrated circuits.

[Means for Solving the Problems] In order to solve the above problems, the present invention provides an operational amplifier circuit in which a common source is connected to a first constant current source whose one end is connected to the first voltage source. a pair of differential transistors connected to each other, each having a first polarity and whose gate electrode serves as an input terminal, and a first pair of transistors each having a first polarity and whose drain electrode is referenced to the first voltage source; a second current mirror having a second polarity connected to a first current mirror having a gate electrode commonly connected to a first reference voltage source and a source electrode respectively connected to a drain electrode of each of said differential transistor pair; a first folded cascode stage constituted by two transistor pairs; a drain electrode connected to a source electrode of the second transistor pair; a source electrode connected to a second voltage source; a current source pair consisting of a pair of transistors having polarities; and the first current mirror consisting of a third pair of transistors whose drain electrodes have a first polarity and connected with respect to the first voltage source. a second current mirror having a symmetric relationship, a gain electrode being commonly connected to the first reference voltage source;
a second folded cascode stage constituted by a fourth pair of transistors having a second polarity, each having a source electrode connected to a drain electrode of each of said differential transistor pairs; third and fourth transistors constituted by a pair of transistors having a second polarity as the second voltage source and whose input transistors controlling mutually inverted currents are each output of the folded cascode stage; It has two pairs of transistors each having a first polarity connected to a current mirror and whose gate electrodes are respectively connected to the folded cascode stage, and the current flowing through the third and fourth current mirrors is supplied from the outside. and means for controlling the current mirror, and connecting points between the two pairs of transistors having the first polarity and the third and fourth current mirrors are positive and negative output terminals, respectively. .

[Effect]

By using the circuit of the present invention, there are two sets of folded cascode stages connected to the differential input stage, and one output is sent to one of the final stages of the inverting amplifier for two balanced outputs. By driving the drive transistor of the inverting amplifier and using the other output as a current mirror to drive the other transistor of the inverting amplifier, a push-pull type output stage is constructed, which dramatically improves the drive ability for capacitive loads. The output voltage range can be expanded to the full power supply voltage.

〔Example〕

Hereinafter, the present invention will be explained in detail by giving an example realized on a MOS type integrated circuit. FIG. 1 is a circuit diagram showing the configuration of this embodiment. The embodiment shown in FIG. 1 includes a P-channel MOS transistor.
MP12, MP13 and N-channel MOS transistors MN13, MN14, MN15, MN1
A simple reference bias voltage generating circuit configured by 6 is also included in the description.

First, an MP11 whose source electrode is connected to the first voltage source 1 and whose gate electrode is constantly biased
MP1 and MP2, both of whose sources are connected to a constant current source configured by , constitute a differential transistor pair. The gate electrodes of MP1 and MP2 form input terminals 3 and 4, respectively. MN1 and MN2 whose gate electrodes are biased to another constant voltage and whose source electrodes are connected to the drain electrodes of the differential pairs MP1 and MP2, respectively;
The input signal is amplified by a first folded cascode stage composed of a current mirror composed of P-channel MOS transistors MP3 and MP4, in which the drain electrodes of MN1 and MN2 are connected to the current input and output terminals, respectively. , an amplified output is obtained at node 5.

This circuit has another folded cascode stage. That is, the N-channel transistor pair of the first folded cascode stage, the N-channel MOS transistor pair MN3 and MN4 whose gate electrode and source electrode are connected in common, and the drain electrodes of MN3 and MN4, respectively, are current inputs. a second folded cascode stage constituted by a current mirror consisting of P-channel MOS transistors MP5 and MP6, connected to the output and whose direction of reversed current is inversely related to that of the first current mirror; be. This second folded cascode stage is symmetrical with respect to the first folded cascode stage, and the outputs 6 and 5 of this stage are of opposite phase to each other.

These two folded cascode stages are
It operates by being current biased by N-channel MOS transistors MN7 and MN8 forming a pair of constant current sources whose gate electrodes are biased to a common constant voltage. The output 5 of the first folded cascode stage is a P-channel MOS transistor.
Converted to current by MP7, MN5 and MN
6 is connected to the output terminal 7 through a third current mirror constituted by 6. The output 6 of the second folded cascode stage is connected to the output terminal 8 through a P-channel MOS transistor MP10, thereby forming a push-pull output circuit.
Furthermore, MP8, MP9, which is symmetrical to this output circuit,
It has another output circuit composed of MN6 and MN7. Furthermore, an N-channel transistor MN11 is connected in parallel with current mirror transistors MN5 and MN6 for stabilizing the in-phase components of the output voltages of these two output circuits, respectively, and for externally controlling the current mirror outputs of MN7 and MN8. and MN12. In FIG. 1, C _c1 and C _c2 are phase compensation capacitors.

To explain the operation of this circuit again, input terminal 3,
The signal input from 4 is amplified and output to output nodes 5 and 6 of the folded cascode stage. One of the balanced outputs of the cascode stage drives MP10, and the other output drives MP7,
It is inverted by MN5 and drives MN8. The output of MN8 forms a push-pull configuration together with MP10, is further amplified, and is output to output 8. The other balanced output is opposite to the output of the cascode stage described above and drives MP9, and the other is inverted by MP8 and MN6 and drives MN7. Then, the output of MN7 becomes a push-pull configuration with MP9, and is further amplified to output 7.
is output to.

In a balanced operational amplifier, the output operating point inevitably differs from the design due to variations in the elements.
The difference that occurs between two output voltages when the same input voltage is input can be corrected as an input offset voltage, but if the operating point of the output is out of phase, it cannot be changed at the input terminals 3 and 4. MN11
And MN12 is a current source for compensating for this in-phase error, and by increasing this gate voltage, the output voltage can be increased.

Two examples of feedback circuits used for this purpose are shown in FIGS. 2a and 2b. The circuit of FIG. 2a consists of resistors RR1 and R2 with equal resistance values for two output terminals 7 and 8, and a capacitor C with equal capacitance value.
1 and C2 in parallel, find the center of the output operating point by taking the midpoint, and differentially amplify the difference between this voltage and the reference operating center voltage applied from node 12, and apply it from node 9. It was designed to trigger a return. Further, 1 and 2 are first and second voltage sources, respectively, and a predetermined voltage is also applied to the node 10.

The circuit of FIG. 2b determines the center of the alternating current operating point of outputs 7 and 8 by means of capacitors C3 and C4 having equal capacitance values. Since this alone is indeterminate with respect to DC voltage, a capacitor C with equal capacity
5 and C6 and switches SW1 to SW4 define the DC voltage. This part of the operation is performed in two time slots that do not overlap with each other.
In the first time slot, switch SW1 is connected to output terminal 7, switch SW3 is connected to output terminal 8, and switches SW2 and SW4 are connected to node 11 of the reference voltage generating circuit of FIG. Next, in the second time slot, switch SW1 and
SW3 is connected to the terminal 12 to which the reference operating center voltage supplied from the outside is applied, and the switch
SW2 and SW4 are connected to node 9 in FIG.

Through these two operations, the sum of the voltage differences between the two power voltages of the operational amplifier and the reference operating voltage supplied from the outside is subtracted from the voltage of the reference voltage generation circuit, and this subtracted voltage and C5 and The sum of the charges of the capacitances of C6 is output to node 9.
The voltage at node 9 is determined so that this amount of charge becomes 0. This amount of charge becomes 0 because the sum of the voltage differences between the two output voltages of the operational amplifier and the reference operating voltage supplied from the outside is approximately 0, that is, the average value of the voltages at nodes 7 and 8 is This is when the voltage is equal to the voltage at terminal 12.

In addition, in the present invention, the N-channel MOS transistor and the P-channel MOS transistor in the embodiment shown in FIG.
There is no problem even if the circuit is made by replacing the transistors.

〔Effect of the invention〕

In this circuit, the maximum value of the voltage at node 6 rises to the voltage of the first power supply, in this case MP8 and MP
9 is turned off and the voltage at output 8 is allowed to drop to a voltage equal to the voltage of the second power supply. On the other hand, at this time, since no current flows through MN6, MN7 is also turned off, and the voltage at output 7 rises to a voltage equal to the voltage of the first voltage source. Conversely, the voltage at node 5 also rises to the voltage of the first power supply, so in this case MP7
Since MP9 is turned off and no current flows to MN5, no current flows to MN8 either. That is, in this case, the voltage at the output 8 rises to the voltage of the first voltage source, and the voltage at the output 7 falls to a voltage equal to the voltage of the second voltage source. Furthermore, since this circuit is a two-stage amplifier, the output drive capability is the product of the gain of the first folded cascode amplifier stage and the sum of the mutual conductance of the push-pull output stage. Overwhelmingly improved. Furthermore, since the output stage has a push-pull configuration, the slew rate is not limited by the output stage as in the prior art, allowing high speed and low power consumption.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing the configuration of an embodiment of the present invention, Fig. 2 a and b are circuit diagrams of a circuit for setting the output operating point used in the circuit of Fig. 1, and Fig. 3 is a circuit diagram showing the configuration of an embodiment of the invention. A circuit diagram showing a known balanced CMOS operational amplifier circuit, and FIG. 4 is a circuit diagram showing a conventional example of a single-ended type. MN1 to 16...N channel MOS transistors, MP1 to 13...P channel MOS transistors.

Claims (1)

[Claims] 1. A differential transistor pair having a first polarity, each having a common source connected to a first constant current source whose one end is connected to a first voltage source, and each gate electrode serving as an input terminal. and a drain electrode connected to a first current mirror formed by a first transistor pair having a first polarity and referenced to the first voltage source, and a gate electrode common to the first reference voltage source. a first folded cascode stage constituted by a second pair of transistors of a second polarity connected to each other and having a source electrode connected to a drain electrode of each of said differential transistor pairs; a pair of current sources connected to the source electrode of the second pair of transistors, the source electrode of which is connected to a second voltage source, the pair of transistors having a second polarity; and the drain electrode of which has a first polarity; a third pair of transistors having a reference voltage source connected to a second current mirror having a symmetrical relationship with the first current mirror, the gate electrode being connected to the first reference voltage source; commonly connected to a voltage source,
a second folded cascode stage constituted by a fourth pair of transistors having a second polarity, each having a source electrode connected to a drain electrode of each of said differential transistor pairs; third and fourth transistors constituted by a pair of transistors having a second polarity as the second voltage source and whose input transistors controlling mutually inverted currents are each output of the folded cascode stage; It has two pairs of transistors each having a first polarity connected to a current mirror and whose gate electrodes are respectively connected to the folded cascode stage, and the current flowing through the third and fourth current mirrors is supplied from the outside. and means for controlling the current mirror, and connecting points between the two pairs of transistors having the first polarity and the third and fourth current mirrors are positive and negative output terminals, respectively. Amplification circuit.