JPH0571137B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit device formed by a polycell (building block) layout method using multilayer metal wiring, and particularly relates to a semiconductor integrated circuit device formed by a polycell (building block) layout method using multilayer metal wiring. .

[Technical Background of the Invention] Conventionally, this type of semiconductor integrated circuit device has been proposed in Japanese Patent Application No. 59-44602 filed by the present applicant entitled “Semiconductor Integrated Circuit Device,” which uses two layers of metal wiring to achieve high operating speed. A number of proposals have been made to achieve higher speed and higher integration. FIG. 4 shows a polycell layout type semiconductor integrated circuit device shown in FIG. 4 in the above-mentioned Japanese Patent Application No. 59-44602. In addition, in order to make the drawing easier to read, this FIG. 4 is a schematic representation of FIG. 4 of the above-mentioned application, and the same parts are given the same reference numerals. In this semiconductor integrated circuit device, the wiring layers include a first metal wiring layer, a second metal wiring layer,
Three different types of wiring layers are used, each consisting of a polysilicon layer used as a gate electrode, and a polysilicon layer used as a gate electrode. An example of a pattern layout of a unit cell (inverter) in a semiconductor integrated circuit device using such a polycell layout method is shown in FIGS.

In the above configuration, the input signal to the unit cell is input into the cell through the polysilicon layer serving as the gate electrode, and the output signal from this cell is externally transmitted through the second metal wiring layer. is derived. The first metal wiring layer is connected to the second metal wiring layer through a contact hole.
This first layer metal wiring layer is connected to the polysilicon layer through a contact hole in the same wiring channel region, and connected to the input end of the unit cell in the next cell column, or again through the contact hole. The wiring crosses the cell column via the second metal wiring layer and is wired to the next wiring area. The signal lines formed by the second layer metal wiring layer wired to the predetermined wiring channel region in this way are connected to other polysilicon layers via the first layer metal wiring layer, as in the aforementioned wiring channel region. connected to provide input signals to other cells.

The features of the wiring system as shown in FIGS. 4 and 5 a and b are as listed below.

(1) The output signal line from the unit cell must be in the second metal wiring layer.

(2) The input signal line to the unit cell shall be a polysilicon layer used for the gate electrode.

(3) A first metal wiring layer is used in the horizontal direction of the cell column, and a second metal wiring layer and polysilicon layer are used in the vertical direction.

(4) A second metal wiring layer is used for the wiring that crosses the cell rows.

(5) The polysilicon layer is used only for the wiring that will ultimately be input to the cell, and is not used for any other wiring.

(6) Through wiring (wiring that crosses cell rows) using the second metal wiring layer is an area on the cell where the second metal wiring layer is not used (through wiring prohibited area)
pass through.

Note that when automatic placement and wiring using CAD is used to determine the arrangement of unit cells and wiring routes in the polycell layout method, the center line of each wiring is aligned on a predetermined unit grid. Further, the metal wiring layer remains the same even if the first layer and the second layer are replaced.

[Problems with background technology]

Incidentally, the size of the minimum unit grid in the polycell layout method using automatic placement and wiring is generally determined by the minimum pitch of the wiring. That is, the horizontal direction (X direction) to the cell column is determined by the wiring pitch of the first metal wiring layer, and the vertical direction (Y direction) to the cell column is determined by the wiring pitch of the second metal wiring layer and polysilicon. Here, the minimum wiring width of the second metal wiring layer and the width required for contact with the first metal wiring layer are larger than the minimum wiring width of the polysilicon layer and the width required for contact, and the wiring pitch is larger than that of the polysilicon layer. also becomes larger. For this reason, usually
The size of the minimum unit cell in the Y direction is determined by the wiring pitch of the polysilicon layer. In this case, the wiring pitch of the second metal wiring layer is often set to twice the minimum unit grid width in the Y direction of the wiring pitch of the polysilicon layer.

FIG. 6 shows an example of such a wiring pattern. In FIG. 6, broken lines 31, 31, . . . are unit lattices in the X direction, dashed lines 32, 32, .
4 is a second metal wiring layer, and 35 is a polysilicon wiring layer.

When the unit lattices and wiring pitches are determined as described above, the unit lattices that can be wired in the second metal wiring layer are the unit lattices 31, 31, . . . in the polysilicon wiring layer, as shown in FIG. Every other one is selected from among them (indicated by the two-dot chain line). However, cell 11k using the same cell library (basic logic circuit prepared in advance)
and 11l are arranged at positions shifted by an odd number of units of the unit cell as shown in FIG. It's different. Therefore, when designing the pattern of the cell library, it is necessary to take this point into consideration and minimize the area where through wiring is prohibited by using the second metal wiring layer. It goes without saying that the second metal wiring layer is indispensable within the cell as an output tap.

FIG. 8 shows the relationship between through wiring prohibited areas and wiring. In FIG. 8, 36, 36,...
... is a through-wiring prohibited area, and 37 is an output tap. The wiring (second layer metal wiring layer) passing above the cell rows 11 ₁ , 11 ₂ , 11 ₃ , . . .
The wiring is done while avoiding the through wiring prohibited area 36 where 7 is present.

By the way, for output wiring, it is unknown whether the odd-numbered or even-numbered unit cells from the end of the unit cell in the cell are selected. must also be placed so that they can be connected. This also applies to two adjacent unit grids, and it is clear that the minimum value of the through wiring prohibited area due to the output tap is the width of two unit grids. However, if output taps are placed carelessly, the through-wiring prohibited area may require three or more wires in a unit grid, and when the through-wiring prohibited area increases in this way, the following various drawbacks occur.

First of all, if the actual number of through wiring is greater than the number of possible through wiring on a cell column, a through wiring area exclusively for through wiring is formed between unit cells. It is necessary and damages the degree of integration.

Second, since the selection of through wiring positions is restricted, it becomes difficult to optimize the wiring algorithm, which impairs the degree of integration.

Third, if there are many restrictions on the positions of through wiring, the number of wirings in the direction parallel to the cell column increases, which impairs the degree of integration and causes a decrease in operating speed.

[Purpose of the invention]

This invention was made in view of the above circumstances, and its purpose is to optimize the position of the output tap within the cell in a polycell automatic layout method using multilayer metal wiring. It is an object of the present invention to provide a semiconductor integrated circuit device which can minimize the prohibited area for through-wiring passing through and improve the degree of integration.

[Summary of the invention]

That is, the semiconductor integrated circuit device of the present invention has the following features:
A plurality of cell rows formed by unit cells housing various functional circuits, and a first metal wiring layer and a second metal wiring layer arranged between these cell rows based on a unit grid. , and a wiring layer forming the gate electrodes of various functional circuits, and an output tap consisting of the first metal wiring layer for leading the output signal from the unit cell to the outside of the cell. and the minimum unit cell width is twice the minimum width of the first or second metal wiring layer.
The distance between the output tap and the unit grid at the shortest distance that does not intersect the output tap is set to be greater than or equal to the sum of 1/2 and the minimum space width, and the distance between the output tap and the unit grid at the shortest distance that does not intersect the output tap is 0 and the first or second metal wiring. It is arranged so that it is between one-half of the minimum width of the layer.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Figure 1 shows the design standards (or process standards) for the metal layer used as output wiring.
The minimum width, the minimum space width, the output tap within the cell, and the through wire passing over the cell are shown, respectively. Note that all these metal layers are the same.

Here, one-half of the minimum width of the metal layer is defined as W, the minimum space width is defined as S, and the minimum unit grid width is defined as Px. Further, the distance from the end of the output tap in the X direction to the unit grid at the shortest distance that does not intersect with the output tap is defined as ΔX. In addition, 31m, 31n, 31
o, 31p is a unit cell, 37 is an output tap, 38
is through wiring.

As mentioned above, since the unit grid planned for output wiring requires at least two or more adjacent unit grids, the unit grids 31o and 31p in FIG.
Let be the unit cell for output wiring.

First, consider the maximum value of ΔX. Since the output tap 37 and the output wiring must be connected regardless of whether the unit grid 31o or 31p is selected as the output wiring, ΔX≦W (1). Next, consider the minimum value of ΔX. The space between the through wiring 38 passing over the unit grid 31n and the output tap 37 is the minimum space width S.
Since the above is necessary, the following equation (2) is derived.

ΔX+(Px-W)≧S...(2) From the previous equation (2), ΔX≧W+S-Px...(3). From the above equations (1) and (3), (a) When Px>W+S, "W+S-Px<0", so "0≦ΔX≦W" holds true.

(b) In the case of Px=W+S, it is clear that "0≦ΔX≦W".

(c) If Px<W+S, “W+S−Px≦ΔX≦
W'', a simple condition cannot be obtained.

As mentioned above, in the case of condition (c), ΔX cannot be obtained by a simple formula, so when arranging the output tap 37 above the cell 11m, each design standard and unit grid standard etc. are always taken into consideration. There is a need. On the other hand, under the conditions shown in (a) and (b), ΔX is larger than 0 and smaller than W, so the output tap 37
The output taps 37 may be arranged in contact with adjacent unit grids or at a distance of less than 1/2 the width of the metal layer used for output wiring, and the arrangement of the output taps 37 is simple.

Under the conditions (a) and (b) above, that is, “Px≧W+
When the output tap 37 is arranged so that 0≦ΔX≦W under the condition “S”, the prohibited area of the through wiring 38 becomes the diagonally shaded area 39 shown in FIG. In this case, the prohibited unit cells are 30o, 30o
There are only two lines of p, which can be the minimum. Therefore, the position of the output tap 37 can be optimized and the degree of integration can be improved. At this time, output tap 37 and output wiring 4
0 is combined as shown.

FIGS. 3a to 3f each show the relationship between the through wiring 38, the output tap 37, and the output wiring 40 under each of the above-mentioned conditions. In figure a, Px=
The case where W+S, ΔX<0 is shown. Under this condition, the through wiring 38 and the output tap 37 are too close to each other, so the unit grids 31n, 31o, 3
It is necessary to make the area above 1p a prohibited area for the through wiring 38. Therefore, the degree of integration is reduced.

Also, figure b is Px=W+S, ΔX=0, figure c is
Px=W+S, 0<ΔX<W, and d figure is Px=
The cases of W+S and ΔX=W are shown, respectively.
Under this condition, the only unit grids for which through wiring 38 should be prohibited are 31o and 31p, and the arrangement of output taps 37 can be optimized.

Figure e shows the case where Px=W+S and ΔX>W. Under this condition, the area above the unit grids 31o and 31p becomes a prohibited area for the through wiring 38, and although there is no problem in terms of the degree of integration, the output tap 37 and the output wiring 40
is not connected.

The f diagram shows the case where Px<W+S and ΔX=0. Under this condition, the output tap 37 and the through wiring 38 are too close to each other, so the unit grid 3
It is necessary to make the areas above 1n, 31o, and 31p a prohibited area for the through wiring 38, which reduces the degree of integration.

Therefore, if each of the conditions shown in FIG. 3 b, c, and d is selected, the through wiring 38 and the output tap 37
The relationship with the output wiring 40 can be optimized, and the degree of integration can be improved.

〔Effect of the invention〕

As explained above, according to the present invention, by optimizing the position of the output tap in a polycell layout method using multilayer metal wiring, the prohibited area for through wiring passing over the cell can be minimized, and A semiconductor integrated circuit device with improved degree of integration can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a pattern plan view for explaining a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is a pattern plan view showing areas where through wiring is prohibited, and FIG. 3 is a pattern plan view showing through wiring under various conditions. Pattern plan views showing the relationship between output taps and output wiring, and FIGS. 4 to 8 are diagrams for explaining conventional semiconductor integrated circuit devices, respectively. 11a, 11b, 11c... unit cell, 11 ₁ ,
11 ₂ , 11 ₃ ... cell row, 12 ₁ , 12 ₂ , 12 ₃ ...
...Wiring area, 31m, 31n, 31o, 31p...
...Unit grid, 37...Output tap, 38...Through wiring, 39...Through wiring prohibited area, 40...
Output wiring, Px...Minimum unit grid width, W...Half of the minimum width of the metal wiring layer, S...Minimum space width, ΔX...Distance to the unit grid at the shortest distance that does not intersect with the output tap .

Claims (1)

[Claims] 1 A plurality of cell rows formed by unit cells housing various functional circuits, and a first layer of metal wiring layer and a second layer of metal wiring arranged between these cell rows based on a unit grid. an output consisting of a wiring region in which a layer and a wiring layer forming gate electrodes of various functional circuits are formed, respectively, and the first metal wiring layer for leading an output signal from the unit cell to the outside of the cell; The minimum unit grid width is set to be greater than or equal to the sum of half of the minimum width of the first or second metal wiring layer and the minimum space width, and the output tap is output. A semiconductor integrated circuit characterized in that the semiconductor integrated circuit is arranged so that the distance to the unit cell at the shortest distance that does not intersect with the tap is between 0 and one half of the minimum width of the first or second metal wiring layer. Device.