JPH0572040B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a MOS integrated circuit suitable for a dynamic RAM (DRAM) or the like in which a source power supply voltage conversion circuit is provided within the chip.

[Technical background of the invention and its problems]

MOS integrated circuits, especially memories, are rapidly becoming more highly integrated and larger in capacity.

Along with this, the devices used are being miniaturized. For this reason, the voltage resistance and reliability of the device have become problems, and from a process perspective, LDD
(Lightly Doped Drain) Structures and other improvements have been made, but there are limits to device breakdown voltage and reliability, and low voltage technology has become essential for circuit design. For example, dynamic RAM
(DRAM), as the external input supply voltage
5V single power supply system is adopted from 64KDRAM,
256K and 1M are also commercialized using this method.
DRAM users also strongly desire this 5V single power supply system for 4M and 16M.
For this reason, in 4MDRAM, considering the durability and reliability of the device mentioned above, a step-down circuit is installed inside the chip to step down the external power supply voltage of 5V to approximately 3V and supply it to each circuit inside the chip as an internal drain voltage. The method is being tested.

However, in the method of incorporating a step-down circuit, both a step-down circuit and a substrate bias conversion circuit are included in the chip, which hinders high integration and increases current consumption. Furthermore, if the outputs of both circuits fluctuate due to noise during chip operation, this may lead to malfunction of the circuit. This problem becomes more noticeable as the capacity of memory cells increases. This is because the transient current during chip operation increases as the capacity increases, and the inductance L inside the chip tends to increase as the wiring width decreases.

[Purpose of the invention]

The present invention has been made in view of the above problems, and an object of the present invention is to provide a MOS integrated circuit that is less susceptible to circuit malfunctions due to power supply noise and is capable of stable operation while taking into account the withstand voltage and reliability of the device.

[Summary of the invention]

In the present invention, a source power supply voltage conversion circuit is built inside the chip, its output is inputted as the source power supply voltage inside the chip, the source power supply voltage outside the chip is inputted as the substrate bias of the chip, and the drain power supply voltage outside the chip is inputted as the source power supply voltage inside the chip. The main idea is to use it directly as the drain power supply voltage inside the chip. The source power voltage conversion circuit sets a predetermined reference potential between a low potential (for example, ground voltage Vss) and a high potential (for example, power supply voltage Vcc), and this reference potential and this reference potential are set inside the chip. The output voltage from the power supply voltage conversion circuit, which is output as the source reference potential, is compared by an amplifier circuit.
The reference potential is detected and the reference potential is supplied as the source power supply voltage of the internal circuit of the chip.

〔Effect of the invention〕

According to the present invention, the source power supply voltage inside the chip can be raised from 0V to 2V using a source power supply voltage conversion circuit, and the voltage applied to the device can be relatively reduced, and the withstand voltage and reliability of the device can be sufficiently guaranteed. can.

In addition, while reducing the voltage applied to the device in this way, the source power supply voltage outside the chip is used directly as the substrate bias for the chip, which eliminates the need for a substrate bias generation circuit that was conventionally built inside the chip. It is possible to reduce the area and the current consumption during standby.

Furthermore, in DRAM, fluctuations in the reference potential (Vref) of address buffer circuits and the like are a major problem, but stabilization of the substrate bias can be achieved, which is highly effective in preventing malfunctions.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 schematically shows a system block diagram of a DRAM.

The surface of the pedestal 101 of the IC package is coated with a conductive layer, and the DRAM chip 102 is mounted on the back surface in contact with the conductive layer. Chip drain power supply voltage pad 103 and source power supply voltage pad 104
A drain external power supply voltage (VccExt) 106 and a source external power supply voltage (VssExt) 107 are respectively input from a power supply 105 external to the chip. 1
08 is a blocking capacitor, and here VccExt is 5V and VssExt is 0V.

VccExt is directly input as the internal drain power supply voltage (Vcc Int.) 110 of the internal circuit 109 inside the chip. The internal circuit 109 consists of a basic clock generation circuit 111 and a DRAM circuit 112.
The DRAM circuit 112 further includes core circuits 113 such as DRAM memory cells, sense amplifiers, precharge circuits, decoder circuits, address buffer circuits, I/O circuits, etc.
It is composed of peripheral circuits 114 such as O circuits.

On the other hand, VssExt is boosted to 2V by the power supply voltage conversion circuit 115 inside the chip, and VssInt.
The signal is input to the internal circuit 109 as follows. Further, this VssExt. 107 outside the chip is connected to the package base 101 with a conductive surface, and serves as the substrate potential V _BB 117 of the chip 102.

The source power supply voltage conversion circuit 115 has a block configuration shown in FIG. 201 is a reference potential generation circuit, 202 is an error amplification circuit, and 203 is an internal source potential load circuit. Chip internal source potential
The potential difference between VssInt.116 and the reference potential 204 set by the reference potential generation circuit 201 is amplified by the error amplification circuit 202, and the internal source potential load circuit 2
03, the current consumption of the internal circuit 109 is controlled to stabilize the chip internal source potential VssInt.

FIG. 3 is an actual circuit diagram of FIG. That is,
A reference potential 204 is provided by dividing 5V and 0V of VccExt. and VssExt. by resistors R ₁ and R ₂ . The error amplification circuit 202 includes p-ch MOSFETs Q ₁ to Q3 and n-
The chMOSFETs Q ₄ and Q ₅ constitute a current mirror type error amplification circuit. _Q6 is an n-ch MOSFET for chip internal source potential output load.

Although FIG. 3 shows a CMOS configuration, it is also possible to configure an n-ch MOSFET as shown in FIG. 4. Here, Q ₁ to _{Q 3} are D type, and Q ₄ to _{Q 6} are E type.
It is a type of MOSFET.

In FIGS. 3 and 4, the chip internal source reference potential 204 is set by resistance division, but as shown in FIG. 5, for example, n-ch MOSFETs Q ₇ to _{Q 10} may be used.

FIG. 6 shows a circuit diagram of the address buffer circuit described above. That is, it compares the address input signal Ain with a small amplitude at the TTL level with a reference potential Vref set to an intermediate potential of the amplitude obtained by resistor division, detects whether Ain is H or L, and amplifies it to internally The address signal Aout and its complementary signal Aout are obtained.

Conventionally, in circuits using a substrate bias circuit, the substrate potential V _BB tends to fluctuate due to the junction capacitance of the diffusion layer of the memory cell that contacts the bit line during charging and discharging of the bit line. However, there was a problem in that the Vref line fluctuated, causing the address buffer circuit to malfunction.

FIG. 7 shows an operational waveform diagram of the address buffer circuit of FIG. 6, and the operation will be briefly explained below.

First, let us assume that the clock signals φ ₁ , φ ₂ , φ ₃ , and φ ₄ are respectively “H”, “H”, “L”, and “L” (“H”=5V,
"L" = 2V), MOSFETs _{Q 13} and Q ₁₄ become conductive, node N ₁ is charged to the address input terminal level, and node N ₂ is charged to the reference potential. on the other hand,
MOSFETs ₂₁ , Q ₂₂ and Q ₂₃ also become conductive, nodes N ₅ and N ₆ are charged to “H”, and MOSFETs Q ₁₇ and
Q ₁₈ , Q ₂₆ , and Q ₂₇ also become conductive, and since φ ₃ and φ ₄ are “L”, N ₃ , N ₄ , Aout, and Aout all become “L”.

Next, the clock signals φ ₁ and φ ₂ change from the “H” level to the “L” level, and then the clock signal φ ₃ changes from the “H” level to the “L” level.
changes from “L” to “H”. Then, the MOSFET
An attempt is made to transfer the level of φ ₃ to nodes N ₃ and N ₄ at Q ₁₇ and Q ₁₈ , respectively. However, nodes N ₁ and N ₂ are
This is a sufficient level to make MOSFETs Q ₁₁ and Q ₁₂ conductive, and since there is a level difference between node N ₁ and node N ₂ , there is a difference in conductance between MOSFETs Q ₁₁ and Q ₁₂ , so node N ₃ and There are level differences in _N4 . Here, N ₄ because Ain="H"
“H”, N ₃ “L”. This potential difference is applied to the MOSFET
The flip-flop consisting of Q ₁₅ and Q ₁₆ amplifies,
At the same time, MOSFETs Q ₁₉ and Q ₂₀ are connected to node N ₅ ,
Transfer the states of nodes N ₃ and N ₄ to N ₆ . N ₄ “H”,
Since N ₃ is “L”, MOSFET Q ₁₉ is non-conducting, Q ₂₀
conducts, node N ₅ remains “H”, node N ₆
It changes from “H” to “L”. Since nodes N ₅ and N ₆ are connected to the gates of Q ₁₈ and Q ₁₇ , respectively, when node N ₆ becomes “L”, the conductance of MOSFET Q ₁₇ decreases, and N ₃ “L” and N ₄ “H” Encourage the level difference to grow. Due to the feedback system as described above, N ₃ and N ₆ become "L" level, and N ₄ and N ₅ become "H" level.

Next, when the clock signal φ ₄ changes from "L" to "H", MOSFET Q ₂₆ is conductive because N ₅ and N ₆ are "H" and "L", respectively, and Aout is because Q ₂₇ is non-conductive. The level of φ4 is transferred to _φ4 , and since Aout is “H”, MOSFET Q ₁₅ becomes conductive, Aous becomes “L”, and the address signal Aout
“H” and Aout “L” are output. Reference potential Vref is generated by reference potential generation circuit 601. This reference potential generation circuit 601 is composed of a resistance divider circuit using resistors R ₃ and R ₄ made of polysilicon film, and also has a long
There is VrefAl wiring, and there is large capacitive coupling between it and the semiconductor substrate. This value is generally larger than the capacitance between interconnects. Therefore, in a conventional circuit using a substrate bias generation circuit, when charging and discharging the bit line,
There was a problem that V _BB fluctuated, which caused Vref to fluctuate, causing malfunction of the address buffer circuit with a small margin. This is manifested as a malfunction when inputting Ain to specify a column address or row address after charging and discharging the bit line.

However, in the present invention, V _BB has a large power supply capacity.
Since Vssext. is used as V _BB , this problem is greatly improved. Also, when charging and discharging the bit line,
There is also the problem that Vcc and Vss fluctuate due to the excessive current, but as shown in Figures 1 and 6,
Since VccExt and VssExt, which have large power supply capacities, can be directly divided by resistance, Vref can be significantly stabilized. Furthermore, since there is only one power supply voltage conversion circuit including the substrate bias, the internal circuit 109 including the address buffer circuit itself is resistant to noise.

In FIG. 1, 602 is a signal input pad for Ain. Incidentally, the reference potential generation circuit 601 may be constituted by a MOSFET as shown in FIG.

As explained above, according to the present invention, it is possible to improve device breakdown voltage and reliability, downsize the power supply circuit and reduce power consumption, and significantly improve chip noise malfunction. It is something.

In addition, the present invention is not limited to the above embodiments, and can be implemented with various modifications.

[Brief explanation of the drawing]

Figure 1 is a system block diagram showing an embodiment of the present invention, Figure 2 is a block diagram of a source power voltage conversion circuit, Figures 3, 4, and 5 are circuit diagrams thereof, and Figure 6 is an address buffer. The circuit diagram of the FAR circuit, FIG. 7, is a timing chart of its operation. In the figure, 105...external power supply, 115...
Source voltage conversion circuit, 109...internal circuit.

Claims (1)

[Claims] 1. Among the two types of external power supplies, the high potential external power supply is used as the drain power supply voltage of the internal circuit of the chip, and the low potential external power supply is used as the substrate bias, and the high potential and low potential of the external power supply A predetermined reference potential is set between the potential and the reference potential, and an amplifier circuit compares and detects this reference potential with the output potential from the power supply voltage conversion circuit, which outputs this reference potential as the chip internal source reference potential. A MOS integrated circuit characterized in that the reference potential is supplied as a source power supply voltage of an internal circuit of the chip. 2. The MOS integrated circuit according to claim 1, wherein the chip is a dynamic RAM chip. 3. The MOS integrated circuit according to claim 1, wherein the two types of external power supplies are 5V and 0V, respectively, and the output of the power supply voltage conversion circuit is 2V. 4. The MOS integrated circuit according to claim 1 or 2, characterized in that it comprises an address buffer circuit. 5. The MOS integrated circuit according to claim 4, wherein the reference potential of the address buffer circuit is obtained by dividing the power supply voltage of an external power supply.