JPH0572189B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a drive circuit for a semiconductor device, and more particularly to a drive circuit for a semiconductor device suitable for high-speed switching of two semiconductor devices that operate complementary to each other. It is something.

[Background of the invention]

Conventionally, an inverter circuit using a transistor and a pulse transformer for driving the transistor is described in, for example, Japanese Patent Laid-Open No. 53-24515.

However, in the device described in this publication, sufficient consideration has not yet been made regarding high speed when transmitting a signal from the control circuit to the gate circuit.

[Purpose of the invention]

The present invention relates to a drive circuit for high-speed switching of a semiconductor element such as a MOS/FET, and an object of the present invention is to provide a drive circuit for a semiconductor element that transmits a high-speed and accurate signal.

[Summary of the invention]

The configuration of the semiconductor device drive circuit according to the present invention is as follows:
In order to drive two semiconductor switches that switch in a complementary manner, a pulse transformer is provided. In a drive circuit that switches semiconductor switches, in response to two drive signals for each of the two semiconductor switches, the time from the time when one semiconductor switch is turned on to the time when the other semiconductor switch is turned on is: It is provided with a synchronization circuit that sets the time to an integral multiple of one period of the modulation pulse signal.

[Embodiments of the invention]

Before describing embodiments of the semiconductor device drive circuit of the present invention, a conventional example will first be described.

Here, FIG. 3 is a block diagram of a conventional semiconductor device drive circuit, and FIG. 4 is a time chart thereof.

A conventional pulse width modulation type (hereinafter abbreviated as PWM type) inverter using bipolar transistors has a carrier frequency of several KHz. Also,
The signal delay from the control circuit to the base of the bipolar transistor was several tens of microseconds.

If high-speed semiconductor elements are used in the inverter, the above-mentioned carrier frequency can be increased to several tens of KHz or more.

In the following, MOS/FET is used as a high-speed semiconductor element.
We will explain the case using .

In order for MOS/FETs to operate at high speeds, the signal delay from the control circuit to the MOS/FET gate must be as fast as several hundred nanoseconds to several microseconds.

Furthermore, the control circuit and the gate circuit must be electrically insulated from their power supplies in order to prevent malfunction of the device.

Insulation methods include photocouplers and pulse transformers, but photocouplers have a delay time of several microseconds and are susceptible to noise.

On the other hand, a pulse transformer can achieve a delay of 100 nanoseconds depending on the selection of the primary inductance of the winding.

However, since the primary impedance of a pulse transformer is extremely small, it is necessary to modulate it with a high-frequency pulse signal of several hundred nanoseconds in order to create a wide gate signal.

Here, FIG. 3 is a block diagram of a semiconductor device drive circuit provided with an analog gate circuit on the input side of a pulse transformer, and FIG. 4 is a time chart thereof.

In the gate circuit, it is necessary to create a non-lap time τ _L so that the on-times of MOS/FETM ₁ and M ₂ do not overlap.

For this reason, the drive signal V ₁ is applied to the analog integrator circuit
A delay is created by R ₀₁ and C ₀₁ and a drive signal of V ₂ is obtained via the hysteresis AND circuit 1.

With this drive signal V ₂ and modulation pulse signal E ₀ ,
In the AND circuit 2, a modulation signal of _V3 is obtained.

This modulation signal V ₃ is amplified by the transistor Q ₁ and sent to the gate circuit 3 by the pulse transformer PT.
transmitted to. The secondary output of the pulse transformer PT is rectified by diode 4 and
It is smoothed by R ₃ and capacitor C ₂ .

This smoothed signal is transmitted through transistors Q ₂ and Q ₃
is amplified by transistors _Q4 and _Q5 ,
The gate-source voltage of the MOS/FET is set to the power supply E ₂
A signal of M1GS is obtained by determining whether to supply it from the power source E3 to make a positive signal or to supply it from the power source _E3 to make a negative signal.

Further, the capacitor _C1 is a speed-up capacitor that speeds up the on time and off time of the transistor _Q1 , and the resistor _R2 has the effect of speeding up the off time of the transistor _Q1 .

On the other hand, the drive signal _V1 is inverted by the NOT circuit 5,
A drive signal Y ₁ is obtained, and a drive signal Y ₂ is obtained by an integration circuit of R ₀₂ and C ₀₂ and a hysteresis AND circuit 6, and with this and a modulation pulse signal E ₀ ,
In the AND circuit 7, a modulation signal _Y3 is obtained.

This modulation signal Y ₃ is transmitted to the gate circuit 8 by
This is to create the gate-source signal M2GS of MOS/FETM ₂ .

As a result, as shown in FIG. 4, the M1GS signal and the M2GS signal secure a non-lap time τ _L1 , so that _M1 and _M2 of the MOS/FETs do not become conductive at the same time.

However, the drive signal V ₂ with guaranteed non-lap time
is asynchronous with the modulation pulse signal E ₀ , so the fourth
As shown at the bottom of the figure, the waveform of the modulation signal V ₃ is
The first pulse width t ₀ varies.

Therefore, the smoothed signal V ₄ in Figure 3 is the modulated signal
The capacitor at the first pulse width t ₀ of the V ₃ waveform
C ₂ may not be enough to charge the battery, and the 4th
A state occurs in which the smoothed signal V ₄ in the figure chatters across the threshold voltage Vs of the transistors Q ₂ and Q ₃ . Therefore, M ₁ of MOS/FET
The voltage between the drain and source of the device causes chattering when it is turned on.

In addition, due to high-speed switching in nanoseconds,
Due to variations in R ₀₁ and C ₀₁ related to the constant of integration, the
As shown in Figure 4, there are variations in the non-lap time τ _L1 due to the charging time of C ₀₁ and the non-lap time τ _L2 due to the discharging time. This has the disadvantage that the current conductivity of the PWM inverter deteriorates due to the circuit design.

Therefore, in order to prevent the above-mentioned chattering, the resistor R ₃ and capacitor C ₂ in Fig.
It is necessary to make the smoothing time constant large, but if it is made large in this way, the result is that it becomes impossible to achieve frequency characteristics, in other words, high speed.

Next, an embodiment of the present invention will be described with reference to FIGS. 1 and 2.

FIG. 1 is a block diagram of a semiconductor device drive circuit according to an embodiment of the present invention, and FIG. 2 is a time chart thereof.

Note that Q ₁ to _{Q 5} are simply referred to as transistors, but Q ₁ , Q ₂ , and Q ₄ are NPN transistors, and Q ₃ ,
Q ₅ is a PNP transistor, and likewise,
_C1 is a speed-up capacitor, and _C2 is a smoothing capacitor.

The modulation pulse signal E ₀ uses a high-precision oscillator such as a crystal oscillator to obtain an accurate frequency, and the modulation pulse signal E ₀ is frequency-divided to create an accurate non-lap time τ _L. An output clock pulse _Eo is obtained through the circuit 9.

The drive signal _U1 is latched by the first latch circuit 10 using the clock pulse _Eo as a trigger, and the output signal _U2 is obtained.

Also, to provide accurate non-lap time,
The signal _U2 is further latched by the second latch circuit 11 using the clock pulse _Eo as a trigger, and the output signal _U3 is obtained.

Note that the first latch circuit 10 and the second latch circuit 11 described above correspond to a synchronization circuit to be described later.

The output signal U ₄ shown in the figure is obtained by logically multiplying the signals U ₂ and U ₃ by the AND circuit 12.

At this time, the phase difference between the signals U ₂ and U ₃ related to the output for creating the non-lap time is such that the first half θ _o1 and the second half θ _o2 exactly match, as shown in FIG.

In addition, signal U ₄ related to output and pulse signal for modulation
E ₀ means that the AND circuit 2 obtains the modulated signal U ₅ .

Here, the signal U ₄ related to the output of the AND circuit 12
and the modulated pulse signal E ₀ are precisely synchronized, so that the first pulse width t ₀ of the modulated signal U ₅
is always a constant width.

If a signal with an accurate pulse width is amplified by the transistor _Q1 and the signal is transmitted from the pulse transformer PT to the gate circuit 3, the gate signal _M of the MOS/FETM1
1GS transmits accurate signals without chattering.

Similarly, the drive signal U ₁ is inverted by the NOT circuit 5 to obtain a drive signal for the MOS/FETM ₂ ,
An output X ₃ is obtained via the first latch circuit 10 and the second latch circuit 11. Additionally, including output x ₂ ,
An output _X5 is obtained via an AND circuit 13 and an AND circuit 7, and the waveform is shaped by a gate circuit 8 to obtain a gate signal M2GS of the MOS/ _FETM2 .

Therefore, the non-lap time τ _L can be easily adjusted by changing the frequency division ratio of the frequency divider circuit 9.

As described above, in the above embodiment, the modulation signals U ₅ and X ₅ related to the two drive signals for each of the two semiconductor switches MOS/FETM ₁ and M ₂ are
, from the time when one MOS/FETM ₁ is turned on (the first time of U ₅ in Fig. 2), the other MOS/FETM 1 is turned on.
The time up to the point when MOS/FETM ₂ is turned on (the first point of _X5 in Figure 2) is expressed as the modulated pulse signal _E0
As mentioned earlier, the time is an integral multiple of one cycle of
A synchronization circuit relating to the first and second latch circuits 10 and 11 is provided.

According to this embodiment, the modulation pulse width of the signal applied to the pulse transformer is equal to that of the first modulation pulse signal.
Since the signal has a constant width from the pulse width t ₀ of U ₅ , the waveform obtained by rectifying and smoothing the secondary output of the pulse transformer becomes smooth.

As a result, the gate signal of the MOS/FET is free from chattering, and the precision of the non-lap time width is accurate.

Furthermore, since a stable non-lap time width can be obtained, the time width can be reduced, and by increasing the frequency of the PWM carrier wave and improving the duty ratio, a highly efficient inverter can be realized.

Although the above embodiments have been described with respect to MOS/FETs, the present invention is not limited thereto, and can be widely applied to semiconductor elements having the same function.

〔Effect of the invention〕

According to the present invention, it is possible to provide a driving circuit for a semiconductor element that can transmit high-speed and accurate signals, and it can be said that the present invention has excellent practical effects.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a semiconductor device drive circuit according to an embodiment of the present invention, FIG. 2 is a time chart thereof, and FIG. 3 is a block diagram of a semiconductor device drive circuit according to a conventional example. 4 is a time chart thereof. U ₁ ... Drive signal, E ₀ ... Modulation pulse signal,
M1GS, M2GS...MOS/FETM ₁ , _M2 gate-source signal, 2, 7, 12, 13...
AND circuit, 5... NOT circuit, 3, 8... gate circuit, 4... diode, 9... frequency dividing circuit, 10
...First latch circuit, 11... Second latch circuit, Q ₁ , Q ₂ , Q ₄ ... NPN transistor, Q ₃ ,
Q ₅ ... PNP transistor, C ₁ ... Speed up capacitor, C ₂ ... Smoothing capacitor, E ₁ ...
Control power supply, E ₂ ...Positive gate power supply, E ₃ ...Negative gate power supply.

Claims (1)

[Scope of Claims] 1. Concerning the driving of two semiconductor switches that switch in a complementary manner, a pulse transformer is provided, and the drive signal to the semiconductor switch is pulse-width-modulated by a modulation pulse signal, and the above-mentioned In a drive circuit that switches the semiconductor switches via a pulse transformer, in response to two drive signals for each of the two semiconductor switches, from the time when one semiconductor switch is turned on, the other semiconductor switch is turned on. A drive circuit for a semiconductor device, comprising a synchronization circuit that makes the time up to the point in time equal to an integral multiple of one cycle of the modulation pulse signal. 2. In what is stated in claim 1,
The synchronization circuit divides the modulation pulse signal into a frequency dividing circuit,
Two latch circuits that use the output signal of this frequency divider circuit as a clock pulse, and two
What is claimed is: 1. A drive circuit for a semiconductor device, comprising a circuit for calculating an AND of two output signals and the modulation pulse signal.