JPH0572748B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of forming an integrated circuit, and particularly to a method of forming a wiring structure of a semiconductor integrated circuit device using multilayer wiring.

(Prior art) Conventionally, in a semiconductor device using multilayer wiring,
If you want to know the characteristics of an internal element that is connected to an internal circuit by the first layer wiring through a contact part, it is normal to know that other internal elements are densely formed around the internal element used in the circuit. Therefore, even if the first layer wiring was changed to the master slice wiring, the measurement pad could not be placed and the characteristics could not be measured. Therefore, as shown in FIG.
Therefore, it was necessary to specially form the same element as the internal element 11 connected to the internal circuit as a single measuring element 14 that is not electrically connected to the internal circuit. The measurement element 14 is connected to the first layer wiring 16 at the contact portion 15 and further connected to the second layer wiring 18 via the through hole portion 17, and uses the second layer wiring 18 as a measurement terminal to measure the characteristics. Was.

(Problems to be solved by the invention) This causes the chip size to increase, and the characteristics of the elements used in the internal circuit are not the same and lack accuracy. The drawback was that I couldn't know much about it.

An object of the present invention is to provide a method for forming an integrated circuit having a wiring structure that allows accurate measurement of element characteristics of an internal circuit.

(Means for Solving the Problems) A method for forming an integrated circuit according to the present invention includes the steps of forming a plurality of first layer wirings connected to each of a plurality of internal elements formed on a substrate; is connected to the plurality of first layer wirings and is integrally formed with the characteristic measurement pad, and at least one of the plurality of second layer wirings is connected to the plurality of first layer wirings to form an internal circuit. It is characterized by having the step of forming.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIGS. 1a and 1b are schematic plan views of internal wiring of a semiconductor integrated circuit device illustrating an embodiment of the present invention. In the internal element 1 shown in FIG. It is electrically connected to the first-layer wiring 7, so that the internal element 1 can be connected to other internal elements of the circuit and perform a circuit function.

Here, in order to measure the characteristics of the internal element 1,
The second layer wiring 5 in FIG. 1a is changed to a master slice second layer wiring 8 as shown in FIG. 1b.
Thereby, the internal element 1 is electrically isolated from the internal circuit, and the characteristics of the internal element 9 can be accurately measured independently.

FIG. 2 is a schematic plan view of a wafer illustrating another embodiment of the present invention. By inserting in advance the pattern of the second layer wiring 8 for master slicing shown in FIG. 1 into a part of the mask used in the photolithography process of the second layer wiring, it is possible to simultaneously , a part of the chip 10 of the wafer 9 can be formed with the second layer wiring 8 for master slicing, and the chip 10 can be used as a measurement chip to measure the characteristics of internal elements.

(Effects of the Invention) As described above, the semiconductor integrated circuit device having the multilayer wiring structure according to the present invention can directly measure the characteristics of internal elements used in the circuit, and also eliminates the need to form special measurement elements. Therefore, the chip size can be reduced.

[Brief explanation of drawings]

1a and 1b are schematic plan views of internal wiring of a semiconductor integrated circuit device illustrating an embodiment of the present invention;
FIG. 3 is a schematic plan view of a wafer explaining another embodiment of the present invention, and FIG. 3 is a schematic plan view of internal wiring of a semiconductor integrated circuit device explaining the prior art. 1, 11... Internal element, 2, 12, 15... Contact portion, 3, 7, 13, 16... First layer wiring, 4, 6, 17... Through hole, 5, 18...
...2nd layer wiring, 8...2nd layer for master outer slice
Layer wiring, 9... Wafer, 10... Chip formed using second layer wiring for master slicing, 1
4...Measurement element.

Claims (1)

[Claims] 1. Forming a plurality of first layer wirings connected to each of the plurality of internal elements formed on the substrate, and at least one being connected to the plurality of first layer wirings and integrally formed with a characteristic measurement pad. and at least one other step of forming a plurality of second layer wirings constituting an internal circuit by connecting the plurality of first layer wirings.