JPH0573289B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a delay device, and particularly to a delay device applied to a system that requires highly accurate delay time setting.

(Prior Art) For example, the conventional delay circuit is shown in FIGS. 8 and 9.
The delay circuit of FIG. 8 is constructed as shown in the figure, and is composed of resistive elements R1 to Rn and capacitive elements C1 to Cn. Generally, polysilicon resistors or diffused resistors using impurities are used for the resistive elements R1 to Rn, but the resistance values of these resistive elements depend on the physical size of the resistive elements during the manufacturing process, It largely depends on variations in impurity concentration, etc. Similarly, capacitive elements C1~
The capacitance value of Cn also depends largely on variations in the plate electrode size, the thickness of the insulating layer, etc.

That is, in a delay circuit having such a configuration, the delay time largely depends on process parameters, so there is a considerable problem in the delay accuracy.

FIG. 9 shows a delay circuit in which inverters I1 to In are connected in multiple stages. Since the delay circuit configured in this manner is a digital circuit delay, there are fewer variations due to process parameters than in a delay circuit using a resistive element and a capacitive element as shown in FIG. However, even in such digital circuit delays, the problem of variation still exists. Further, since the delay circuit configured in this manner is a digital circuit delay, a considerably large number of connection stages is required in order to obtain a long delay time. Therefore, it is not suitable for high integration.

(Problems to be Solved by the Invention) This invention has been made in view of the above points, and aims to improve the problem that in conventional delay circuits, the delay time is largely dependent on variations in process parameters. The present invention aims to provide a highly accurate delay device that does not depend on variations in process parameters even if they occur.

[Structure of the invention] (Means for solving the problem) In other words, in the delay device according to the present invention,
A phase-locked loop circuit is used, in which an oscillation circuit and a delay circuit provided in this circuit are formed with the same element configuration, and the oscillation circuit is activated based on a control signal output from a low-pass filter in the phase-locked loop circuit. In addition to controlling the oscillation frequency of the delay circuit, the delay time of the delay circuit is also controlled by the control signal.

(Function) In the delay device equipped with the above means, the oscillation frequency of the oscillation circuit is controlled by the control signal from the low-pass filter so that it corresponds to the reference frequency signal, and the oscillation circuit is controlled by the control signal from the low-pass filter. The delay circuit, which has the same element configuration as , is also controlled by the control signal from the low-pass filter, so even if there are variations in process parameters,
The delay time of the delay circuit can be controlled to a predetermined value by the control signal output from the low-pass filter.

(Example) Examples of the present invention will be described below with reference to the drawings. FIG. 1 shows a delay device according to an embodiment of the present invention, and this delay device is composed of a phase-locked loop circuit 11 and a delay circuit 12. As shown in FIG. The phase locked loop circuit 11 includes a voltage controlled oscillator 1
3. Phase comparator 14 and low-pass filter 15
It is configured to oscillate at the frequency of a reference frequency signal supplied from the outside. Further, the voltage controlled oscillator 13 is formed with the same element configuration as the delay circuit 12.

The phase comparator 14 is supplied with the oscillation frequency signal output from the voltage controlled oscillator 13 and a reference frequency signal having a predetermined frequency, and the phase comparator 14 corresponds to the phase difference between these two frequency signals. Outputs a pulse signal. This pulse signal, that is, the output signal from the phase comparator 14, is integrated by a low-pass filter 15 consisting of a CR time constant circuit of a resistor R and a capacitive element C, as shown in FIG. converted to voltage.
The DC voltage output from this low-pass filter 15 is supplied to the voltage controlled oscillator 13 as a voltage control signal.

For example, as shown in FIG. 3, the phase comparator 14 includes a phase difference detection circuit 141 that detects a phase difference between the oscillation frequency signal from the voltage controlled oscillator 13 and the reference frequency signal, The charge pump circuit 142 outputs a high-level or low-level pulse signal in response to the phase difference detection signal output from the detection circuit 141.
The phase difference detection circuit 141 includes two D-type flip circuits F1 and F2, and each data input D of the circuits F1 and F2 receives a high level signal.
V _D is always supplied, and the clock signal input CLK
are supplied with the oscillation frequency signal from the voltage controlled oscillator 13 and the reference frequency signal, respectively. The Q outputs of these flip-flop circuits F1 and F2 are both connected to the input of an AND circuit A1, and the output of this AND circuit A1 is supplied to the reset input R of the flip-flop circuits F1 and F2, respectively. It's getting old.

The charge pump circuit 142 is composed of a P channel type MOS transistor Q1 and an N channel type MOS transistor Q2 connected in series between a power supply voltage terminal to which voltage _VD is supplied and a ground terminal. An inverting circuit N1 is connected to the gate electrode of the type MOS transistor Q1.
The Q output signal of the flip-flop circuit F1 which is inverted by the Q output signal is supplied to the gate electrode of the N-channel type MOS transistor Q2.

FIG. 4 shows a specific example of the configuration of the voltage controlled oscillator 13.
It is composed of a voltage generating circuit 13a and a ring oscillator 13b. The voltage generation circuit 13a is configured by connecting a P-channel MOS transistor Q3 and an N-channel MOS transistor Q4 in series, and a voltage control signal from the low-pass filter 15 is applied to the gate electrode of the N-channel MOS transistor Q4. is now being supplied. Further, this voltage control signal is also supplied to the gate electrodes of N-channel MOS transistors Q11, Q12, . . . , Q1n of the ring oscillator 13b. Voltage generation circuit 1
The output voltage signal outputted from 3a is supplied to the gate electrodes of P-channel type MOS transistors Q21, Q22, . . . , Q2n of ring oscillator 13b. Therefore, each MOS transistor Q
11, Q12,...Q1n, and Q21, Q2
2, ... Since the conduction resistance of Q2n is controlled by the voltage control signal and the output voltage signal of the voltage generation circuit 13a, the CMOS inverter consisting of a P-channel MOS transistor and an N-channel MOS transistor 131,
The operating speeds of 132, . . . , 13n are controlled by the voltage control signal.

In addition, the output inverter 131 of the inverter 13n
Since the ring oscillator 13b is feedback-connected to the input of the ring oscillator 13b, the ring oscillator 13b oscillates at the frequency f.
This oscillation frequency f is f=1/2nT, where T is the delay time of each stage constituting the ring oscillator 13b, that is, the delay time of each of the CMOS inverters 131, 132, . . . 13n. Here, n corresponds to the number of CMOS inverters in the ring oscillator 13b,
It is an odd number.

FIG. 5 shows the voltage controlled oscillator 13 shown in FIG.
This figure shows the configuration of the delay circuit 12 corresponding to the above, and is formed with the same element configuration as the voltage controlled oscillator 13. That is, this delay circuit 12
The voltage generating circuit 12a is composed of a voltage generating circuit 12a and a delay generating section 12b, and the voltage generating circuit 12a is composed of a P-channel type MOS transistor Q5 and an N-channel type MOS transistor Q6 connected in series. A low pass filter 1 is connected to the gate electrode of this N-channel type MOS transistor Q6.
5 is supplied with a voltage control signal, and this voltage control signal is supplied to the N-channel type delay generator 12b.
MOS transistors Q31, Q32,..., Q3n
It is also supplied to each gate electrode. The output voltage signal from the voltage generation circuit 12a is transmitted to the P channel type MOS transistor Q41,
It is supplied to each gate electrode of Q42,...Q4n. Therefore, each MOS transistor Q31,
Q32,...Q3n, and Q41, Q42,...Q
Since the 4n conduction resistances are each controlled by the voltage control signal and the output voltage signal of the voltage generation circuit 12a, the P-channel type MOS
CMOS inverters 121, 122 consisting of transistors and N-channel MOS transistors,
..., 12n are controlled by the voltage control signal.

Furthermore, since the input signal is supplied to the input of the CMOS inverter 121 in the first stage of the delay generating section 12b, this input signal is delayed by T for each stage, and is delayed by nT in total. is output.

FIG. 6 shows another configuration example of the voltage controlled oscillator 13. In this configuration example, P channel type MOS transistors Q61,
Transfer gates consisting of Q62,...Q6n and N-channel MOS transistors Q51, Q52,...Q5n are connected, and the delay time of each stage consisting of the transfer gate and inverter is controlled by changing the conduction resistance of these transfer gates. The oscillation frequency can be controlled by Voltage controlled oscillator 1 configured in this way
The configuration of the delay circuit 12 corresponding to No. 3 is as shown in FIG.

That is, inverters 121, 122,..., 1
P channel type on each input side of 2n.
MOS transistors Q81, Q82,...Q8n,
and N-channel MOS transistor Q71,
Transfer gates made up of Q72, .

In this way, the delay circuit 12 and the voltage controlled oscillator 1
By forming the delay circuit 12 with the same element configuration and controlling with the same voltage control signal, the delay circuit 12
The delay time becomes nT, and the oscillation frequency f of the voltage controlled oscillator 13 becomes f=1/2nT.

That is, the delay time of this delay circuit 12 is controlled by a voltage control signal for controlling the voltage controlled oscillator 13 of the phase locked loop circuit 11.
In this case, the voltage control signal controls the voltage controlled oscillator 13 to generate the same frequency signal as the reference frequency signal in accordance with the circuit characteristics of the voltage controlled oscillator 13.

Here, this voltage controlled oscillator 13 and the delay circuit 1
The voltage control signal is supplied to this delay circuit 12, and its delay time is set. Therefore,
The delay circuit 12 is controlled under the same conditions as the voltage controlled oscillator 13 having the same element configuration, and as a result, its delay time is controlled based on the reference frequency signal.

Therefore, if the frequency of the reference frequency signal input to the phase comparator 14 is set based on the delay time desired by the delay circuit 12, a highly accurate delay device that does not depend on variations in process parameters can be created. It becomes possible to realize it.

[Effects of the Invention] As described above, according to the present invention, since the delay circuit and the voltage controlled oscillator undergo similar changes due to variations in process parameters, the control signal output from the low-pass filter of the phase-locked loop circuit The delay time of the delay circuit is controlled to a predetermined value. Therefore, a highly accurate delay device that does not depend on variations in process parameters can be provided.

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating the configuration of a delay device according to an embodiment of the present invention, FIG. 2 is a diagram showing the configuration of a low-pass filter provided in the delay device, and FIG. 3 is a diagram illustrating the configuration of a low-pass filter provided in the delay device. 4 is a diagram showing the configuration of a voltage controlled oscillator provided in the delay device. FIG. 5 is a diagram showing the configuration of a delay circuit provided in the delay device. FIG. 6 is a diagram showing another example of the voltage controlled oscillator, FIG. 7 is a diagram showing another example of the delay circuit, and FIGS. 8 and 9 are diagrams explaining conventional delay circuits. 11... Phase locked loop circuit, 12... Delay circuit,
13... Voltage controlled oscillator, 14... Phase comparator, 15
...Low pass filter.

Claims (1)

[Claims] 1. A first delay circuit configured by serially connecting signal inverting circuits in which the delay time between input and output is controlled based on an input control signal, A voltage controlled oscillator circuit configured by connecting the output of the final stage signal inverting circuit in feedback to the input of the first stage signal inverting circuit, a reference frequency signal to be set, and an oscillation frequency signal output from the voltage controlled oscillator circuit. a phase comparator that detects the phase difference between the two and outputs the phase difference detection signal, and converts the phase difference detection signal from this phase comparator into a DC voltage signal and sends it to the voltage controlled oscillator circuit as the control signal. It consists of a low-pass filter that configures a phase-locked loop circuit by outputting it, and a signal inversion circuit that controls the delay time between input and output based on the input control signal, connected in series, and the signal inversion circuit in the first stage. a second delay circuit that delays the input signal supplied to the input of the circuit and outputs it from the final stage signal inverting circuit, and the signal inverting circuit of the second delay circuit is similar to the first signal inverting circuit.
The second delay circuit has the same element configuration as the signal inversion circuit of the second delay circuit, and the output of the last stage signal inversion circuit of the second delay circuit is electrically isolated from the input of the first stage signal inversion circuit. delay device. 2. The delay device according to claim 1, wherein the signal inversion circuit includes an inverter and a switching element that is connected in series to a current path of the inverter and whose conduction resistance is controlled based on the control signal. . 3. The delay device according to claim 1, wherein the signal inversion circuit includes an inverter and a transfer gate that is connected in series to the current path of the inverter and whose conduction resistance is controlled based on the control signal. . 4. The delay device according to claim 1 or 3, wherein the inverter provided in the signal inversion circuit has a CMOS configuration.