JPH0574272B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image signal converting device, and is particularly applicable to, for example, a special effect generating device for adding special effects to a television signal.

[Background technology and its problems]

Conventionally, this type of special effect generating device is used to write or read a video signal converted into a digital code into an image memory having a predetermined memory capacity, for example, a memory capacity for one frame. A system has been proposed that converts an input video signal containing a flat image into an output video signal with special effects by controlling the input video signal using a special effect. As an image signal conversion device based on such a principle, one having the configuration shown in FIG. 1 can be considered.

In FIG. 1, reference numeral 1 designates an image signal converting device as a whole, where an input image signal S1 is given to a border generation circuit 2, and an image signal S2 formed by adding a frame within the screen is input to a writing interpolation filter as an input image digital signal. feed into circuit 3. Write interpolation filter circuit 3
adds interpolation data to the image signal S2 as necessary, and then provides the write image data S3 to the frame memory 4 as an image memory. The frame memory 4 has an odd field memory that stores image data of odd lines and an even field memory that stores image data of even lines, and is configured to store image data for one frame. The image data thus stored in the frame memory 4 is read out in such an order that a special effect is produced at the time of reading, and is applied to the readout interpolation filter circuit 5 as image data S4. This readout interpolation filter circuit 5 uses image data S to add special effects.
When image data at a position not included in 4 is required, interpolation is performed from the image data S4 to obtain image data at the interpolation position, and the interpolated image data is added to send out an output image signal S5. do.

The write address control circuit 6 applies special effects by controlling the write address as necessary when image data is written into the frame memory 4. In other words, a wipe signal S6 containing special effects such as reduction and slide is given to the auxiliary central processing unit (auxiliary CPU) 7, and the data generation circuit 2 determines the position for reducing and sliding the image within the frame. Data S7 is given to write address generation circuit 8. Write address generation circuit 8
A write address signal S8 consisting of an address corresponding to the position data S7 is applied to the frame memory 4 through the address selection circuit 9 to cause the image data corresponding to the reduced and slid position to be written at the corresponding address. At the same time, the write address generation circuit 8 supplies an auxiliary operation command S9 to the write interpolation filter circuit 3 when the reduced position is at the middle position of the image data S2.

Also, the read address control circuit 11 is one of the special effects.
It has a rotational image forming circuit 12 to obtain the effect of rotating the image within the frame, and its rotational position signal is given to the perspective image forming circuit 13 to convert it into position data S12 that generates a perspective image and read it out. It is applied to the address generation circuit 14. In addition to this configuration, the read address control circuit 11 has a cylindrical image forming circuit 15 for converting a planar image stored in the frame memory 4 into a three-dimensional image, for example a cylindrical image, as another special effect, and the cylindrical image position data S
13 to the read address generation circuit 14.

The read address generation circuit 14 generates position data S12.
and a readout address signal S14 corresponding to S13 is applied to the frame memory 4 through the address selection circuit 9, and thus the image data in the frame memory 4 is sequentially read out in an order such that a rotated or perspective image is obtained, or a cylindrical image is obtained. The image data is sequentially read out in the specified order. However, if the image conversion position is in the middle of the address positions of the frame memory 4, the read address generation circuit 14 generates the read interpolation operation command S.
15 is applied to the readout interpolation filter circuit 5.

The operations of the write address control circuit 6 and read address control circuit 11 are controlled by a main central processing unit (main CPU) 16 via a bus 17.

In this embodiment, recursive loops 18 and 19 are provided from the frame memory 4 and the readout interpolation filter circuit 5 to the border generation circuit 2, so that a recursive effect can be produced.

According to the image signal conversion device 1 having the configuration shown in FIG.
When writing image data to the frame memory 4, the write address control circuit operates and sends a wipe signal S.
Image data with reduction and slide effects based on 6 is stored in the frame memory 4, and is rotated based on the rotation and perspective image position data S12 obtained in the read address control circuit 11 when this data is read out. , an output image signal S5 with a perspective effect is obtained, and an output image signal S5 with a cylindrical image effect is obtained based on the cylindrical image position data S13.

By the way, the read address signal S14 generated in the read address control circuit 11 reads out the image data necessary for obtaining a converted image from among the image data for each dot included in each line of image data stored in the frame memory 4. However, when the readout interpolation filter circuit 5 is used to interpolate image data at dot positions that are not stored in the image memory 4, all positions on the screen are It is desirable to be able to calculate interpolated image data using data stored in the image memory 4 for
Therefore, it is effective to prevent the reading of data from the image memory 4 from becoming complicated in terms of simplifying the overall configuration. Incidentally, unless this is done, there is a problem that the image quality of the converted image cannot be increased above a certain level.

[Purpose of the invention]

The present invention has been made in consideration of the above points, and
An attempt is made to read out the image data in the image memory 4 using a relatively simple procedure, and to calculate interpolation data for all dot positions necessary for applying special effects based on the read image data. It is something to do.

[Summary of the invention]

In order to achieve this purpose, the present invention includes:
At least 2 image data stored in the image memory
Image data of a predetermined number of dots included in a line are divided into image data groups and read out sequentially, and interpolation calculations are performed based on the read image data.

〔Example〕

An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 2 is a diagram for explaining the principle of the present invention, and shows an arrangement of dots for one block on the screen. That is, the screen is arranged such that the m-th dot to the m+5-th dot are sequentially adjacent to each other in the H direction (horizontal direction) for each of the n-th line to the n+3-th line.
The image data of the dots included in each line is stored in the frame memory 4 as an image memory at a timing corresponding to a predetermined position of the dot area, for example, the center position.
(FIG. 1).
Therefore, the planar image data stored in the frame memory 4 is divided into dots on each line (in this example,
768 dots)) will be read out so as to be distributed at the center of the area allocated to the area.

By the way, in a standard television signal, the odd-numbered lines, that is, the n-th and n+2-th image data form an odd-numbered field, and the even-numbered lines, that is, the n+1-th and n+3-th image data, form an even field. Form. Furthermore, since the image data of odd and even fields are processed at different timings, the image data of each field is also processed separately. However, the read address control circuit 11 (first
The converted address obtained by the operation in Figure) is the second address.
Since the image data at this converted position is often located between the dot positions in the image shown in the figure and is not stored in the image memory 4, it is obtained by interpolation from four dots around the converted position. In this way, the converted data for each part of the converted image is made continuous and natural. In this embodiment, the image memory 4 has 512 effective lines in the V direction, thus storing image data of 393216 (=768 (H) x 512 (V)) dot positions. .

In the present invention, when reading distributed image data as shown in FIG. 2 stored in the frame memory 4, one block of image data having a predetermined number of image data included in at least two lines is read out as a unit. One block at a time, and H
The frames are read out sequentially from the frame memory 4 in such a manner as to partially overlap each other in the and V directions. In this embodiment, a block of image data consists of 6 dots in the H direction and 2 lines in the V direction for each of the odd and even fields, and 2 dots in the H direction and 1 line in the V direction.
It is designed to have overlapping parts for each line. Thus, the image data in the image memory 4 is for the nth to (n+3)th line group V1,
As shown in FIG. 3, a dot group H1 consisting of m-th to (m+5)-th dots, a dot group H1 consisting of m-th to (m+5)-th dots,
Dot group H2, which is the (m+9)th dot,
The dot groups H3 consisting of the (m+6)th to (m+11)th dots are read out in the order, and the dot groups H1, H2, H2, etc. are read out in the same order for the (n+2)th to (n+5)th line groups V2. H3... are read out in the order, and the line groups V3,
For V4..., dot groups H1, H2,
They are read out in the order of H3...

The image data groups read from the frame memory 4 in this manner are used in the readout interpolation filter circuit 5 to perform interpolation calculations for each group as necessary.

The frame memory 4 has the configuration shown in FIG. 4 so as to be able to send out image data in the manner described above with respect to FIG. In FIG. 4, the frame memory 4 has an odd field memory 21 that stores image data of odd lines and an even field memory 22 that stores image data of even lines. The odd field memory 21 and the even field memory 22 have the same configuration except for the timing at which data is read out. Therefore, in FIG. 4, only the configuration of the odd field memory 21 is shown in detail; comprises a pair of line memories 23 and 24.

Each line memory 23 is static.
Four memory areas 25A to 25D consisting of RAM
and two memory areas 25E and 25F, and the first to sixth memory areas 25A to 25F are connected to the output line 27A of the serial/parallel conversion circuit 26, respectively.
- Connected to 27F. Also line memory 2
Similarly, 4 consists of four memory areas 28A to 28D and two memory areas 28E and 28F, each of which is composed of static RAM.
Sixth memory areas 28A-28F are connected to output lines 27A-27F of serial-parallel conversion circuit 26, respectively.

The serial/parallel conversion circuit 26 is the write interpolation filter circuit 3
The write image data S3 arriving from the source (FIG. 1) is received as an input digital image signal. This write image data S3 is obtained by sequentially transmitting image data of odd and even fields in series as one frame of image data, and sequentially transmitting line data constituting data of each field in series, and further constituting each line. The dot data (i.e., image data) is transmitted in series. The serial-to-parallel conversion circuit 26 sequentially divides the dot data constituting each line into six pieces, assigns them to the first to sixth output lines 17A to 27F, and sends them out as parallel data. That is, first, the first to sixth dot data are sequentially assigned to the output lines 27A to 27F, then the seventh to twelfth dot data are assigned to the first to sixth output lines 27A to 27F, and the 13th to 18th dot data are assigned to the first to sixth output lines 27A to 27F. The dot data is sent to the first to sixth output lines 27A to 27F.
It is arranged so that...

Here, the line memories 23 and 24 are controlled so as to sequentially and alternately take in data from adjacent lines among the lines of the odd field. That is, when the nth line is an odd line, the nth line is taken into the line memory 28, the data of the next odd numbered line (n+2)th line is taken into the line memory 24, and then the data of the next odd numbered line (n+2)th line is taken into the line memory 24. The data of the (n+4)th line, which is the third odd numbered line, is taken into the line memory 23, and then the data of the (n+6)th line, which is the fourth odd numbered line, is taken into the line memory 24, and the following steps are taken. Similarly, data is taken into the line memories 23 and 24 alternately.

In this way, as shown in FIG.
Data for dots a2 to f2 are stored in the memory area 25.
Data for 6 dots is stored in memory areas 25A to 25F in the same manner. Regarding the (n+2)th line, data g1 to l1 for the first six dots are stored in the memory areas 28A to 28F, and the following six dots are stored in the memory areas 28A to 28F.
The data g2 to l2 for dots are stored in the memory area 28.
Data for 6 dots is stored in memory areas 28A to 28F in the same manner. Further, for the (n+4)th line, the first 6 dots of data a11 to f1
1 is stored in the memory areas 25A to 25F, the following 6 dots worth of data a12 to f12 are stored in the memory areas 25A to 25F, and in the same way, 6 dots worth of data are stored in the memory areas 25A to 25F.
They are sequentially stored in F. Furthermore, data g for the first 6 dots for the (n+6)th line
11 to l11 are stored in memory areas 28A to 28F, and the following 6 dots of data g12 to l12
is stored in memory areas 28A to 28F, and thereafter data for 6 dots are stored in memory areas 28A to 28F.
It will be stored on the 28th floor. Thereafter, image data of odd lines are sequentially and alternately transferred to the line memory 23 in the same manner.
memory areas 25A to 25F, or memory areas 28A to 28F of the line memory 24.

Memory areas 25A to 25 of line memory 23
The outputs a to f of F are given to the output selection circuit 30,
Six outputs a~ depending on the operating mode shown in Figure 6.
Of f, sequentially adjacent outputs a and b, b and c,
c and d, d and e, e and f, f and a are sent out as outputs V _1OUT and V _2OUT in this order.

Similarly, memory area 28A of line memory 24
The outputs g to l of ~28F are given to the output selection circuit 31, and they are sequentially g and h, h and i, i and j, j and k, k and l, according to the operation mode shown in FIG.
l and g are sent out in the order as outputs V _3OUT and V _4OUT . Thus, the outputs _V1OUT to _V4OUT sent from the odd field memory 21 are sent to the frame memory 4.
The interpolation filter circuit 5 reads out the image data S4 as
(Figure 1).

The configuration of the even field memory 22 is the same as that described above for the odd field memory 21,
The outputs V _1OUT to V _4OUT thus sent out are sent to the readout interpolation filter circuit 5.

In the above configuration, frame memory 4 (fourth
As shown in FIG. ₆ for the odd field and even field, respectively, there are By selecting one of the two reading modes and applying an address signal in the H direction and an address signal in the V direction, output signals V _1OUT to V _4OUT as shown in FIG. 6 are sent out. The horizontal address signals H and H' are obtained by converting a binary horizontal address (corresponding to the 0th dot to the 767th dot) into a hexadecimal (4+2) address.

In FIG. 6, the first readout mode is when the readout mode designation information _V0 , which is the lowest bit of the vertical address, is logic "0".
Dot data (ie, image data) of two adjacent lines are read out from the line memories 23 and 24 in the order of line numbers.

In other words, as shown in the column "VV'" in Figure 6,
Line memory 23 by V direction address signal V
A line with a smaller line number n is specified for the line memory 24, and a larger line number n+2 is specified for the line memory 24 by the V direction address signal V'. In this state, as shown in the "H" and "H'" columns of FIG.
4 from memory areas 25A to 25D and 28A to 28D of line memories 23 and 24.
While reading the image data for pixels, the memory areas 25E, 25F, and 28 of the line memories 23 and 24 are read out by the address signal H' in the H direction.
Image data for two pixels is read from E and 28F.

On the other hand, the second readout mode is when the readout mode designation information V ₀ is logic "1", and at this time, from the line memories 23 and 24 of the frame memory 4, adjacent two The image data of the line of the book is read out.

That is, as shown in the column "VV'" in FIG. Therefore, the line number n is small for the line memory 24.
Specify +2. In this state, as shown in the columns "H" and "H'" in FIG.
Image data for 4 dots is read out from 8D, and memory areas 25E and 2 of line memories 23 and 24 are read out by address signal H' in the H direction.
Image data for two dots is read from 5F, 28E, and 28F.

The dot data a to f and g to l read out from the memory areas 25A to 25F and 28A to 28F in this way are 6 of the set of image data of two adjacent lines in the range of predetermined dot numbers.
This image data portion is sent to output selection circuits 30 and 31.

The output selection circuits 30 and 31 latch the read dot data a to f and g to l, and
As shown in the column "H ₂ H ₁ H ₀ " in the figure, 12 dot data a to f and g to l are input by 3-bit address signals "H ₂ ", "H ₁ ", and "H ₀ ". Select two pieces of image data for each (four in total) and output image data V _1OUT for interpolation calculation corresponding to two dots on the left and right sides included in two adjacent upper and lower lines required for interpolation calculation. Outputs V _2OUT , V _3OUT , and V _4OUT .

Here, the image data output V _1OUT for interpolation calculation,
V _2OUT , V _3OUT , and V _4OUT mean image data at the four surrounding dot positions sandwiching the dot position that needs to be interpolated, and the image data output V _1OUT is the image data at the two adjacent dot positions. The image data output V _{2OUT corresponds to the dot on the left side of the upper line, the image data output V 3OUT} corresponds to the dot on the left side of the lower line, and the image data output V _3OUT corresponds to the dot on the left side of the lower line. The data output _V4OUT corresponds to the right dot of the lower line.

The output selection circuits 30 and 31 receive the address bit "V ₀ " indicating the read mode along with the address signals "H ₂ ", "H ₁ ", and "H ₀ ", so that when the read mode is V ₀ = "0", However, even when V ₀ = "1", the four image data are sequentially output in the order from image data with a small line number and small bit number to image data with a large line number and large dot number. Select and output as V _1OUT , V _2OUT , V _3OUT , and V _4OUT .

As a result, as shown in FIGS. 7 and 8, even if the readout modes are different, the arithmetic processing of the readout interpolation filter circuit 5 can be performed using the same circuit.

The case of FIG. 7 is an example of reading out the image data of the nth line and (n+2)th line in FIG.
Data from A to 28D and two memory areas 25
While the image data of E, 25F and 28E and 28F are read out in that order, the second addressing mode reads out the image data of two memory areas 25E, 25F.
After reading out F, 28E, and 28F, addressing is performed so that image data in four memory areas 25A to 25D and 28A to 28D can be read out. In this way, the image data selection operations in the output selection circuits 30 and 31 can be performed continuously without interruption. That is, for example, when addressing the image data a1 to f1, a2 to f2, etc. of the nth line in FIG. 5, the first data portion a1 to f1 is addressed in the first addressing mode. Then, the second data portions e1 to d2 are addressed in the second addressing mode, and then the third data portions a2 to f2 are addressed in the first addressing mode,
Thereafter, data addressing is performed in the same manner while alternately switching between the first addressing mode and the second addressing mode.

Similarly, the addressing for the (n+2)th line in FIG. , 3rd
Addressing of data groups g2 to l2 . . . is executed.

In this way, the image data for two dots (stored in memory areas 25E, 25F and 28E, 28F) of the data group specified in the first addressing mode is addressed in the second addressing mode. In some cases, it will be specified twice. In practice, while the image data for 2 dots or the image data for 4 dots is read out in the output selection circuits 30 and 31 in this way, the memory areas 25A to 25F and 28A to 2
The image data for 4 dots or the image data for 2 dots to be read from 8F is switched,
Thus, the output selection circuits 30 and 31 perform the read operation continuously without interruption. In other words, in FIG. 7, for two adjacent lines, the n-th and (n+2)-th, the first data group a1 to f is set in the first addressing mode.
1 and g1 to l1 (code M1
), the output selection circuits 30 and 31
selects a1 _, b1 _and b1, _h1 , then selects b1, c1 and h1, i1, then c
1, d1 and i1, j1, then d1,
Select e1, j1, k1 and output image data
Send as V _1OUT , V _2OUT and V _3OUT , V _4OUT .
Subsequently, the addressing mode is switched to the second addressing mode, and the second data group e1 to d2 is
and k1 to j2 are specified (symbol M
2), the selection circuits 30 and 31 sequentially select a1,
Select f1, k1, l1, then f1, a2
and select l1, g2 and sequentially output image data.
Output as V _1OUT , V _2OUT and V _3OUT , V _4OUT .
Thereafter, the first addressing mode and the second addressing mode are sequentially and alternately switched (indicated by symbols M3, M4, . . . ) to select four image data. As is clear from the explanation of the operation in FIG. 7, the data stored in the line memories 23 and 24 are sequentially read out in sequence, including four adjacent data without excess or deficiency, and continuously.

On the other hand, when reading the image data of the (n+2)th line and (n+4)th line in FIG. 5, as shown in FIG. 8 corresponding to FIG. Image data read from the line memory 24 side that stores image data is sent out as data outputs V _1OUT and V _2OUT , and is read from the line memory 23 that stores image data with a large line number. Except that the image data is sent out as image data outputs V _3OUT and V _4OUT , four adjacent image data can be sequentially read without excess or deficiency and continuously in the same manner as in the case of FIG. 7.

Therefore, the readout interpolation filter circuit 5 interpolates the image data at the conversion dot position between the four image data sequentially applied as described above by calculating based on a predetermined calculation formula as necessary. data can be obtained. This means that interpolated data can be easily obtained for any position on the screen of one frame when converting a flat image stored in the image memory 4 into an image that produces special effects, and thus is sufficient for practical use. This means that it is possible to realize a converted image with smoothness.

Note that the column VV' in Figure 6 contains readout mode specification information.
When V ₀ is logic “0”, the nth and (n+2)th
We have described the operation when reading the data of the th line, but this operation is when reading the (n+4)th line, the (n+6)th line, the (n+8)th line, the (n+10)th line... _The same applies to the operation of the (n+2)-th and (n+4)-th
As mentioned above, the (n+6)th and (n+8)th lines, the (n+10)th
The same applies to the th and (n+12)th lines.

〔Effect of the invention〕

As described above, according to the present invention, the frame memory 4
When processing the data of each dot stored in the image data, a group of image data of a predetermined number of dots are sequentially read out and processed using the same method, thereby simplifying the configuration and procedure for processing the data. By addressing a part of the image data constituting each data group so that they overlap with each other, it is possible to process the image data uniformly and without omissions on the entire screen, thus producing a high-quality converted image signal. can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the image signal conversion device according to the present invention, FIG. 2 is a schematic diagram showing the configuration of the image memory, and FIG. 3 is a mode of reading image data stored in the image memory. 4 is a block diagram showing the detailed structure of the image memory, FIG. 5 is a schematic diagram showing the structure of image data stored in each line memory, and FIG. 6 is a block diagram showing the detailed structure of the image memory. FIGS. 7 and 8 are schematic diagrams for explaining the data read operation of the image memory. DESCRIPTION OF SYMBOLS 1... Image signal conversion device, 4... Frame memory, 5... Read interpolation filter circuit, 6... Write address control circuit, 11... Read address control circuit, 21, 22... Odd number, even number field memory, 23, 24...Line memory, 25A to 25
F, 28A to 28F...Memory area, 26...
Series/parallel circuit, 30, 31...output selection circuit.

Claims (1)

[Scope of Claims] 1. An image memory for storing an input digital image signal, write address generation means for supplying a write address signal to the image memory, and read address generation means for supplying a read address signal to the image memory. and readout interpolation, in which the image signal read out from the image memory is supplied based on the readout address signal supplied from the readout address generation means, and pixel data at each pixel position after conversion is formed by interpolation processing. In the image signal conversion device having a circuit, the image memory sequentially converts dot data portions of predetermined dot numbers among two sets of dot data constituting two adjacent odd-numbered lines of the input digital image signal. A first memory to be recorded in the first and second memory areas, and a dot data portion of a predetermined dot number among two sets of dot data constituting two adjacent even-numbered lines of the digital image signal, respectively, are sequentially recorded. a second memory to record in the third and fourth memory areas, and two successive dot data for the two adjacent odd lines from the first and second memory areas of the first memory section, respectively. a first output selection circuit that selects and outputs at a predetermined timing; and two consecutive pixel data for the two adjacent even lines from the third and fourth memory areas of the second memory section, respectively. a second output selection circuit that selects and outputs at a predetermined timing, and the read address generation circuit includes: The dot data portions of the predetermined dot numbers are sequentially and alternately stored in the first memory area and the second memory area, or in the second memory area and the first memory area.
controlling the image memory in a control manner such that the image memory is read out in the order of the memory areas, and in the second output selection circuit, the dot data of the predetermined dot numbers stored in the third and fourth memory areas are the image memory in a controlled manner such that the portions are read out sequentially and alternately in the order of the third memory area and the fourth memory area, or in the order of the fourth memory area and the third memory area. An image signal conversion device characterized by controlling.