JPH0574939B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method of manufacturing a dielectrically isolated type semiconductor integrated circuit device.

[Conventional technology]

When forming both a high-voltage element and a low-voltage element in a dielectric-insulated separated substrate, in order to satisfy the voltage-resistance performance of the high-voltage element, the substrate has a high resistivity and the depth of the isolated single-crystal silicon island. is generally 40μm
A depth greater than or equal to that is required. On the other hand, the depth of the single-crystal silicon island required for low-voltage elements is sufficient to be about 20 μm, but in the general manufacturing process, the low-voltage element part has the same island depth as the high-voltage element part, and the bottom of the island Even if a high-concentration impurity diffusion region was provided, the collector series resistance was extremely large.

Conventionally, in response to this, there is a manufacturing method shown in FIG. 2 as a technique for forming only the single crystal silicon layer in the high breakdown voltage element part to be thick and the single crystal silicon island in the low breakdown voltage element part to be thin.

In the conventional method, as shown in FIG. 2a, an oxide film such as SiO ₂ is formed as a mask material 2 in a predetermined area on a single crystal silicon substrate 1 having a (100) plane as a surface by photolithography. First, a recess ₃ having a desired depth d3 is formed by etching as shown in FIG. Generally, anisotropic etching using an alkaline aqueous solution such as potassium hydroxide (KOH) aqueous solution is used for this etching.

Next, a deep first V-groove 4 with a desired depth d ₁ for forming a high breakdown voltage element portion is placed at a predetermined position on the surface of the single crystal silicon substrate, and is further placed at a predetermined position on the surface of the recessed portion 3 that will become a low breakdown voltage element portion. A shallow second V-groove 5 with a desired depth d ₂ is formed at the position by photolithography and anisotropic etching. The cross section after anisotropic etching is as shown in FIG. 2c, and it is desirable that the tips of the first V-groove and the second V-groove be formed on substantially the same plane.

Next, as shown in FIG. 2d, a high concentration impurity region 6 is formed,
An insulating film 7 is formed, a polycrystalline silicon layer 8 is thickly stacked as a support as shown in FIG. As shown in FIG.
A shallow single-crystal silicon island 10 for a low breakdown voltage element portion is formed.

[Problem that the invention seeks to solve]

In the conventional manufacturing method described above, a recessed portion is formed by a first photolithography technique and anisotropic etching to form a shallow single-crystal silicon island for a low-voltage element portion, and then a recessed portion is formed later for isolation of a high-voltage element portion. It is necessary to form a deep first V-groove and a shallow second V-groove for isolating low voltage elements using a second or third photolithography technique and anisotropic etching.

Therefore, in the second and third photolithography steps, cracking of the wafer is very likely to occur, and the number of anisotropic etching steps is required at least twice, increasing the number of steps, resulting in lower yields and higher costs. It has the disadvantage of being inviting.

[Means for solving problems]

The present invention solves the above problems by forming a deep V-groove from the silicon substrate surface for insulating and separating the deep single-crystal silicon island in the high-voltage element part, and forming a shallow single-crystal silicon island in the low-voltage element part. A thick masking film is formed on the bottom of the single crystal silicon island in the high voltage element part and a shallow V-groove from its surface. By using a mask film thinner than the above-mentioned mask film, which has an appropriate film thickness determined from the depth of the single crystal silicon island in the element part, the depth of the high breakdown voltage element part and the low breakdown voltage element part can be reduced by one-time anisotropic etching. The present invention provides a method for manufacturing a dielectric insulating isolated substrate that enables the simultaneous formation of single crystal silicon of different sizes.

〔Example〕

Next, the present invention will be explained with reference to the drawings.
FIG. 1 is a longitudinal sectional view of an embodiment of the present invention. First, a single crystal silicon substrate 1 with (100) plane as the surface
As shown in FIG. 1a, an oxide film 2 having a thickness t ₁ sufficient as a mask material is formed on the bottom surface of the single-crystal silicon island in the upper high voltage element section by photolithography. This film thickness _t1 is sufficient to form a V-groove depth by anisotropic etching to separate the high voltage element portions.

Next, an oxide film 3 having a predetermined film thickness t ₂ calculated from equation (1) based on the depth d ₂ of the island desired for the low breakdown voltage element is placed at the position that will become the bottom surface of the single crystal silicon island in the low breakdown voltage element. In the case of this embodiment in which d 2 is formed by photolithography as shown in FIG. 1b, d ₂ =d ₃ .

t ₂ = R _SiO2 /R _Si(100)・d ₃ R _SiO2 ≪R _Si(100) R _SiO2 : Etching rate of the mask material oxide film used by the potassium hydroxide-based etching solution, generally 20 to 70 Å/ MinR _Si(100) : (100) of the single crystal silicon substrate used
Etching rate using potassium hydroxide-based etching solution on surfaces is generally 0.5 μm to 1.5 μm/
Also, the width of the substrate surface of the part to be etched
W ₁ is determined by the desired depth d ₁ of the single crystal silicon island in the high voltage element portion.

Next, the single-crystal silicon substrate using the above-mentioned mask material oxide films of different thicknesses is etched with a potassium hydroxide-based etching solution. First, when the anisotropic etching progresses to a depth _d3 , the oxide film mask material at the bottom of the single crystal silicon island in the low voltage element part is completely removed by the etching solution, as shown in Figure 1c. (100) surface 4 begins to come into contact with the etching solution. As the etching progresses further, as shown in Figure 1(d), a V is formed to insulate each silicon island.
In parallel with the continuous etching of groove 5 by anisotropic etching, etching for forming the bottom surface of the low breakdown voltage silicon island also proceeds.

Finally, as shown in FIG. A relatively shallow V-groove 8 for insulating and isolating the high-voltage element portion and the high-voltage element portion is simultaneously formed in one etching process.

Next, a high concentration impurity region 9 and an insulating oxide film 10 are formed as shown in FIG. 1f, and a polycrystalline silicon layer 11 is laminated thereon as a support as shown in FIG. By removing the single-crystal silicon up to the extent shown in FIG. 1h, it is possible to form a deep single-crystal silicon island 13 serving as a high-breakdown voltage element portion and a shallow single-crystal silicon island 12 serving as a low-breakdown voltage element portion.

In the case of this embodiment, the tips of the V-groove for isolating single-crystal silicon islands in the high-voltage element area and the V-groove for isolating the single-crystal silicon island in the low-voltage element area are always etched at the same time, so the depth from the substrate surface is the same. Since they are on the same plane, it is very easy to control when grinding to the tip during the polishing process.

〔Effect of the invention〕

As explained above, the present invention provides a thick mask film for anti-anisotropic etching on the bottom part of the single crystal silicon island in the high voltage element part on the single crystal silicon substrate. The position is determined based on the desired depth of the single crystal silicon island in the low breakdown voltage element portion. By forming a mask film with an appropriate thickness on a flat wafer using photolithography technology, V-grooves for insulating isolation between each silicon island can be easily formed with a single anisotropic etching process, allowing for different depths. Single-crystal silicon islands in the high-voltage element part and the low-voltage element part can be formed at the same time, preventing wafer cracking in the photolithography process, reducing the number of manufacturing steps, and improving yield. This has the effect of reducing the cost of the separation substrate.

[Brief explanation of drawings]

FIG. 1 is a process cross-sectional view showing an embodiment of the present invention in the order of manufacturing steps. FIG. 2 is a process cross-sectional view showing the conventional method for manufacturing a dielectric insulation isolation substrate in order of steps. Fig. 1 1...Single crystal silicon substrate, 2...Oxide film, 3...Oxide film, 4...Substrate surface, 5...V
Groove, 6... V groove, 7... Low breakdown voltage element portion silicon island bottom, 8... Shallow V groove, 9... High concentration impurity region, 10... Insulating oxide film, 11... Polycrystalline silicon, 12... ...Low voltage element part silicon island, 13...
High voltage element part silicon island, Fig. 2 1... Single crystal silicon substrate, 2... Mask film, 3... Recessed part, 4... First V groove, 5... Second V groove, 6... High concentration impurity Region, 7... Insulating film, 8... Polycrystalline silicon layer, 9... High voltage element part silicon island, 10...
...Silicon island in low voltage element part.

Claims (1)

[Claims] 1. A thin film for a mask with a constant thickness is selectively formed on the surface of a single crystal semiconductor substrate, and a V-shaped groove of a desired depth is formed by etching. Using a polycrystalline semiconductor as a support, the film is wrapped in an oxide film and mutually connected. A method for manufacturing a dielectrically isolated integrated circuit having a plurality of isolated single crystal semiconductor regions, comprising the steps of: selectively forming at least two kinds of thin films for masks having different thicknesses on the surface of a single crystal semiconductor substrate; , a plurality of Vs of a predetermined depth are formed in a predetermined area by one etching process.
Forming single-crystal semiconductor regions with different depths by simultaneously forming a groove, a recess having a desired depth and opening size, and a V-groove having a predetermined depth at a predetermined position on the surface thereof. A method for manufacturing a dielectric insulating isolation substrate.