JPH0574962B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an operational amplifier circuit that uses complementary MISFETs, has a wide frequency band, has low power consumption, and has a good slew rate. Complementary type below
MISFET is called CMOS.

(Prior art and its problems) Conventionally, as a balanced input type CMOS operational amplifier circuit, Masuda, Kitamura, and Nakano in 1985 IEICE General Conference Proceedings 505 "Transconductance Type High-Speed Operational Amplifier" The first announced
A CMOS operational amplifier circuit as shown in the figure is known.

In Figure 1, MOSFET M, which is a constant current source
MOSFET M1 with source commonly connected to 5
and M2 form a differential input pair, MOSFET M3
and M4 are diode-connected and serve as a load for the differential input pair. 1 and 2 are input terminals, and the signal input to terminal 2 is reversed by M2 and sent to the next stage.
It is input to the gate of MOSFET M10, which is one driver of the CMOS cascode output gain stage. In addition, the signal input to terminal 1 is inverted by M1, further input to the gate of MOSFET M6, inverted again, and then passed through a current mirror circuit to the MOSFET, which is the other driver of the CMOS cascode output gain stage. It is input to the gate of M8. The signals input to M10 and M8 are respectively amplified and inverted and output to the output terminal 3.

In this operational amplifier circuit, output terminal 3 and input terminal 1 are connected, and when a falling pulse is input to input terminal 2 as a voltage follower connection, M2
Since the drain voltage of increases, the M connected there
The gate voltage of 10 also increases. Along with that, M1
When the absolute value of the gate-source voltage of M10 becomes smaller than the absolute value of the threshold voltage of M10, M
10 is cut off, and the potential at the output terminal begins to drop while discharging the load capacitance C _L. At this time, the speed at which the potential decreases, the slew rate, is determined by the ratio _IO / _CL of the current IO flowing through M8 and the load capacitance _CL .
In this type of circuit, if you want to reduce power consumption, you cannot increase the value of I _O ,
Slew rate is not good.

In non-balanced input type operational amplifier circuits, the following techniques are conventionally known to improve the slew rate. First, Figure 2 shows the IEEE Journal of
Solid−state Circuit Vol.SC−14 no.6 White
This figure shows a CMOS operational amplifier circuit announced by et al.

In this case as well, connect the voltage follower, and when a falling pulse is input to input terminal 2, the MOSFET will
The drain voltage of M2 rises, and MOSFET M12 whose gate is connected to it is cut off.
The potential of output terminal 3 decreases while discharging the load capacitance C _L and phase compensation capacitance C _C , and the current at that time is
The slew rate is not good as it is limited by MOSFET M13.

In order to improve this point, the gate of M13 was
As shown in the figure, it is connected to the drain of M2 via a source follower M14 with M15 as a load, and is a MOSFET in the opposite channel to M12 when the drain voltage of M2 increases and M12 is cut off. A known technique is to improve the slew rate by increasing the gate-source voltage of M13', allowing a larger amount of current to flow than before, and rapidly discharging the load capacitance and phase compensation capacitance. (IEEE Journal of Solid-state
Circuit vol.SC−14 no.6 (1979), Gregorian,
Nicholson “CMOS Switched Capacitor Filter
(for PCM Voice Codec), Proceedings of the 1981 National Conference of the Institute of Electronics and Communication Engineers, Proceedings 532, Ishigaki, Sato, et al. The total power consumption increases by the amount of power consumed by the sources and followers added to improve the rate.
In addition, in order to widen the frequency band, it is conventionally known to use a cascode type, which has better frequency characteristics than an inverter, but in the circuit type shown in Figure 3, both the input stage and the output gain stage are inverter type. Due to the circuit configuration, the frequency band is narrow as it is. In order to widen the frequency band with the current circuit format, it is possible to increase the current, but this has the drawbacks of increasing power consumption and reducing DC gain. Therefore, it is difficult to reduce power consumption and widen the frequency band with the circuit format shown in FIG.

As an example of using a cascode format with good frequency characteristics, Proc.1982 ISCAS pp241−244“2μm
CMOS Switched Capacitor Circuits for
An operational amplifier circuit as shown in Fig. 4, which was announced by Matsui et al. in ``Analog Video LSI'', is known. In Fig. 4, the source is a constant current source.
The drains of the two N-channel MOSFETs M1 and M2 of the MOSFET differential pair connected to MOSFET M5 are connected in common to the sources of the constant current source MOSFET and the gate-grounded MOSFET, respectively. It is a cascode type differential input-differential output operational amplifier circuit with output terminals 3 and 3' taken out from the connection point with the load, respectively. This circuit has a very wide frequency band because it uses a cascode format and is simple with a single-stage configuration. However, on the other hand, the DC gain is quite small, and since it is a differential output, it can be used to convert differential to single It has the disadvantage that a conversion stage may be required.

(Object of the invention) In view of the above points, the present invention provides a complementary MISFET
The purpose of this invention is to provide an operational amplifier circuit that has a wide frequency band, low power consumption, and a high slew rate without reducing the DC gain.

(Structure of the Invention) The CMOS operational amplifier circuit of the present invention has a source commonly connected to a first DC power supply terminal via a constant current source, and a drain connected to a second DC power supply terminal via a load. first and second MISFETs forming a differential pair, and a third MISFET of a common gate type that is of a conductivity type different from the first MISFET and whose source is connected to the drain of the first MISFET. , a MISFET of a conductivity type different from the second MISFET, whose source is connected to the drain of the second MISFET, and whose gate is connected to the third MISFET.
A fourth MISFET with a gate grounding type that is biased in common with the gate of the MISFET, and a third MISFET.
The drain and gate are connected to the drain of
a fifth MISFET whose source is connected to the first DC power supply terminal to form a current mirror circuit;
a differential input stage consisting of a sixth MISFET whose drain is connected to the drain of the fourth MISFET, whose gate is connected to the gate of the fifth MISFET, and whose source is connected to the first DC power supply terminal; 2 of
A MISFET of a conductivity type different from the MISFET, whose gate is connected to the drain of the second MISFET,
a seventh MISFET whose drain is connected to the output terminal and whose source is connected to the second DC power supply terminal;
The gate is connected to the drain of the sixth MISFET,
A gain stage consisting of an eighth MISFET whose drain is connected to the output terminal and whose source is connected to the first DC power supply terminal, and a gate-grounded P channel and N channel of different conductivity types connected in parallel. The sixth MISFET is characterized in that it includes two MISFETs, and a phase compensation circuit in which a capacitor is connected in series between the output terminal and the drain of the sixth MISFET.

(Example) As one example, a detailed explanation of the configuration will be given with reference to FIG. 5 in which an N-channel MOSFET is used as an input transistor.

The differential input stage is constructed as follows. N-channel MOSFET differential pair M1 and M2 are connected to one output terminal 5 of the DC power supply through a constant current source M5, and the drains are connected to the drains of M1 and M2, respectively, and the source is connected to one output terminal 5 of the DC power supply through a constant current source M5. a P-channel MOSFETM 3 connected to the other output terminal 4 of the DC power supply and whose gates are commonly biased;
M4, M24, M27 and the MOSFET differential pair and M
P channel whose source is connected to the connection point with 3
MOSFET M25, the MOSFET differential pair and M4
The source is connected to the connection point with the gate.
P-channel MOSFET M28 biased in common with the gate of MOSFET M25;
N-channel MOSFET M26 whose drain and gate are commonly connected to the drain of MOSFET M25 and whose source is connected to output terminal 5;
It is composed of an N-channel MOSFET M29 whose drain is connected to the drain of MOSFET M28, whose gate is commonly connected to the gate of MOSFET M26, and whose source is connected to the output terminal 5.

The gain stage is constructed as follows. Consists of two MOSFETs, P-channel and N-channel, whose drains are commonly connected.
MOSFET M30 has its gate connected to the connection point between M28 and M29, and its source connected to output terminal 5, and P-channel MOSFET M31 has its gate connected to the connection point between the MOSFET differential pair and M28, and its source connected to the output terminal. 4, and the output terminal 3 is connected to the connection point between M30 and M31.

The phase compensation circuit connects the connection point between M28 and M29 and the output terminal 3 with a capacitor C _C and M _C1 that acts as a resistor.
It is constructed by connecting in series MC2 and _MC2 connected in parallel.

Next, the operation of this circuit will be explained.

One MOSFET M1 of the MOSFET differential pair
The input signal is inverted by M1, amplified by MOSFET M25 with a grounded gate, passed through a current mirror circuit, and inverted again by MOSFET M29. This signal and the other of the MOSFET differential pair
The signal input to MOSFET M2, inverted, and amplified by MOSFET M28 with a grounded gate configuration overlaps at the connection point between MOSFET M28 and MOSFET M29, and the signal is output to the N-channel MOSFET in the gain stage.
The signal is output to the gate of M30, and the signal is inverted and amplified by M30, and then output to the output terminal.

That is, in the differential input stage, the signal input to the differential pair is then input from the source to the gate-grounded MOSFET, amplified, converted from differential to single, and then output to the gain stage.

The technique of using a MOSFET with a grounded gate configuration in a cascode format to improve frequency characteristics by reducing Miller capacitance is also used in the operational amplifier circuit shown in Figure 4, but in Figure 4 there is a difference. In contrast, in the present invention, the dynamic output remains the same.
MOSFETM26 and M27 are used to convert from differential to single, and a gain stage is further provided to achieve a DC gain value that cannot be achieved with the circuit shown in FIG.

Furthermore, in order to improve the slew rate, in the present invention, of the two MOSFETs in the gain stage, the gate of the N-channel MOSFET is connected to the drain of the MOSFET M28, which has a gate ground plane in the differential input stage.
P channel MOSFET has gate as MOSFET
It is connected to the connection portion between the differential pair and MOSFET M28, that is, the drain portion of M2.

This is due to the following reason. When output terminal 3 is connected to input terminal 1 to make a voltage follower connection, when a falling pulse is input to input terminal 2,
The drain voltage of MOSFET M2 increases. Then, the absolute value of the gate-source voltage of P-channel MOSFET M31 in the gain stage decreases, and M31
is cut off. At that time, the gate ground MOSFET whose source is connected to the drain of M2
The drain voltage of M28 increases with the drain voltage of M2. MOSFET M30 has a gate of M
Since it is connected to the drain of M30, the gate-source voltage of M30 increases, allowing a large amount of current to flow. Therefore the load capacity rapidly
C _L and phase compensation capacitor C _C can be discharged, improving the slew rate.

When a rising pulse is input to input terminal 2, the drain voltage of M2 decreases and accordingly, M
The drain voltage of 28 also decreases, and the gate voltage of M30 decreases, so M30 is cut off, but since the drain voltage of M31 decreases, the gate-source voltage increases, causing a large amount of current to flow. Allows to rapidly increase load capacity
The slew rate can be improved by charging C _L and the phase compensation capacitor C _C.

In other words, two nodes of the gain stage are connected to two nodes where the voltage changes in the same way according to the rise and fall of the input when connected as a voltage follower.
The slew rate is improved by connecting the MOSFET gates.

Although the method of improving the slew rate by adding a source follower as shown in FIG. 3 generates extra power consumption, this does not occur in the present invention, and the power consumption can be reduced. According to Ishigaki, Sato, etc. mentioned earlier, in the circuit format shown in Figure 3,
MOSFET gate length 3μm, frequency band 15MHz,
It has been reported that the DC gain is 57 dB and the power consumption is 6 mW, but the circuit of the present invention has a gate length of 5 μm.
frequency band 10MHz, DC gain 74dB, power consumption
A simulation result of 2 mW was obtained, and by setting the gate length to 3 μm, the frequency band could be increased to 15 MHz without changing the power consumption, resulting in a wide band, low power consumption, and high gain operational amplifier circuit. There is.

(Other Embodiments) As another embodiment, FIG. 6 shows an example in which the N-channel and P-channel MOSFETs are replaced.
In this case, there is no essential difference because the polarity is simply switched.

In yet another embodiment, the output stage is a source
FIG. 7 shows an example in which a follower is added.

This is a P channel for the input MOSFET.
An example using MOSFETs (FIG. 6) is formed by adding N-channel source followers M32 and M33 and connecting the input terminal of the N-channel source follower to the previous output terminal. in this case,
By adding an N-channel source follower as an output stage, the common-mode output voltage range can be set from OV even when the DC power source is, for example, a single 5V, and a P-channel MOSFET can be used as an input MOSFET. In some cases, the common mode input voltage range can be taken from OV.

When an N-channel MOSFET is used as the input MOSFET (as shown in Figure 5), if a P-channel source follower is added as an output stage, the common-mode voltage range for both input and output will be from the positive output voltage of the DC power supply. You will be able to take it.

(Effects of the Invention) As described above, according to the present invention, a CMOS device with low power consumption, a wide frequency band, and a good slew rate can be used.
An operational amplifier circuit can be provided.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing a conventional balanced input type CMOS operational amplifier circuit, Figures 2, 3 and 4 are circuit diagrams showing a conventional CMOS operational amplifier circuit, and Figure 5 is a circuit diagram showing a conventional CMOS operational amplifier circuit.
The figure is a circuit diagram showing one embodiment of the invention, and FIGS. 6 and 7 are circuit diagrams showing other embodiments of the invention. 1 and 2 are input terminals, 3 and 3' are output terminals, 4 and 5 are DC power supply terminals, M1 to M57, _MC1 , _MC2 are
MOSFET, R ₁ and R ₂ are resistances, and C _C , C _L , C ₁ and C ₂ are capacitances.

Claims (1)

[Claims] 1 A differential pair is formed in which the source is commonly connected to a first DC power supply terminal via a constant current source, and the drains are respectively connected to a second DC power supply terminal via a load. the first and second MISFETs, and the first
A third MISFET of a conductivity type different from the MISFET and having a common gate type whose source is connected to the drain of the first MISFET, and a second MISFET.
A MISFET of a conductivity type different from the MISFET, whose source is connected to the drain of the second MISFET,
a fourth MISFET of a gate-grounded type whose gate is biased in common with the gate of the third MISFET;
A fifth MISFET whose drain and gate are connected to the drain of the third MISFET, and whose source is connected to the first DC power supply terminal to form a current mirror circuit.
and a sixth MISFET whose drain is connected to the drain of the fourth MISFET, whose gate is connected to the gate of the fifth MISFET, and whose source is connected to the first DC power supply terminal. and a seventh MISFET, which is a MISFET of a conductivity type different from the second MISFET, whose gate is connected to the drain of the second MISFET, whose drain is connected to the output terminal, and whose source is connected to the second DC power supply terminal. of
The gate is connected to the drain of the MISFET and the sixth MISFET, and the drain is connected to the output terminal.
the eighth whose source is connected to the first DC power supply terminal;
A gain stage consisting of a MISFET and two gate-grounded P-channel and N-channel transistors of different conductivity types connected in parallel.
The MISFET and the capacitor are connected in series to the output terminal and the sixth
Complementary type characterized by including a phase compensation circuit connected between the drain of MISFET
Operational amplifier circuit using MISFET.