JPH0574992B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention improves the signal output method, improves the S/N ratio, facilitates adjustment when manufacturing a television camera, and realizes a highly sensitive television camera. The present invention relates to solid-state imaging devices that can be used.

[Background of the invention]

Figure 1 shows a general solid-state image sensor (S. Ohba et al.
al, “MOS Area Sensor：Part Low−
Noise MOS Area Sensor With Antiblooming
Photodiodes，”IEEE Transactions on
Electron Devices, Vol. ED-27, No.8
August 1980) is a schematic plan view, in which 1 is a chip made of a silicon substrate and has various elements and circuits formed on a flat surface, and 2 is a light receiving section that forms an image of the subject, performs optical-to-electrical conversion, and generates an electrical signal. , 3 is a vertical scanning section that vertically scans each pixel of the light receiving section, 4 is a horizontal scanning section that also horizontally scans, and 5 is an output terminal from which a signal is output.

Such a chip 1 is stored in a package cage,
The light receiving section 2 is covered and sealed with a glass plate. The chip 1 is formed with terminals 5 for signal extraction, voltage supply terminals (not shown), etc., and these terminals are connected to pads formed on the package with thin metal wires of Au or Al, and are connected via lead pins. It is designed to be electrically connected to an external circuit. The output signal outputted to the terminal 5 is amplified by a preamplifier in an external circuit, and inputted to a television image monitor cathode ray tube to display an image of the subject.

FIG. 2 is a hard circuit configuration diagram of a circuit formed on a chip of a conventional solid-state image sensor that extracts signals by the switching action of a MOS type FET (field effect transistor). Although a large number of pixels are formed in a matrix in the light receiving section, only six pixels are shown in the horizontal direction and four pixels are shown in the vertical direction in the figure. Pixels W, G, Cy, Ye are photodiodes 2
White, green, cyan, and yellow color filters are formed on the surface of each pixel, respectively, so that a corresponding color signal is extracted from each pixel. 2
1 is the photodiode 20 and the vertical output line 43 ₁ , 4
Turn on the connection between 3 ₂ , 43 ₃ , 43 ₄ , ...
MOSFET to be turned off, 31 is a vertical scanning shift register of the vertical scanning unit 3, 32 is an interlace circuit, 33 ₁ , 33 ₂ , 33 ₃ , 33 ₄ are vertical gate lines, 41 is a horizontal scanning shift register of the horizontal scanning unit 4, 42 ₁ , 42 ₂ , 42 ₃ , 42 ₄ are vertical output lines 4
3 ₁ , 43 ₂ , 43 ₃ , 43 ₄ and output terminals 5 ₁ , 5 ₂ ,
Turn on/off the connection between 5 ₃ and 5 ₄
It is a MOSFET. In this embodiment, an example will be described in which an element is formed in a P-type well in a P-type silicon substrate or an N-type silicon substrate. Note that when the element is formed in an N-type well in an N-type substrate or a P-type substrate, the operation is the same just by reversing the polarity of the applied voltage.

Now, if a positive potential of 3 to 5 V is applied to the output terminals 5 ₁ to 5 ₄ , after one scan, each signal will be output at the timing of each scan.
The FET is turned on and this voltage is applied to the photodiode 20
p- of each photodiode 20.
A reverse bias of 3 to 5V is applied to the n-junction capacitance. Here, in the photodiode where the light is incident,
The reverse bias is discharged by photoelectrons, and the accumulated charge in the junction capacitance is reduced. This decrease corresponds to the storage amount as an optical signal.

When the first stage scan pulse V ₁ is output from the vertical scan shift register 31, the interlace circuit 32 outputs the vertical gate line 33 in the A field.
₁ and 33 ₂ are selected, and in the B field, vertical gate lines 33 ₂ and 33 ₃ are selected and a positive potential is applied to each. Considering the A field, the pixels W ₁₁ , Cy ₁₂ , connected to the vertical gate line 33 ₁
G ₁₃ , Ye ₁₄ , ..., and each of the pixels G ₂₁ , Ye ₂₂ , W ₂₃ , Cy ₂₄ , ... connected to the vertical gate line 33 ₂
A positive potential is applied to the gate of FET21, and these
All FETs 21 are turned on. As a result, the optical signals stored in each photodiode 20 of the pixel are transmitted to the vertical output lines 43 ₁ , 43 ₂ , 43 ₃ , 43 ₄ , . . .
... respectively. Next, positive potential scanning pulses H ₁ , H ₂ , H ₃ , . . . are sent from the horizontal scanning shift register 41.
... is output sequentially, FET42 ₁ , 42 ₂ , 42
_{3 and 42 4 . _ _ _ _ _} Ru. These outputs correspond to green, white, cyan, and yellow color signals separated by respective color filters.

The arrangement of pixels G ₁₃ , W ₂₃ , Ye ₁₄ , and Cy ₂₄ is vertically reversed from that of the above four pixels, but switching FETs 42 ₅ , 42 ₆ and 42 ₇ , 42 ₈
By reversing the connection on the drain side of the pixels, the color signals from these pixels are outputted to each output terminal of the same color. In this way, since independent color signals are output from each output terminal, there is no need for a color separation circuit that is essential in general single-tube color television cameras, eliminating color noise caused by color separation circuits, and improving S/N. You can get good color signals.

However, the MOSFET is used in the horizontal scanning section explained above.
Instead of using a CCD in the horizontal scanning section
In a solid-state image sensor using a charge transfer circuit such as a charge coupled device (Charge Coupled Device), the color signal is It is output from one output terminal in a time-division manner.

FIG. 3 is a circuit diagram of such a solid-state image sensor. When the scanning pulses V ₁ , V ₂ , . . . are sequentially output from the vertical scanning shift register 31, the interlacing circuit 32a outputs the odd-numbered vertical gate lines 33 ₁ , 33 ₃ , . Vertical gate line 33 ₂ , 33 of row
₄ , . . . are sequentially selected, and a positive potential signal of each gate line is applied. Now, considering the A field for the first stage scanning pulse _V1 , the vertical gate line ₃₃₁ is selected, and all pixels in the first row are
The FETs of R ₁₁ , G ₁₂ , B ₁₃ , ... are turned on,
The optical signals stored in the photodiodes 20 of these pixels are transmitted to the vertical output lines 43 ₁ , 43 ₂ , 43 ₃ , . . .
43 Move to _n . Note that red, green, and blue color filters are formed in the photodiodes 20 of pixels R, G, and B, respectively.

Next, transfer circuits 42a ₁ , 42a ₂ , 42a ₃ ,...
..., 42a _n are operated at the timing shown in Fig. 4b, and the signals on the vertical output lines 43 ₁ to ₄₃
Move everything to position A of 41a. The CCD 41a has three 3-channels with a 120° phase shift as shown in Figure 4c, d, and e.
Phase clock pulses φ ₁ , φ ₂ , and φ ₃ are applied, whereby the charge of the signal transferred to position A is sequentially transferred to the left. Then, the charge sent by the output gate signal OG at the timing shown in Figure 4 f is transferred to the FET of the floating gate amplifier.
44, a current corresponding to the amount of charge flows through the terminal 46--FET 44--load resistor 47, and an output signal as shown in FIG. 4h is taken out from the output terminal 5. After extracting the signal for one pixel, the fourth
The reset signal RG is sent to the FET at the timing shown in Figure g.
In addition to the gate of FET 45, the charge on the gate of FET 44 is discharged to prepare for the next step signal. In this way, the red, green, and blue color signals of each pixel are extracted from the output terminal 5 in time series.

For this reason, such solid-state image sensors require a circuit that time-divides and separates the color signals according to the clock timing, and as a result, color mixing and noise are likely to occur, making it difficult to make adjustments when assembling a color television camera. The man-hours required time and there was a problem with productivity.

[Purpose of the invention]

The present invention has been made in view of the above points, and it is an object of the present invention to provide a solid-state image sensor that does not require a color separation circuit even if a charge transfer circuit is used in the horizontal scanning section.

[Summary of the invention]

In order to achieve such an object, the present invention adds an additional charge transfer circuit having at least N (plural) stages to the charge transfer circuit used for horizontal scanning, and charges are transferred to each position of the N stages of the additional charge transfer circuit. The received signal charges are simultaneously transferred to the gates of N floating gate circuits at a predetermined timing, and N signals are output independently from the output terminal of each floating gate circuit.

If these N signals are divided into N color signals by color filters, each color signal can be output independently, and a color separation circuit is not required.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail based on examples.

FIG. 5 is a circuit configuration diagram of an embodiment of the solid-state image sensor according to the present invention. In the figure, the same or corresponding parts as in FIG. 3 are given the same reference numerals, and their explanation will be omitted.

The color signal transferred to the A position of the CCD 41a is transferred to the left by three-phase clock pulses φ ₁ , φ ₂ , and φ ₃ . To the left of this CCD 41a, three stages of additional CCDs 41b are successively provided, and the added number of stages, three, corresponds to the number of color signals, which is three.
In the case of four colors, white, cyan, green, and yellow, the number of additional stages is also four. At the B position of the additional CCD41b,
As shown in FIG. 6f, a clock pulse φ ₂ ' in which one of the three clocks of φ ₂ is missing is applied, and at the timing when one clock is missing, the output gate 48 receives a clock pulse φ ₂ as shown in FIG. 6g. ” is starting to be applied.

CCD4 by transfer circuits 42a ₁ , 42a ₂ , 42a ₃
The three consecutive red, green, and blue color signal rows moved to the A position of 1a are transferred to the left and output to the additional CCD 41b.
Move to A ₁ , A ₂ , A ₃ positions. Next clock pulse φ ₂
At the timing of , a clock pulse φ ₂ '' is applied to the output gate 48, and the signal charges at the A ₁ , A ₂ , and A ₃ positions are transferred to _the drains 49 ₁ , 49 ₂ , and 49 ₃ , respectively. The structure leading to the drain 49 ₁ is preferably a CCD structure that enables complete charge transfer.Drains 49 ₁ , 49 ₂ ,
The charge transferred to 49 ₃ is applied to the gates of MOSFETs 44 ₁ , 44 ₂ , 44 ₃ of the floating gate amplifier, and the gm (mutual conductance) of this FFT is
control. As a result, a current flows in the path of power supply terminal 46 - FET 44 ₁ - output terminal 5 ₁ - load resistor 47 ₁ - ground according to the amount of charge of the red signal, and as shown in Figure 6i, a current flows from output terminal 5 ₁ to red signal. color signals are output. Similarly, as shown in FIGS. 6j and 6h, a green signal is obtained from the output terminal ₅₂ and a blue signal is obtained from the output terminal ₅₃ . In this way, each color signal is output from the independent output terminals 5 ₁ , 5 ₂ , and 5 ₃ , so that the color signal can be obtained without a color separation circuit.

The voltage applied to the gates of the FETs 44 ₁ , 44 ₂ , 44 ₃ needs to be reset when the next φ ₂ ″ is applied, and therefore the voltages applied to the gates of the MOSFETs 45 ₁ , 45 ₂ , 4
A reset signal RG is applied to the gate of ₅₃ at the timing shown in FIG. 6h. The floating amplifier operates during the period from the generation of the clock pulse φ ₂ '' to the generation of the reset signal, and this period is 3 to 4 times longer than that of the conventional example in Figures 3 and 4, and the signal is affected accordingly. As the energy increases, the S/N becomes higher.

Note that each color signal is output _at the same time without time delay, and the difference in spatial position (difference in detection timing due to scanning) in the light receiving part of the photodiode ₂₀ is eliminated. , it is necessary to provide a delay circuit of two clock times to compensate for this. As a result, the timing of the output signal and the timing of scanning coincide.

In the above embodiments, a CCD was used as the charge transfer circuit, but a BBD (Buchet Brigade Device),
BCCD (Buried Channel Charge Coupled)
Device) etc. can also be used.

〔Effect of the invention〕

As described above, according to the solid-state image sensor according to the present invention, the signal charges transferred to each position of the N stages of the additional charge transfer circuit are simultaneously transferred to the gates of the N floating gate circuits, and the signal charges are transferred from the N output terminals to the gates of the N floating gate circuits. Since it is now possible to output independent signals, when the signal is used as a color signal for N colors, a color separation circuit is not required, and color mixing and noise are eliminated, resulting in a low S/N ratio.
In addition, the adjustment man-hours when assembling a color television camera can be significantly reduced, and productivity can be improved.

[Brief explanation of the drawing]

Figure 1 is a schematic plan view of a general solid-state image sensor.
Figure 2 is a circuit diagram of a conventional solid-state image sensor;
The figure is a circuit configuration diagram of a solid-state image sensor using a conventional CCD, FIG. 4 is a time chart of signals of each part of the circuit, and FIG. 5 is a circuit configuration diagram of an embodiment of a solid-state image sensor according to the present invention. FIG. 6 is a time chart of signals in each part of the circuit. 20...Photodiode, 21...
MOSTFET, 33 ₁ ~ 31 _o ... Vertical gate line,
41a...CCD, 41b...Additional CCD, 42a ₁
~42a _n ...Transfer circuit, _{431 to 43n} ...Vertical output line, ₄₄₁ to ₄₄₃ ...Floating gate amplifier MOSFET, 451 _{to 453} ...For reset
MOSFET, 5 ₁ - 5 ₃ ... output terminal, 48 ... output gate, 49 ₁ - 49 ₃ ... drain.

Claims (1)

[Claims] 1. A solid-state imaging device in which a charge transfer circuit is used in the horizontal scanning section, and the signal from each pixel is transferred to the corresponding stage position of the charge transfer circuit, and then the signal is transferred and output one stage at a time. In the device, an additional charge transfer circuit having at least a plurality of stages added to the charge transfer circuit, and a plurality of output floating gate circuits;
means for transferring the signal charges transferred to each position of the additional charge transfer circuit to the gate of the floating gate circuit at a predetermined timing, and the signal is divided by a color filter of the pixel. The number of color signals divided by the color filter is equal to the number of the output floating gate circuits, and each of the output floating gate circuits outputs each color signal. A solid-state image sensor characterized by: 2. The solid-state imaging device according to claim 1, wherein the number of stages of the additional charge transfer circuit and the number of output floating gate circuits are the same number. 3. The solid-state imaging device according to claim 1 or 2, wherein the means for transferring the signal charges to the gate simultaneously transfers the signal charges. 4. The solid-state image sensor according to claim 1, wherein the number of stages of the additional charge transfer circuit and the number of color signals divided by the color filter are the same.