JPH0575182B2 - - Google Patents
Info
- Publication number
- JPH0575182B2 JPH0575182B2 JP62192860A JP19286087A JPH0575182B2 JP H0575182 B2 JPH0575182 B2 JP H0575182B2 JP 62192860 A JP62192860 A JP 62192860A JP 19286087 A JP19286087 A JP 19286087A JP H0575182 B2 JPH0575182 B2 JP H0575182B2
- Authority
- JP
- Japan
- Prior art keywords
- lsi
- wiring
- wiring board
- chip
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Non-Insulated Conductors (AREA)
- Multi-Conductor Connections (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
- Cooling Or The Like Of Electrical Apparatus (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、マルチチツプパツケージに関し、特
に大型コンピユータや高周波通信装置などの高速
な信号処理を要求される電子機器に使用するのに
適するLSIパツケージ等のマルチチツプパツケー
ジに関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a multi-chip package, and in particular to an LSI package suitable for use in electronic devices that require high-speed signal processing such as large-sized computers and high-frequency communication devices. Regarding multi-chip packages such as
従来この種のマルチチツプパツケージは、装置
の処理能力の高速化を達成するため、LSIチツプ
の処理能力の高速化、およびLSIチツプ間相互の
配線距離の短縮のためのLSIチツプの実装密度の
増大と、それに伴う配線の高密度化にたいする努
力がなされて来た。
Conventionally, this type of multi-chip package has been designed to increase the processing capacity of LSI chips in order to achieve high-speed processing performance of equipment, and to increase the packaging density of LSI chips to shorten the interconnection distance between LSI chips. As a result, efforts have been made to increase the density of wiring.
一方、LSIチツプ、とくに論理処理用LSIの処
理能力の高速化のために、論理回路形式にECL
(エミツタ・カツプルド・ロジツク)もしくは、
CML(カレント・モード・ロジツク)を用いるこ
とが広く行なわれている。これらのECLあるい
はCMLという回路形式は電源に2種以上の電圧
を必要とするので、LSI搭載用配線基板には、接
地配線を含め、少なくとも3種の電源供給配線を
形成するとともに、これらの配線を外部の電源供
給配線と接続していた。 On the other hand, in order to speed up the processing performance of LSI chips, especially LSIs for logic processing, ECL was added to the logic circuit format.
(Emitsuta Katsupurud Rojitsuk) Or,
CML (current mode logic) is widely used. These ECL or CML circuit formats require two or more types of voltage for the power supply, so at least three types of power supply wiring, including a ground wiring, are formed on the LSI mounting wiring board, and these wiring was connected to the external power supply wiring.
上述した従来のマルチチツプパツケージはLSI
が必要とする電圧が5V以下と低い上に実装密度
も高くなつているので、これらの電源供給配線お
よび接地配線、更にはそれらの配線に接続する外
部接続用端子は極めて大電流を流すことのできる
ものとしなければならず、配線基板に占めるこれ
ら配線と端子の割合が増大し、信号配線領域を圧
迫すると共に信号配線の外部接続端子の配置領域
をも圧迫するという欠点があつた。さらに消費電
力の高いこれらのチツプを高密度に実装している
ことから、冷却は液冷方式にするのが普通であ
り、冷却液からの低温をチツプに伝えるための熱
伝導路が必要なのでこれらの熱伝導路が電源供給
配線や信号配線の外部接続端子の配置領域を圧迫
するという第2の欠点もあつた。
The conventional multi-chip package mentioned above is an LSI
The voltage required for these is as low as 5V or less, and the packaging density is also increasing, so these power supply wiring and grounding wiring, as well as the external connection terminals connected to these wiring, must be able to handle extremely large currents. However, the proportion of these wires and terminals on the wiring board increases, which has the disadvantage of not only compressing the signal wiring area but also compressing the area for arranging external connection terminals of the signal wiring. Furthermore, since these chips with high power consumption are mounted in a high density, it is common to use a liquid cooling method for cooling, and a heat conduction path is required to transfer the low temperature from the coolant to the chips. A second drawback was that the heat conduction path compressed the area where external connection terminals for power supply wiring and signal wiring were arranged.
本発明のマルチチツプパツケージは配線基板に
搭載されたLSIチツプに低温を伝えるための冷却
管路を複数の互いに電気的に独立した系統に分
け、それぞれの系統が異なる電圧の電源供給配線
として複数の電圧値の電源を配線基板内に供給す
ることを特徴としている。
The multi-chip package of the present invention divides the cooling pipe line for transmitting low temperature to the LSI chip mounted on the wiring board into a plurality of electrically independent systems, and each system serves as a power supply wiring with a different voltage. It is characterized by supplying power with a voltage value into the wiring board.
次に本発明の実施例について図面を参照して詳
細に説明する。
Next, embodiments of the present invention will be described in detail with reference to the drawings.
第1図は、本発明の第1の実施例を示す。第1
図において、本発明の第1の実施例はセラミツク
配線板10に搭載れたLSIチツプ20等に低温を
伝えるための冷却管路を有している。セラミツク
配線板10には信号配線の入出力ピン11と電極
12および給電用電極13とが設けられている。
このセラミツク配線板10に搭載されたLSIチツ
プ20はそのリード21が電極12に接着されて
いる。またLSIチツプ20は低温に保たれている
冷却液31が循環している冷却液配管30,3
3,34に近接していることで常に低温に保たれ
るようになつている。そして冷却液配管30,3
3,34は熱伝導効率の良い銅でできていて、そ
れぞれが電気的に独立した系統になつており冷却
液配管30,33,34はそれぞれ接地電位、−
3.3ボルトの電源電位、−0.3ボルトのリフアレン
ス電位に対応する電源配線をも兼ねている。冷却
液配管が電気の良導体である銅でできていること
により、これを電源配線として用いている。それ
ぞれの冷却液配管30,33,34とセラミツク
配線板10上の給電用電極13との間には銅箔3
2が半田付けされていてこの銅箔を介して、各電
源電位はセラミツク配線板10に伝えられる。 FIG. 1 shows a first embodiment of the invention. 1st
In the figure, the first embodiment of the present invention has a cooling conduit for transmitting low temperature to an LSI chip 20 etc. mounted on a ceramic wiring board 10. Ceramic wiring board 10 is provided with signal wiring input/output pins 11, electrodes 12, and power supply electrodes 13.
The LSI chip 20 mounted on the ceramic wiring board 10 has its leads 21 glued to the electrodes 12. In addition, the LSI chip 20 has coolant pipes 30 and 3 through which coolant 31 kept at a low temperature circulates.
3 and 34, the temperature is always kept low. and coolant pipes 30,3
3 and 34 are made of copper with good heat conduction efficiency, and each is an electrically independent system, and the coolant pipes 30, 33, and 34 are connected to ground potential, -
It also serves as the power supply wiring corresponding to the 3.3 volt power supply potential and -0.3 volt reference potential. Since the coolant piping is made of copper, which is a good conductor of electricity, it is used as the power supply wiring. A copper foil 3 is placed between each coolant pipe 30, 33, 34 and the power supply electrode 13 on the ceramic wiring board 10.
2 is soldered to the ceramic wiring board 10, and each power supply potential is transmitted to the ceramic wiring board 10 via this copper foil.
第2図は、本発明の第2の実施例を示す。第2
図において、第2の実施例のプリント配線板40
にはこれに実装されたLSIチツプキヤリア50を
介して、冷却液配管60,62,63,64によ
つて4種の電源電圧が供給されている。冷却液配
管60,63,64,65は銅でできており、こ
れらの配管の低温は一端がLSIチツプ55に接着
され、他の一端冷却液配管に接している、銅と鉄
から成るスタツド57を介してLSIチツプに伝え
られる。 FIG. 2 shows a second embodiment of the invention. Second
In the figure, a printed wiring board 40 of the second embodiment
Four types of power supply voltages are supplied through coolant pipes 60, 62, 63, and 64 via an LSI chip carrier 50 mounted thereon. The coolant pipes 60, 63, 64, and 65 are made of copper, and the low temperature of these pipes is maintained by a stud 57 made of copper and iron, which has one end glued to the LSI chip 55 and the other end in contact with the coolant pipe. It is transmitted to the LSI chip via.
LSIチツプ55のリード56はチツプキヤリア
50に設けられた電極51に装着されており、こ
の電極はさらに信号配線スルーホール53を経て
プリント配線板40内の配線に接続されている。 Leads 56 of the LSI chip 55 are attached to electrodes 51 provided on the chip carrier 50, and these electrodes are further connected to wiring within the printed wiring board 40 via signal wiring through holes 53.
冷却液配管60,62,63,64はそれぞ
れ、接地電位、−3.3ボルトの電源電位、−0.3ボル
トのリフアレンス電位、−2ボルトの抵抗終端電
位の電源配線を兼ねており、これらの配線より供
給される電圧は、銅でできているチツプキヤリア
ケース57を介してチツプキヤリア50上に設け
られた電極58に伝えられ、さらにチツプキヤリ
ア50に設けられた電源スルーホール53を経
て、プリント配線板40に伝えられる。チツプキ
ヤリア50とプリント配線板40との電気的接続
はチツプキヤリアに設けられたバンプ59とプリ
ント配線板40に設けられた電極41との半田付
けによつて行なわれる。従つて、チツプキヤリア
を介して、一旦プリント配線板に供給された各電
源電圧は、これらのバンプを経てそれぞれのチツ
プキヤリアに再び分配される。 The coolant pipes 60, 62, 63, and 64 each serve as power wiring for ground potential, -3.3 volt power supply potential, -0.3 volt reference potential, and -2 volt resistance terminal potential, and are supplied from these wirings. The voltage is transmitted to the electrode 58 provided on the chip carrier 50 via the chip carrier case 57 made of copper, and further transmitted to the printed wiring board 40 via the power supply through hole 53 provided in the chip carrier 50. It will be done. Electrical connection between the chip carrier 50 and the printed wiring board 40 is achieved by soldering bumps 59 provided on the chip carrier and electrodes 41 provided on the printed wiring board 40. Therefore, the power supply voltages once supplied to the printed wiring board via the chip carriers are again distributed to the respective chip carriers via these bumps.
以上説明したように、本発明は、LSIチツプの
冷却液配管に電源配線としての役割を持たせるこ
とにより、配線基板内に本来電源配線を設置すべ
き領域を無くすることができるので、従来電源供
給のために必要としていた領域をLSIチツプの実
装や信号配線その他の配線領域に振り向けること
により、実装密度の増大が図れるという効果があ
る。
As explained above, the present invention allows the coolant piping of an LSI chip to play the role of power supply wiring, thereby eliminating the area in the wiring board where power supply wiring should normally be installed. By allocating the area required for supply to LSI chip mounting, signal wiring, and other wiring areas, the packaging density can be increased.
第1図は、本発明の第1の実施例を示す縦断面
図、第2図は、本発明の第2の実施例を示す縦断
面図である。
10……セラミツク配線板、11……入出力ピ
ン、12,13,41,51,58……電極、2
0,55……LSIチツプ、21,56……LSIリ
ード、30,33,34,60,62,63,6
4……冷却液配管、31,61……冷却液、32
……銅箔、40……プリント配線板、50……チ
ツプキヤリア、52,53……スルーホール配
線、54……チツプキヤリアケース、57……熱
伝導スタツド、59……バンプ。
FIG. 1 is a longitudinal sectional view showing a first embodiment of the invention, and FIG. 2 is a longitudinal sectional view showing a second embodiment of the invention. 10... Ceramic wiring board, 11... Input/output pin, 12, 13, 41, 51, 58... Electrode, 2
0,55...LSI chip, 21,56...LSI lead, 30,33,34,60,62,63,6
4...Cooling liquid piping, 31, 61...Cooling liquid, 32
...Copper foil, 40...Printed wiring board, 50...Chip carrier, 52, 53...Through hole wiring, 54...Chip carrier case, 57...Heat conductive stud, 59...Bump.
Claims (1)
複数のLSIチツプキヤリアもしくはLSIチツプと、
これらのLSIチツプの発熱による温度上昇を抑え
るために個々のLSIチツプキヤリアもしくはLSI
チツプに接し、或いは近接して配置された冷却液
配管を有するマルチチツプパツケージにおいて、
これらの冷却液配管を独立した複数の配管系統に
わけ、それぞれの冷却液配管を導電材で構成し
て、前記それぞれの冷却液配管系統が、異なる電
圧の電源配線系統を兼ねて配線基板に複数の電源
電圧を供給するようにしたことを特徴とするマル
チチツプパツケージ。1. A wiring board, multiple LSI chip carriers or LSI chips mounted on this wiring board,
In order to suppress the temperature rise due to heat generated by these LSI chips, individual LSI chip carriers or LSI
In a multi-chip package having coolant piping arranged in contact with or close to the chip,
These coolant piping systems are divided into a plurality of independent piping systems, each of which is made of a conductive material, and each of the coolant piping systems is connected to a plurality of wiring boards on a wiring board to serve as a power supply wiring system for different voltages. A multi-chip package characterized by supplying a power supply voltage of .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62192860A JPS6437046A (en) | 1987-07-31 | 1987-07-31 | Multi-chip package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62192860A JPS6437046A (en) | 1987-07-31 | 1987-07-31 | Multi-chip package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6437046A JPS6437046A (en) | 1989-02-07 |
| JPH0575182B2 true JPH0575182B2 (en) | 1993-10-20 |
Family
ID=16298175
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62192860A Granted JPS6437046A (en) | 1987-07-31 | 1987-07-31 | Multi-chip package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6437046A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105118811A (en) * | 2015-07-27 | 2015-12-02 | 电子科技大学 | Temperature equalizing device adopting vapor chamber and microchannel for radiating multi-heat-source device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012174856A (en) * | 2011-02-21 | 2012-09-10 | Hitachi Cable Ltd | Heat sink and manufacturing method of the same |
-
1987
- 1987-07-31 JP JP62192860A patent/JPS6437046A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105118811A (en) * | 2015-07-27 | 2015-12-02 | 电子科技大学 | Temperature equalizing device adopting vapor chamber and microchannel for radiating multi-heat-source device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6437046A (en) | 1989-02-07 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |