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JPH0575186B2 - - Google Patents
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JPH0575186B2 - - Google Patents

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Publication number
JPH0575186B2
JPH0575186B2 JP62072053A JP7205387A JPH0575186B2 JP H0575186 B2 JPH0575186 B2 JP H0575186B2 JP 62072053 A JP62072053 A JP 62072053A JP 7205387 A JP7205387 A JP 7205387A JP H0575186 B2 JPH0575186 B2 JP H0575186B2
Authority
JP
Japan
Prior art keywords
gaas
layer
optical
integrated circuit
semi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62072053A
Other languages
Japanese (ja)
Other versions
JPS63237466A (en
Inventor
Tomoji Terakado
Yasumasa Imoto
Akira Suzuki
Tomohiro Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP62072053A priority Critical patent/JPS63237466A/en
Priority to CA000555687A priority patent/CA1274900A/en
Priority to US07/140,849 priority patent/US4829346A/en
Publication of JPS63237466A publication Critical patent/JPS63237466A/en
Publication of JPH0575186B2 publication Critical patent/JPH0575186B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351Substrate regions of field-effect devices
    • H10D62/357Substrate regions of field-effect devices of FETs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/80FETs having rectifying junction gate electrodes
    • H10D30/87FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10FINORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10Integrated devices
    • H10F39/103Integrated devices the at least one element covered by H10F30/00 having potential barriers, e.g. integrated devices comprising photodiodes or phototransistors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10HINORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H29/00Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/10Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901Materials
    • H10P14/2907Materials being Group IIIA-VA materials
    • H10P14/2909Phosphides
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202Materials thereof
    • H10P14/3214Materials thereof being Group IIIA-VA semiconductors
    • H10P14/3218Phosphides
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202Materials thereof
    • H10P14/3214Materials thereof being Group IIIA-VA semiconductors
    • H10P14/3221Arsenides
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34Deposited materials, e.g. layers
    • H10P14/3402Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3414Deposited materials, e.g. layers characterised by the chemical composition being group IIIA-VIA materials
    • H10P14/3418Phosphides
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34Deposited materials, e.g. layers
    • H10P14/3402Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3414Deposited materials, e.g. layers characterised by the chemical composition being group IIIA-VIA materials
    • H10P14/3421Arsenides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/02Structural details or components not essential to laser action
    • H01S5/026Monolithically integrated components, e.g. waveguides, monitoring photo-detectors, drivers
    • H01S5/0261Non-optical elements, e.g. laser driver components, heaters

Landscapes

  • Junction Field-Effect Transistors (AREA)
  • Semiconductor Lasers (AREA)

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、光電子集積回路の改良に関する。[Detailed description of the invention] (Industrial application field) The present invention relates to improvements in optoelectronic integrated circuits.

(従来技術とその問題点) 光通信技術の進歩に伴い、その適用分野は、基
幹伝送系から加入者系、LAN、データ・リンク
等のシステムへ急速に拡がりつつある。このよう
な、光システムの高度化に対応する為には光デバ
イスのより高性能化、高機能化が不可決である。
(Prior art and its problems) With the progress of optical communication technology, its application fields are rapidly expanding from backbone transmission systems to systems such as subscriber systems, LANs, and data links. In order to respond to such advancements in optical systems, it is imperative that optical devices have higher performance and functionality.

光電子集積回路は、これらの光シスムの核とな
るキー・デバイスの一つである。すなわち、低価
格・小型・高信頼・無調整化といつた集積による
基本的メリツトのみならず、高速化・高感度化と
いつた光デバイスの性能改善、さらには、光配
線、光交換といつた将来の光システムを支える高
機能・新機能デバイスの実現をねらいとする。
Optoelectronic integrated circuits are one of the key devices at the core of these optical systems. In other words, not only are the basic benefits of integration such as low cost, small size, high reliability, and no adjustment required, but also improvements in the performance of optical devices such as faster speeds and higher sensitivity, as well as improvements in optical interconnection, optical switching, and more. The aim is to realize highly functional and new functional devices that will support future optical systems.

InP系材料は、光デバイスの信頼性や光フアイ
バの低損失・低分散波長帯への整合性の点ですぐ
れ、光通信の分野においては、この材料を用いた
デバイスは既に実用化され、実績がある。
InP-based materials are excellent in terms of reliability of optical devices and compatibility with the low-loss and low-dispersion wavelength bands of optical fibers. In the field of optical communications, devices using this material have already been put into practical use and have a proven track record. There is.

InP系半導体は電子デバイスにおいて重要な良
好なシヨツト・コンタクトを得ることができない
為、MESFET(金属−半導体電界効果トランジス
タ)に代り、MSFET(金属−絶縁膜−半導体
FET)やJFET(接合ゲートFET)、HBT(ヘテロ
接合バイポーラトランジスタ)の研究開発がすす
められている。しかしながら、MISFETには、
その界面準位に起因する大きなドリフトの問題が
あり、又、JFETやHBTは、動作は安定である
ものの、構造やプロセスが複雑であり、光デバイ
スとの集積が困難である。一方、GaAs系半導体
においては良好なシヨツトキー・コンタクトを形
成できる為、MESFETを基本にした、FET集積
プロセス技術の進歩により、LSI級のICの実用化
も間近い。しかしながら、光デバイスの信頼性に
劣り、伝送能力が、光フアイバの伝送損失と波長
分散により大きな制限を受ける、といつた欠点が
あつた。
Because InP-based semiconductors cannot obtain good shot contact, which is important in electronic devices, MSFETs (metal-insulator-semiconductor field effect transistors) are used instead of MESFETs (metal-semiconductor field effect transistors).
Research and development is progressing on FETs (FETs), JFETs (junction gate FETs), and HBTs (heterojunction bipolar transistors). However, MISFET has
There is a problem of large drift caused by the interface states, and although JFETs and HBTs are stable in operation, their structures and processes are complex, making it difficult to integrate them with optical devices. On the other hand, since GaAs-based semiconductors can form good shot-key contacts, advances in FET integration process technology based on MESFETs will soon bring LSI-class ICs to practical use. However, the reliability of the optical device is poor, and the transmission capacity is severely limited by the transmission loss and chromatic dispersion of the optical fiber.

これらの、InP系材料、GaAs系材料の相反す
る欠点を補い、光デバイスとしてのInP系材料、
電子デバイスとしてのGaAs系材料という最適な
組合せを、GaAs系と、InP系の複合材料を用い
た光電子集積回路により実現しようとする検討が
なされている。(M.Razeghi、Appl.Phys.Lett、
vol.49、pp.215、1986)これは、半絶縁性GaAs
基板上に、減圧MOVPEによる歪ヘテロエピタキ
シーを用いてGaInAsを成長し、GaInAsから成
る受光素子とGaAsから成るMESFETをモノリ
シツク集積したものである。
By compensating for these contradictory drawbacks of InP-based materials and GaAs-based materials, InP-based materials and GaAs-based materials can be used as optical devices.
Studies are underway to realize the optimal combination of GaAs-based materials for electronic devices by optoelectronic integrated circuits using composite materials of GaAs-based and InP-based materials. (M.Razeghi, Appl.Phys.Lett,
vol.49, pp.215, 1986) This is a semi-insulating GaAs
GaInAs is grown on a substrate using strained heteroepitaxy using low-pressure MOVPE, and a photodetector made of GaInAs and a MESFET made of GaAs are monolithically integrated.

しかしながら、この従来例においては、少数キ
ヤリア・デバイスである光デバイスを半絶縁性
GaAs基板上に歪ヘテロエピタキシーにより成長
して作成する為、格子不整による転位の影響を大
きく受け、通信用光デバイスとして十分な素子特
性が得られないばかりでなく、光デバイスの素子
信頼性が著しく低いといつた欠点を有していた。
However, in this conventional example, optical devices, which are minority carrier devices, are semi-insulating.
Since it is grown on a GaAs substrate by strained heteroepitaxy, it is greatly affected by dislocations due to lattice misalignment, which not only makes it impossible to obtain sufficient device characteristics as an optical communication device, but also significantly reduces the device reliability of the optical device. It had the disadvantage of being low.

本発明の目的は、これらの欠点を除去し、高性
能かつ高信頼な光電子集積回路を提供することに
ある。
An object of the present invention is to eliminate these drawbacks and provide a high performance and highly reliable optoelectronic integrated circuit.

(問題点を解決するための手段) 前述の問題点を解決し、上記目的を達成するた
めに、本発明が提供する光電子集積回路は、半絶
縁性InP基板上に、InGaAs又はInGaAsPを含む
InP系半導体から成る光デバイスと、前記半絶縁
性InP基板上に、GaAs又はAlGaAsから成る歪バ
ツフア層をはさんで、AlGaAsを含むGaAs系半
導体から成る電界効果トランジスタがモノリシツ
クに集積されていることを特徴とする。
(Means for Solving the Problems) In order to solve the above problems and achieve the above objects, an optoelectronic integrated circuit provided by the present invention includes InGaAs or InGaAsP on a semi-insulating InP substrate.
An optical device made of an InP-based semiconductor and a field effect transistor made of a GaAs-based semiconductor including AlGaAs are monolithically integrated on the semi-insulating InP substrate with a strained buffer layer made of GaAs or AlGaAs sandwiched therebetween. It is characterized by

(作用) 半絶縁性InP基板上に、InPと格子整合のとれ
るInGaAs又はInGaAsPを含むInP系半導体を構
成することにより、高性能かつ高信頼性の光デバ
イスが得られる。
(Function) By constructing an InP-based semiconductor containing InGaAs or InGaAsP that is lattice-matched to InP on a semi-insulating InP substrate, a high-performance and highly reliable optical device can be obtained.

又、半絶縁性InP基板上に、GaAs又はAlGaAs
からなる歪バツフア層をはさんで、AlGaAsを含
むGaAs系半導体からなる電界効果トランジスタ
を構成することによつて、基板とチヤネル層の間
の格子整合の影響をほとんど受けずに電子デバイ
スとして必要十分な性能と信頼性が得られる。従
つて、光デバイスとしてのInP系材料、電子デバ
イスとしてのGaAs系材料という、光電子集積回
路として最適な組合せをデバイスの性能、信頼性
を確保しつつ実現することが可能となる。
In addition, GaAs or AlGaAs is deposited on a semi-insulating InP substrate.
By constructing a field effect transistor made of GaAs-based semiconductors including AlGaAs with a strain buffer layer made of performance and reliability. Therefore, it is possible to realize an optimal combination of an InP-based material for an optical device and a GaAs-based material for an electronic device as an optoelectronic integrated circuit while ensuring the performance and reliability of the device.

(実施例) 次に図面を参照して本発明の実施例を詳細に説
明する。第1図は第一の実施例の光電子集積回路
の断面図である。図のようにこの光電子集積回路
は半絶縁性InP基板1上に層厚が1μm、キヤリア
濃度が1×1018cm-3のn型In0.87Ga0.13As0.29P0.71
よりなるレーザ・コンタクト層2と発振波長1.3μ
mのInP及びInGaAsPよりなるメサ型埋め込みレ
ーザ3、そして層厚が0.5μmのアンドープn型
GaAsから成る歪バツフア層4、層厚が0.2μmキ
ヤリア濃度が1×1017cm-3のGaAsよりなる能動
層5、及び厚さ0.3μmのAlのゲート電極6をゲー
ト長1μmの電界効果トランジスタ7よりなる。
尚、ドレイン電極8、ソース電極9、レーザのn
電極10はAuGeNi、レーザのp電極11は
AuZn、配線12はTi/Auから成る。
(Example) Next, an example of the present invention will be described in detail with reference to the drawings. FIG. 1 is a sectional view of the optoelectronic integrated circuit of the first embodiment. As shown in the figure, this optoelectronic integrated circuit is made of n-type In 0.87 Ga 0.13 As 0.29 P 0.71 with a layer thickness of 1 μm and a carrier concentration of 1×10 18 cm -3 on a semi-insulating InP substrate 1.
Laser contact layer 2 and oscillation wavelength of 1.3μ
mesa-type buried laser 3 made of InP and InGaAsP with a layer thickness of 0.5 μm, and an undoped n-type laser with a layer thickness of 0.5 μm.
A field effect transistor with a gate length of 1 μm includes a strained buffer layer 4 made of GaAs, an active layer 5 made of GaAs with a layer thickness of 0.2 μm and a carrier concentration of 1×10 17 cm −3 , and a gate electrode 6 of Al with a thickness of 0.3 μm. Consists of 7.
Note that the drain electrode 8, the source electrode 9, and the n of the laser
The electrode 10 is AuGeNi, and the p-electrode 11 of the laser is
AuZn and the wiring 12 are made of Ti/Au.

第2図−a〜cは本実施例の光電子集積回路の
製作工程図である。まず5μm程度の段差を持つ
半絶縁性InP基板1上に液相成長法又は気相成長
法によりレーザ・コンタクト層2と埋め込み型の
レーザ層13を形成する(第2図−a)。次にレ
ーザ層13をメサストライプ化し、レーザコンタ
クト層2をメサエツチし、半絶縁性InP基板1を
露出させ、レーザメサ部14にSiO2よりなるマ
スク15を施し分子線エピタキシー又はMOVPE
法により歪バツフア層4、能動層5を形成する
(第2図−b)。次にマスク15上の能動層5、歪
バツフア層4を除去し、更にメサエツチにより電
界効果トランジスタ7の能動層を形成する(第2
図−c)。次に各電極及び配線を形成し、本実施
例の光電子集積回路が完成する(第1図)。
FIGS. 2-a to 2-c are manufacturing process diagrams of the optoelectronic integrated circuit of this embodiment. First, a laser contact layer 2 and a buried laser layer 13 are formed by liquid phase epitaxy or vapor phase epitaxy on a semi-insulating InP substrate 1 having a step difference of about 5 μm (FIG. 2-a). Next, the laser layer 13 is formed into a mesa stripe, the laser contact layer 2 is mesa-etched, the semi-insulating InP substrate 1 is exposed, and a mask 15 made of SiO 2 is applied to the laser mesa portion 14, followed by molecular beam epitaxy or MOVPE.
A strain buffer layer 4 and an active layer 5 are formed by the method (FIG. 2-b). Next, the active layer 5 and strain buffer layer 4 on the mask 15 are removed, and the active layer of the field effect transistor 7 is formed by mesa etching (second
Figure-c). Next, each electrode and wiring are formed, and the optoelectronic integrated circuit of this example is completed (FIG. 1).

第一の実施例は、メサ型埋め込みレーザ3と電
界効果トランジスタ7が半絶縁性InP基板1上に
モノリシツクに集積された光送信用の光電子集積
回路として動作する。
The first embodiment operates as an optoelectronic integrated circuit for optical transmission in which a mesa-type buried laser 3 and a field effect transistor 7 are monolithically integrated on a semi-insulating InP substrate 1.

第3図は第二の実施例の光電子集積回路の断面
図である。この光電子集積回路は半絶縁性InP基
板1上に層厚が1μm、キヤリア濃度が1×1018cm
-3のn型In0.87Ga0.13As0.29P0.71よりなるフオトダ
イオードコンタクト層17をはさみバンドギヤツ
プエネルギー波長1.67μmのIn0.47Ga0.53Asよりな
る光吸収層19を含むPINフオトダイオード1
6、そして層厚が、0.5μmのアンドープn型
GaAsから成る歪バツフアー層4をはさみ、層厚
が0.2μmキヤリア濃度が1×1017のGaAsよりな
る能動層5、及び厚さ0.3μmのAlのゲート電極6
から成るゲート長1μmの電界効果トランジスタ
7よりなる。
FIG. 3 is a sectional view of the optoelectronic integrated circuit of the second embodiment. This optoelectronic integrated circuit is formed on a semi-insulating InP substrate 1 with a layer thickness of 1 μm and a carrier concentration of 1×10 18 cm.
-3 n-type In 0.87 Ga 0.13 As 0.29 P 0.71 photodiode contact layer 17 sandwiching the bandgap energy wavelength of 1.67 μm In 0.47 Ga 0.53 As light absorption layer 19 made of In 0.47 Ga 0.53 As PIN photodiode 1
6, and an undoped n-type layer with a layer thickness of 0.5 μm.
A strain buffer layer 4 made of GaAs is sandwiched between the active layer 5 made of GaAs with a layer thickness of 0.2 μm and a carrier concentration of 1×10 17 , and a gate electrode 6 made of Al with a thickness of 0.3 μm.
The field effect transistor 7 has a gate length of 1 μm.

本実施例の製作工程は第1の実施例に準ずる。
まず3μm程度の段差を持つ半絶縁性InP基板1上
に液相成長法又は気相成長法によりn型In0.87
Ga0.13As0.29P0.71よりなるフオト・ダイオード・
コンタクト層17(厚さ1.0μm、キヤリア濃度が
1×1018cm-3)、n型InPよりなるフオト・ダイオ
ード・バツフアー層18(厚さ0.5μm、キヤリア
濃度2×1015cm-3)、n型In0.47Ga0.53Asよりなる
光吸収層19(厚さ1.0μm、キヤリア濃度2×
1015cm-3)、n型InPよりなるウインドウ層20
(厚さ1.0μm、キヤリア濃度2×1015cm-3)を順次
形成する。次にPINフオトダイオード部16を残
し、フオトダイオードコンタクト層17、フオト
ダイオードバツフア層18、光吸収層19、ウイ
ンドウ層20をメサエツチし、半絶縁性InP基板
1を露出させる。PINホトダイオード部16に
SiO2によりなるマスクを施しMOVPE法又は分
子線成長法を用いて、GaAsよりなる歪バツフア
層4(厚さ0.5μmノンドープ)、n型GaAsよりな
る能動層5(厚さ0.2μm、キヤリア濃度1×1017
cm-3)を形成する。次に、PINフオトダイオード
部16上の能動層4、バツフア層4を除去し、更
にメサエツチにより電界効果トランジスタ7の能
動層を形成する。次にSiO2よりなるマスクを用
い選択的に亜鉛を拡散し、p形反転領域21を形
成し、更にゲート電極6、ドレイン電極8、ソー
ス電極9、n電極10、p電極11、配線12を
形成し、第二の実施例の光電子集積回路が完成す
る。
The manufacturing process of this embodiment is similar to that of the first embodiment.
First, n-type In 0.87 was deposited on a semi-insulating InP substrate 1 with a step height of about 3 μm by liquid phase growth or vapor phase growth.
Photo diode consisting of Ga 0.13 As 0.29 P 0.71
Contact layer 17 (thickness 1.0 μm, carrier concentration 1×10 18 cm −3 ), photo diode buffer layer 18 made of n-type InP (thickness 0.5 μm, carrier concentration 2×10 15 cm −3 ), Light absorption layer 19 made of n-type In 0.47 Ga 0.53 As (thickness 1.0 μm, carrier concentration 2×
10 15 cm -3 ), window layer 20 made of n-type InP
(thickness: 1.0 μm, carrier concentration: 2×10 15 cm -3 ) are sequentially formed. Next, leaving the PIN photodiode portion 16, the photodiode contact layer 17, photodiode buffer layer 18, light absorption layer 19, and window layer 20 are mesa-etched to expose the semi-insulating InP substrate 1. To the PIN photodiode section 16
A strain buffer layer 4 made of GaAs (thickness 0.5 μm, non-doped) and an active layer 5 made of n-type GaAs (thickness 0.2 μm, carrier concentration 1 ×10 17
cm -3 ). Next, the active layer 4 and buffer layer 4 on the PIN photodiode section 16 are removed, and then the active layer of the field effect transistor 7 is formed by mesa etching. Next, zinc is selectively diffused using a mask made of SiO 2 to form a p-type inversion region 21, and a gate electrode 6, a drain electrode 8, a source electrode 9, an n-electrode 10, a p-electrode 11, and a wiring 12 are formed. The optoelectronic integrated circuit of the second embodiment is completed.

第二の実施例は、PINフオトダイオード16と
電界効果トランジスタ7が半絶縁性InP基板1上
にモノリシツクに集積された光受信用の光電子集
積回路として動作する。
The second embodiment operates as an opto-electronic integrated circuit for receiving light, in which a PIN photodiode 16 and a field effect transistor 7 are monolithically integrated on a semi-insulating InP substrate 1.

尚上述の実施例において電界効果トランジスタ
のゲート電極はAlに限らずシヨツトキー接合が
とれればいかなるものでも良く、又、その能動層
の厚さ、キヤリア濃度、組成は光電子集積回路用
の電子デバイスとして最適化されていればいかな
るものであつても良く、さらに、AlGaAs混晶を
含むヘテロ構造の二次元電子ガスを利用する構造
であつてもよい。また光デバイスは発光ダイオー
ドやアバランシエ・フオト・ダイオード、さらに
は、光双安定素子や光アンプ、光スイツチなどの
光機能素子であつてもよい。電子回路もGaAs電
界効果トランジスタのみならず、ダイオード、抵
抗を含んでもよく、その集積回路規模も、さらに
大きなものであつてもよい。
In the above-mentioned embodiment, the gate electrode of the field effect transistor is not limited to Al, but any material that can form a Schottky junction may be used, and the thickness, carrier concentration, and composition of the active layer are optimal for use as an electronic device for optoelectronic integrated circuits. It may be of any structure as long as it has a heterostructure containing an AlGaAs mixed crystal, and may also be a structure that utilizes a two-dimensional electron gas having a heterostructure containing an AlGaAs mixed crystal. Further, the optical device may be a light emitting diode, an avalanche photo diode, or an optical functional element such as an optical bistable element, an optical amplifier, or an optical switch. The electronic circuit may also include not only GaAs field effect transistors but also diodes and resistors, and the scale of the integrated circuit may be even larger.

(発明の効果) 以上説明したように本発明によれば、光デバイ
スを半絶縁性InP基板上に、格子整合のとれた
InGaAsP又は、InGaAsを含むInP系半導体で構
成し、一方、AlGaAsを含むGaAs系半導体から
成る電界効果トランジスタをGaAs系半導体から
成る歪バツフア層を挾んで半導体性InP基板上に
構成することにより高性能かつ高信頼な光電子集
積回路が得られる。
(Effects of the Invention) As explained above, according to the present invention, an optical device is formed on a semi-insulating InP substrate with lattice matching.
A field-effect transistor made of InGaAsP or an InP-based semiconductor containing InGaAs, and a field-effect transistor made of a GaAs-based semiconductor containing AlGaAs sandwiched between a strained buffer layer made of a GaAs-based semiconductor on a semiconducting InP substrate provides high performance. In addition, a highly reliable optoelectronic integrated circuit can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の第一の実施例の光電子集積回
路の断面構造図、第2図a〜cはその製作工程図
である。第3図は本発明の第二の実施例の光電子
集積回路の断面構造図である。図中で1は半絶縁
性InP基板、2はレーザ・コンタクト層、3はメ
サ型埋め込みレーザ、4は歪バツフア層、5は能
動層、6はゲート電極、7は電界効果トランジス
タ、8はドレイン電極、9はソース電極、10は
n電極、11はp電極、12は配線、13はレー
ザ層、14はレーザメサ部、15はマスク、16
はPINフオトダイオード、17はフオトダイオー
ド・コンタクト層、18はフオトダイオード・バ
ツフア層、19は光吸収層、20はウインドウ
層、21はp形反転領域である。
FIG. 1 is a cross-sectional structural diagram of an optoelectronic integrated circuit according to a first embodiment of the present invention, and FIGS. 2 a to 2 c are diagrams of its manufacturing process. FIG. 3 is a cross-sectional structural diagram of an optoelectronic integrated circuit according to a second embodiment of the present invention. In the figure, 1 is a semi-insulating InP substrate, 2 is a laser contact layer, 3 is a mesa-type buried laser, 4 is a strain buffer layer, 5 is an active layer, 6 is a gate electrode, 7 is a field effect transistor, and 8 is a drain Electrode, 9 is a source electrode, 10 is an n electrode, 11 is a p electrode, 12 is a wiring, 13 is a laser layer, 14 is a laser mesa portion, 15 is a mask, 16
is a PIN photodiode, 17 is a photodiode contact layer, 18 is a photodiode buffer layer, 19 is a light absorption layer, 20 is a window layer, and 21 is a p-type inversion region.

Claims (1)

【特許請求の範囲】[Claims] 1 半絶縁性InP基板上に、InGaAs又は
InGaAsPを含むInP系半導体から成る光デバイス
と、前記半絶縁性InP基板上に、GaAs又は
AlGaAsから成る歪バツフア層をはさんで、
AlGaAsを含むGaAs系半導体から成る電界効果
トランジスタが、モノリシツクに集積されている
ことを特徴とする光電子集積回路。
1 InGaAs or
An optical device made of an InP-based semiconductor containing InGaAsP, and a GaAs or
With a strained buffer layer made of AlGaAs in between,
An optoelectronic integrated circuit characterized by monolithically integrating field effect transistors made of GaAs-based semiconductors including AlGaAs.
JP62072053A 1987-01-05 1987-03-25 Optoelectronic integrated circuit Granted JPS63237466A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP62072053A JPS63237466A (en) 1987-03-25 1987-03-25 Optoelectronic integrated circuit
CA000555687A CA1274900A (en) 1987-01-05 1987-12-31 Field-effect transistor and the same associated with an optical semiconductor device
US07/140,849 US4829346A (en) 1987-01-05 1988-01-05 Field-effect transistor and the same associated with an optical semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62072053A JPS63237466A (en) 1987-03-25 1987-03-25 Optoelectronic integrated circuit

Publications (2)

Publication Number Publication Date
JPS63237466A JPS63237466A (en) 1988-10-03
JPH0575186B2 true JPH0575186B2 (en) 1993-10-20

Family

ID=13478255

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62072053A Granted JPS63237466A (en) 1987-01-05 1987-03-25 Optoelectronic integrated circuit

Country Status (1)

Country Link
JP (1) JPS63237466A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7364997B2 (en) * 2005-07-07 2008-04-29 Micron Technology, Inc. Methods of forming integrated circuitry and methods of forming local interconnects

Also Published As

Publication number Publication date
JPS63237466A (en) 1988-10-03

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