JPH0576176B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device used in an MIS type integrated circuit having high speed and high degree of integration.

[Technical background of the invention and its problems]

In recent years, the degree of integration of integrated circuits has increased, and the so-called super
LSI is now being researched and developed. by the way,
In order to increase the degree of integration, it is necessary to reduce the dimensions of the elements that make up the circuit. It is known that as the dimensions of MOS transistors become smaller, and in particular the channel length becomes shorter, a so-called short channel effect occurs, which significantly lowers the threshold voltage of the transistor. This is because the charge in the channel region is greatly influenced not only by the gate voltage but also by the drain voltage, mainly because a depletion layer caused by the drain voltage invades the channel region. Methods to prevent this short channel effect include implanting ions into the channel region to increase the substrate concentration in this area and suppressing the invasion of the depletion layer, and thinning the gate oxide film layer to increase the influence of the electric field of the gate electrode. There are ways to do this. Furthermore, if the diffusion depth (Xj) of the source/drain is made shallow, the invasion of the depletion layer into the channel region can be suppressed and the short channel effect can be prevented. Since the source and drain are formed at the same time, or because the width of the wiring region is narrowed due to proportional reduction, there is a problem that the layer resistance of the wiring region due to the source and drain and the diffusion layer increases, significantly reducing the operating speed of the circuit. Furthermore, if such a shallow PN junction is formed to suppress the extension of the depletion layer in the channel direction, the reverse withstand voltage of the PN junction decreases due to so-called surface breakdown, making it impossible to increase the power supply voltage. On the other hand, a similar problem occurs with respect to the gate electrode. That is, the resistance of the wiring made of the gate electrode material limits the operating speed of the circuit. For this reason, a method of selectively depositing a tungsten film on the surface of the gate electrode has been attempted, as shown in Electro Chemical Society (ECS) 1981 Fall Meeting Abstract No. 381. However, since this method forms a W film only on the polycrystalline silicon gate, it is not possible to reduce the resistance of the source/drain diffusion layer, and it is not effective in increasing the resistance of the diffusion layer due to miniaturization of the MOS transistor. do not have.

Recently, as a solution to the above problem,
Various proposals have been made. For example, International Device Meeting (IEDM) 1981
Technical Digest (IEDM81-647)
As shown in , at least the side walls of the gate electrode material are covered with an insulator, a metal film is deposited on the entire surface, and the source and drain are connected to the side of the source and drain through a reaction between the metal film and silicon. Metal silicide is placed in a self-aligned manner with the gate without mask alignment on the wiring area and the gate electrode surface, and then the remaining unreacted metal film is removed to achieve proportional integration without compromising the integration density. A method has been proposed that suppresses the short channel effect during reduction and at the same time enables high motion operation and high reverse voltage resistance. However, when installing metal silicide using this method,
It was discovered that the following new problems occurred. This will be explained using FIG. That is,
Before the process of forming the diffusion layers 5a, 5b such as source/drain by ion implantation method or in the thermal process for activation after ion implantation, the diffusion layers 5a and 5b are
A thin oxide film 6, etc., grows on the layers a, 5b and the gate electrode 3 (FIG. 1a). The growth rate of this oxide film 6 on the surface of polycrystalline silicon, which is the gate electrode material, is higher than the growth rate on the surface of the silicon substrate 1. On the other hand, when forming metal silicide, if a slight oxide layer is present between the metal film and silicon, the silicide formation becomes abnormal or does not progress. Therefore, in order to simultaneously form silicide on the diffusion layers 5a and 5b on the silicon substrate 1 and on the gate electrode 3, a pretreatment process for removing such oxide layer 6 etc. is essential before the metal film deposition process. becomes. Moreover, in this pretreatment step, the oxide film 6 and the like on the polycrystalline silicon (gate electrode 3) must be completely removed. However, if the oxide film 6 is removed too much in this pretreatment step, the diffusion layers 5a,
The field oxide film 4 recedes at the edge 5b, and the depth of the junction at the edge 7 becomes shallow as shown in FIG. In a severe case, a short circuit occurs due to the silicide 8 of the edge portion 7, as shown in FIG. 1c.

On the other hand, the present inventors have previously reported that
We are investigating a method for selectively depositing metal films using the CVD method. However, this method also has drawbacks such as short circuits for the same reasons as mentioned above. That is, in this method, the above-mentioned FIG.
Next to the state shown in FIG. 2, a metal film 9 is deposited using the CVD method as shown in FIG. In this case, the field oxide film 4 is etched and retreated at the edge portions 7 of the diffusion layers 5a and 5b, and the remaining thickness of the oxide film 6 on the sidewalls of the gate electrode 3 is reduced. This causes problems in that short circuits occur at the edge portion 7 and poor insulation between the diffusion layer and the gate is likely to occur.

[Purpose of the invention]

An object of the present invention is to prevent the formation of an oxide film on a gate electrode made of polycrystalline silicon due to a thermal process, and to reduce the resistance of the gate electrode, source/drain region, and diffusion wiring region. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can be easily measured, can reliably prevent the occurrence of short circuits between wiring layers, and can further contribute to improving the reliability of interconnections in highly integrated circuits.

[Summary of the invention]

The gist of the present invention is to leave an insulator on the sidewalls of a polycrystalline silicon gate electrode in a self-aligned manner, and
The purpose is to form an oxidation prevention film on the gate electrode to prevent oxide film growth on the gate electrode due to a thermal process.

That is, the present invention provides a method for manufacturing a semiconductor device in which a source/drain region of an MIS transistor and a diffusion wiring region connected to at least one of these are provided in a silicon substrate. After forming a gate electrode and an oxidation prevention film, a silicon oxide film is deposited on the entire surface of the silicon substrate using a vapor phase growth method, and then the silicon oxide film is etched on the entire surface using a directional etching method. The sidewalls of the gate electrode are covered with a silicon oxide film in self-alignment with the electrode, the anti-oxidation film is then removed, and a conductive film is then self-aligned over the gate electrode, source/drain regions and diffusion wiring regions. This method allows for selective formation.

〔Effect of the invention〕

According to the present invention, the growth of an oxide film due to a thermal process etc. on the surface of a polycrystalline silicon gate and the surface of a polycrystalline silicon wiring connected to the side thereof can be suppressed, and the thickness of the oxide film removed in the pre-process of metal film deposition can be reduced. can be reduced. Furthermore, it is possible to reduce the receding of the field oxide film due to etching required for removal and the reduction due to etching of the silicon oxide film left on the gate sidewalls to ensure insulation between the polycrystalline silicon gate and the source/drain diffusion layer. , the adverse effect on the junction at the edge of the source/drain diffusion layer and the insulation defect due to the metal deposited between the gate and diffusion layer can be reduced, and reliability can be further improved.

[Embodiments of the invention]

Figures 3a to 3h relate to one embodiment of the present invention.
FIG. 3 is a cross-sectional view showing the manufacturing process of a MOS type semiconductor device.
First, as shown in Figure 3a, 50
A field oxide film 12, a gate oxide film 13, and a phosphorus-doped polycrystalline silicon 14 are sequentially formed on a p-type silicon substrate 11 of [Ωcm], and then a silicon oxide film 15 is formed on the polycrystalline silicon 14 with a thickness of 150 [Å]. Silicon nitride film (antioxidation film) 1
6 is formed to a thickness of 0.2 [μm] using the well-known CVD method. Next, a desired resist pattern is formed using a light exposure technique, and using this resist pattern as a mask, the silicon nitride film 16 is selectively etched as shown in FIG. etching. Thereby, the gate electrode 14 is formed. Next, after removing the exposed gate oxide film 13, a 200 Å thick silicon oxide film 17 is formed on the Si substrate 11 using, for example, a thermal oxidation method, as shown in FIG. 3B. Next, for example, by implanting 1×10 ¹⁴ As ions at 40 [keV], the source/drain regions 18a, 1
8b and a wiring region 19 are formed. Next, as shown in FIG. 3c, a SiO ₂ film 20 is grown by vapor phase growth.
Approximately 0.3 [μm] is formed on the entire surface. Furthermore, the silicon oxide film 20 is etched by about 0.3 [μm] using a reactive ion etching method or a sputter etching method with directional etching.
As shown in FIG. 3d, a silicon oxide film 20 is formed only on both sides of the polycrystalline silicon gate so as to cover its sidewalls.
leave. Next, after cleaning the surface, approximately 100
After forming a SiO ₂ film 21 of [Å] on the exposed surface of Si, it is annealed for 20 minutes at 1000 [° C.] in an N ₂ atmosphere.
Next, as shown in FIG. 3e, the silicon nitride film 16 on the polycrystalline silicon gate electrode 14 is removed, and the source/drain regions 18a, 18b, wiring region 19 and gate polycrystalline silicon 1
The SiO ₂ films 15 and 21 on the surface of the wafer 4 are removed, and then a metal film, for example tungsten, which is a high melting point metal, is vacuum-deposited to a thickness of about 400 Å over the entire surface of the wafer, as shown in FIG. This wafer is then processed into, for example, 800
When annealing is performed in an _N2 atmosphere at [°C] for about 1 hour, a silicide formation reaction occurs selectively only in the contact area between tungsten and silicon, and a silicide formation reaction occurs on the surface of the source/drain region, the wiring region, and the surface of the polycrystalline silicon gate 14. As shown in FIG. 3g, a tungsten silicide film 23 (WSi ₂ ) is formed.
Here, the unreacted tungsten film 22 is removed by acid treatment as shown in FIG. 3h. Thereafter, a PSG film, contact hole Al wiring, etc. are formed according to the normal MOS transistor manufacturing process. Finally, a PSG film was installed as a protective film, and holes for bonding were made.
The MOS transistor is completed. FIG. 4 shows this plan view. A cross section taken along arrow A-A in the figure is shown in FIG. 3h. This transistor is used, for example, as a switching transistor, and when a voltage of, for example, 5 [V] is applied to the gate and a voltage of, for example, 5 [V] is input to the source from an inverter (not shown), the drain becomes 5V. −V _th (threshold) is output and input to the gates of other transistors through the diffusion wiring layer.

The MOS transistor made by the above method has a thickness of about 1100 Å in the source, drain and gate parts.
Since tungsten silicide is formed, Ps of the source/drain part is approximately 7 [Ω/Ω],
The gate part Ps has an extremely low resistance of approximately 5 [Ω/R], and compared to a diffusion layer made by the conventional method that does not use silicide (Ps 50Ω/R), the resistance of the diffusion layer wiring extending from the drain (or source) is very low. Signal delay time can be reduced by more than 80%. Both the layer resistance of the drain (or source) and the diffusion layer wiring are useful for delay, but generally the length of the wiring region is longer than the dimension of the source or drain connected to it, and therefore the resistance is higher than that of the source or drain, so the wiring The effect of forming metal silicide on the surface of the region is great. The wiring region may be provided for both the drain and the source. In addition, with this method, the dose of ion implantation for source/drain formation can be determined regardless of the resistance value of the diffusion layer, and in this case, it is 1×10 ¹⁴ [cm ^-2 ] and 1×10 ¹⁵ in the conventional method. ~1×
It becomes possible to use a dose amount that is 1/10 compared to 10 ¹⁶ [cm ^-2 ], and the concentration of As at the gate end can be lowered. Therefore, the drain depletion layer extends not only to the substrate side (P region) but also to the As ion implanted layer side (N region), that is, inside the PN junction. As a result, the width of the depletion layer near the drain was expanded, making it possible to raise the surface breakdown voltage by about 4 to 5 V compared to the conventional method. or,
The source/drain depletion layer capacitance can also be reduced by approximately 40%, resulting in a device operating speed of approximately 40%.
I was able to improve it by 10 [%] to 30 [%]. In addition, the PN junction surface, including the silicide layer formed in this case, is about 0.2 [μm] from the main surface of the silicon substrate.
(Conventionally, the depth was approximately 0.4 μm), making it possible to extremely effectively prevent the short channel effect.

In addition, the shape left behind by CVD SiO ₂ formed between the polysilicon gate and the diffusion layer extends upward by an amount equivalent to the SiN film used as the oxidation-resistant film, which reduces the incidence of silicide short circuits between the gate diffusion layer. It also has the advantages of

FIG. 5 is a sectional view for explaining another embodiment of the present invention. This embodiment differs from the previously described embodiments in that instead of forming the tungsten silicide film, a metal film is selectively formed by CVD. That is, the steps up to the state shown in FIG.
A thickness of 1500 [Å] is deposited by CVD using a mixed gas of WF ₆ gas and H ₂ gas. As a result, the tungsten film 25 is selectively formed only on the active region, that is, on the gate electrode 13, the sources/drains 18a and 18b, and the wiring region 19, and is not formed on the silicon oxide film 20. Thereafter, a MOS transistor is formed by forming contact holes, Al wiring, etc. in the same manner as in the previous embodiment.

Thus, according to this embodiment, not only the same effect as the previous embodiment is obtained, but also the advantage that the process is simplified.

Note that the present invention is not limited to the embodiments described above. For example, in integrated circuits such as dynamic RAM, polysilicon wiring is used for bit lines or word lines. The Ps of polysilicon with a film thickness of 0.3 [μm] is approximately 15 [Ω/ro] even if it is heavily doped with phosphorus. When tungsten silicide of about 1100 [Å] is formed on polysilicon, a resistance of about [Ω/Ω] is obtained for Ps, which is 1/3 that of polysilicon wiring made by the conventional method that does not use silicide. can be reduced.

Further, in the embodiment, only thermal annealing is used as the silicide formation reaction, but this may be performed by, for example, irradiating with a laser after depositing the metal layer. In this case, for example
When a CW-Ar laser is used, similar results can be obtained by performing a single laser scan with an output of about 10 [W], which is convenient because there is no need to increase the wafer processing temperature. It is also possible to selectively irradiate only predetermined locations with the laser beam. The same thing can be done by irradiation with a CW electron beam. Also, the formation of silicide is 400 [Å]
The tungsten layer may be deposited by ion-implanting a tungsten layer, for example, Si, into the interface between W and silicon. In this case, the ions may be As, Xe, Ar, etc. in addition to Si. In the embodiment, only the case where p-type silicon is used as the semiconductor substrate has been described, but this is not limited to P-type, but may also be N-type or a case where both N and P are on one substrate, such as CMOS. It may also be polysilicon or single silicon or SOS recrystallized on an amorphous material. In addition, as for the metal layer, although the case of W has been described, other materials such as Pt, Pd, Mi,
Needless to say, Mo, Nd, Ta, or anything else that achieves alloying may be used. Also, the third
The step of forming the PN junction shown in the figure may also be performed by forming metal silicide on the surfaces of the source/drain and wiring areas and then implanting As ions. Further, as the impurity for forming the source/drain, any impurity other than As may be used as long as it is an impurity having a conductivity type opposite to that of the substrate, such as B, Al, or P. Also, although only the case of SiO ₂ is shown as the material covering the gate electrode,
Any insulating material such as alumina may be used for this as well. Further, although polycrystalline silicon was used as the gate electrode and a thin SiO ₂ film was interposed between the heat-resistant material Si ₃ N ₄ , this SiO ₂ film is not necessarily necessary. In this case, the Si ₃ N ₄ film is used only as a stopper when removing with CF ₄ +O ₂ gas plasma, and this SiO ₂ film is unnecessary if a removal method using hot phosphoric acid or the like is used. In addition, in the example,
Although As ion implantation into the diffusion layer was performed only after patterning the polycrystalline silicon gate, a second As ion implantation was performed immediately before metal silicide formation in order to compensate for the recession of the oxide film 7 shown in Fig. 1. It is also possible. Further, in this case, the first ion implantation does not necessarily need to be performed at a high concentration, and may be performed at a dose of, for example, 1×10 ¹¹ to 1×10 ¹² cm ⁻² . In addition, in this example, the diffusion layer and gate polysilicon surfaces were all silicided, but if necessary, a mask such as a silicon oxide or silicon nitride film may be used partially to prevent the silicidation reaction from proceeding. Of course, it can also be done easily. In short, the present invention can be implemented with various modifications without departing from the gist thereof.

[Brief explanation of the drawing]

Figures 1 a to c and 2 are cross-sectional views for explaining the problems of the conventional method, and Figures 3 a to h
4 is a sectional view showing the manufacturing process of a MOS integrated circuit according to an embodiment of the present invention, FIG. 4 is a plan view for explaining the above embodiment, and FIG. 5 is a sectional view for explaining another embodiment. be. 11...Silicon substrate, 12...Field oxide film, 13...Gate oxide film, 14...Polycrystalline silicon film (gate electrode), 16...Silicon nitride film (oxidation prevention film), 18a, 18b...
Source/drain region, 19...diffusion wiring region,
20... Silicon oxide film, 22... Tungsten film (metal film), 23... Tungsten silicide film (conductive film), 25... Tungsten film (conductive film).

Claims (1)

[Claims] 1. When manufacturing a semiconductor device in which a source/drain region of an MIS transistor and a diffusion wiring region connected to at least one of these are provided in a silicon substrate, a gate insulating film, a multilayer A step of laminating a gate electrode and an oxidation prevention film made of crystalline silicon, a step of depositing a silicon oxide film on the entire surface of the silicon substrate using a vapor phase growth method, and a step of depositing a silicon oxide film using a directional etching method. etching the entire surface of the oxide film and self-aligning the sidewalls of the gate electrode with the electrode to cover the silicon oxide film, then removing the anti-oxidation film, and then etching the gate electrode, source and drain. 1. A method of manufacturing a semiconductor device, comprising: selectively forming a conductive film in a self-aligned manner only on the region and the diffusion wiring region by selective CVD using a predetermined gas. 2. The semiconductor device according to claim 1, wherein the gas used in the selective CVD method for forming the conductive film is WF ₆ or MoF ₆ , and the conductive film is a tungsten film or a molybdenum film. manufacturing method. 3. In the step of forming the gate insulating film, gate electrode, and anti-oxidation film, a multilayer film consisting of a gate insulating film, a polycrystalline silicon film, and an anti-oxidation film is formed on the entire surface of the silicon substrate, and then the above-mentioned anti-oxidation film is formed. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising selectively etching the polycrystalline silicon film into a desired shape. 4. A method for manufacturing a semiconductor device according to claim 1, characterized in that a reactive etching method or a sputter etching method is used as a directional etching method when etching the entire surface of the silicon oxide film. . 5. The method of manufacturing a semiconductor device according to claim 1, wherein a silicon nitride film is used as the oxidation-preventing film. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the anti-oxidation film is a multilayer film including a laminated film in which a silicon nitride film is deposited on at least a silicon oxide film. 7 When manufacturing a semiconductor device in which a source/drain region of an MIS transistor and a diffusion wiring region connected to at least one of these are provided in a silicon substrate, a gate insulating film and a gate electrode made of polycrystalline silicon are provided on a silicon substrate. a step of depositing a silicon oxide film over the entire surface of the silicon substrate using a vapor phase growth method; and a step of etching the silicon oxide film over the entire surface using a directional etching method. , a step of self-aligning the side wall portion of the gate electrode with the electrode to cover the silicon oxide film, then a step of removing the anti-oxidation film, and then depositing a metal film on the entire surface of the silicon substrate, The gate electrode and the source are formed by performing an annealing treatment to silicide the portion of the metal film in contact with silicon to form metal silicide in the portion, and then removing the remaining metal film that has not been silicided. - A method for manufacturing a semiconductor device, comprising the steps of: selectively forming the conductive film made of silicide on the drain region and the diffusion wiring region in a self-aligned manner. 8. In the step of forming the gate insulating film, gate electrode, and anti-oxidation film, a multilayer film consisting of a gate insulating film, a polycrystalline silicon film, and an anti-oxidation film is formed on the entire surface of the silicon substrate, and then the above-mentioned anti-oxidation film is formed. 8. The method of manufacturing a semiconductor device according to claim 7, further comprising selectively etching the polycrystalline silicon film into a desired shape. 9. A method for manufacturing a semiconductor device according to claim 7, characterized in that a reactive etching method or a sputter etching method is used as a directional etching method when etching the entire surface of the silicon oxide film. . 10. The method of manufacturing a semiconductor device according to claim 7, wherein tungsten is used as the metal film. 11. The method of manufacturing a semiconductor device according to claim 7, wherein a silicon nitride film is used as the oxidation-preventing film. 12. The method of manufacturing a semiconductor device according to claim 7, wherein the anti-oxidation film is a multilayer film including a laminated film in which a silicon nitride film is deposited on at least a silicon oxide film.