JPH0577177B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a test circuit that can test LSI wafers at high speed and easily.

Conventional Technology As LSIs become larger in scale, it is becoming increasingly difficult to test their functionality. LSI as a solution
Attempts are being made to add testing functionality to circuits. In particular, in wafer-scale large-scale integrated circuits, a dedicated circuit or CPU that generates test patterns and judges output results is formed on the wafer in advance, and by operating it, the quality of each component unit within the wafer is judged. However, connections between non-defective units are performed (for example, wiring fuse programming).

Problems to be Solved by the Invention Since such conventional LSI test circuits are formed on a wafer together with other circuits, the test circuit itself may not operate due to process defects. Therefore, it is necessary to form a plurality of test circuits to provide redundancy not only to the constituent units within the wafer but also to the test circuits, which complicates the overall system and increases cost.

An object of the present invention is to eliminate redundancy in test circuits with a simple configuration and to improve the efficiency of testing large-scale integrated circuits.

Means for Solving the Problems In order to solve the above problems, the present invention mounts a highly versatile non-defective CPU chip prepared in advance on a wafer as a test circuit, and connects the rotation terminal on the wafer and the CPU circuit terminal. The component units within the wafer are then inspected.

Operation According to the above-described configuration, the present invention applies a test pattern to the constituent units on the wafer according to a built-in program from a non-defective CPU incorporated as a test circuit on the wafer, and outputs from the constituent units are read into the CPU. A comparison is made with the expected value, and a pass/fail judgment is made.

Embodiment FIG. 1 is a plan view showing an embodiment of the LSI testing circuit of the present invention. In FIG. 1, a good CPU chip 2 is bonded onto a non-active area 1 of a wafer using an organic resin or the like. Area 1
Around the wafer are aluminum wires for signal lines, power lines, and ground lines that connect the circuit configuration units within the wafer.
The electrodes 3 are arranged, and the Al on the CPU chip 2
It is connected to the electrode 4 by a gold or Al wire 5. To operate the CPU, external probes are connected to power supply pad 6 and ground pad 7 to supply power, and clock and start signals are supplied from pads 8 and 9, respectively. The instructions for executing the inspection are stored in the ROM or EPROM inside the CPU, and the CPU starts executing the inspection instructions upon receiving a start signal. The inspection results are temporarily stored in the RAM in the CPU, and are sent out from the pad 10 in the form of serial data when the complete inspection is completed.

Regarding full wafer scale LSI inspection,
This will be explained based on FIG. on wafer 11
Circuit configuration units 12 such as RAM, ROM, registers, etc. are arranged in a redundant form, that is, in plural units. Each component unit is assigned an address and can be accessed by the CPU. All input/output signals common to each unit are connected, and only the unit selected by the CPU operates with signals input internally.
Since the output signal is given only from the selected unit, the CPU inspects its value and sends the pass/fail result of that unit as a binary code of 0 and 1 internally in the CPU.
Write to RAM. When all the units have been inspected, the results are read out from the RAM, and based on the results, defective units are separated from the connections by means such as wiring trimming with a laser beam, creating an entire circuit consisting only of good units.

Although the case where the CPU is mounted as a chip on the wafer has been described, it is also possible to use a packaged CPU (for example, a flat package).

Effects of the Invention As described above, according to the present invention, since a non-defective CPU on a separate chip is used as the test circuit,
There is no need to provide redundancy to the test circuit, and an LSI test circuit can be realized easily and at low cost.

[Brief explanation of drawings]

FIG. 1 is a plan view showing an LSI test circuit according to an embodiment of the present invention, and FIG. 2 is a plan view of an LSI test circuit according to another embodiment of the present invention.
FIG. 2 is a plan view showing an LSI test circuit. 1...Inactive area, 2...CPU chip, 3,
4... Al electrode, 5... Gold wire, 11... Wafer, 12... Circuit configuration unit.

Claims (1)

[Claims] 1. On the non-active area of the wafer surface, a non-defective CPU
1. An LSI inspection circuit on which a chip is mounted and selectively connects metal electrodes for signals, power and ground provided on a wafer in advance to metal electrodes on the CPU chip. 2. The LSI testing circuit according to claim 1, wherein the CPU chip is packaged, and metal electrodes on the wafer and leads of the package are selectively connected.