JPH0577292B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to semiconductor integrated circuits, and in particular to ROM,
The present invention relates to a logic circuit that has a built-in sequential circuit such as a RAM, and has a structure in which the sequential circuit can be directly accessed from an external terminal.

[Conventional technology]

In general, a semiconductor integrated circuit with a built-in sequential circuit has a configuration in which a sequential circuit 5 is surrounded by a combinational circuit 4, as shown in FIG. are often inaccessible and are built into logic circuits.
When testing the functions of ROM, RAM, etc. directly from external terminals, as shown in Figure 3, a new input/output terminal 3, separate from the original input/output terminals of the logic circuit, is
33, 34, input/output buffer circuits 11, 23 are provided, and the sequential circuit 5, which is the circuit under test, is directly accessed through the input/output terminals, or the input terminal 41 of the logic circuit and the input buffer circuit 11 are provided as shown in FIG. is also used as an input signal supply terminal during a functional test, the output terminal 42 and output buffer circuit 23 of the logic circuit are also used as an output signal observation terminal during a functional test, and the selector circuit 6 is used to monitor the logic circuit during a functional test. The configuration was such that the sequential circuit 5, which is the circuit under test, was directly accessed from the input/output terminals.

[Problem that the invention seeks to solve]

In the conventional logic circuit described above, the method of newly providing input/output terminals and input/output buffer circuits is that if the number of input/output terminals of the circuit under test is large, the number of input/output buffers and input/output terminals of the logic circuit can be increased. As the number of logic circuits increases, the number of usable signal terminals of logic circuits decreases in devices such as gate arrays in which the number of input/output terminals is fixed. Furthermore, standard cells and other custom LSIs have the disadvantage of increasing chip size.

In addition, in order to avoid increasing the number of input/output terminals, the input/output terminals of the logic circuit are shared with the functional test terminals of the circuit under test, and a selector circuit is used. Unnecessary wiring is required, and if the wiring length increases, the delay time of the input buffer circuit increases.Also, because a selector circuit is interposed between the input terminal of the output buffer of the logic circuit and the output terminal of the combinational circuit, This has the disadvantage that the delay time also increases.

[Means for solving problems]

The semiconductor integrated circuit of the present invention is a semiconductor integrated circuit consisting of a logic circuit which includes a built-in sequential circuit and whose function can be tested directly from an external terminal, in which the input terminal of the logic circuit is used during normal operation. and an output terminal that operates as an input buffer circuit and takes out the output of the sequential circuit to the outside of the logic circuit during a functional test of the sequential circuit, and an input/output common terminal and an input/output common terminal configured to operate as a 3-state output buffer circuit. The buffer circuit operates as an output terminal of a logic circuit and a 3-state output buffer circuit during normal operation, and as an input terminal and input buffer circuit for applying a signal to the input of the sequential circuit during a functional test of the sequential circuit. It is characterized by including a configured input/output common terminal and an input/output common buffer circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention. In this embodiment, the logic circuit is a sequential logic circuit 5 that needs to be directly accessed and tested from external terminals such as ROM, RAM, etc., other combinational logic circuits 4, and input signals to the sequential logic circuit 5 are connected to a normal combinational logic circuit 4. A selector circuit 6 selects between a signal from the terminal 1 and a signal applied from the input terminal during testing, and further supplies the signal applied from terminal 1 to the combinational logic circuit 4 during normal operation, and the output of the sequential logic circuit 5 during testing. An input/output common buffer circuit consisting of an input buffer circuit 7 and a 3-state output buffer circuit 8 for extracting signals to the outside, and a 3-state output buffer circuit 9 for outputting the output signal of the combinational logic circuit section 4 during normal operation. It consists of an input/output common buffer circuit configured to take out the signal to the terminal 2 and apply the signal applied to the terminal 2 to the sequential logic circuit 5 via the input buffer circuit 10 and the selector circuit 6 during testing.

Is this logic circuit in a normal operating state? Sequential logic circuit 5
A control input terminal 3 for selecting the state to be tested is provided, and is connected to a control input of a 3-state output buffer circuit 8 and a selector circuit 6 via an input buffer 11.
The signal applied to the 3-state output buffer circuit 9 is inverted by the inverter 12 and applied to the control input of the 3-state output buffer circuit 9.

The operation of the logic circuit configured as described above is as follows. First, a case will be described in which the control input terminal 3 is at a high level, that is, the sequential logic circuit 5 is tested. In this state, a low level is applied to the control input terminal of the three-state output buffer circuit 9, the output of the output buffer circuit 9 is in a high impedance state, and the terminal 2 is in the input mode. Further, a high level is applied to the control input terminal of the selector circuit 6, and the signal applied to the input from the output of the input buffer circuit 10 is obtained at the output of the selector circuit 6. That is, the input signal applied to the input terminal 2 is applied to the input of the sequential logic circuit 5 through the input buffer circuit 10 and the selector circuit 6. Further, a high level is applied to the control input terminal of the 3-state output buffer circuit 8, and the output buffer circuit 8 is put into an operating state, so that the output signal of the sequential circuit 5 is obtained at the terminal 1. In other words, in this state, the sequential logic circuit 5 can be accessed directly from the terminals 1 and 2.

Next, a case will be described in which the control input terminal 3 is at a low level, that is, the logic circuit is in a normal operating state. In this state, the 3-state output buffer circuit 9
Its control input becomes high level and performs an output buffer operation, and the output of the combinational logic circuit 4 appears at the terminal 2. Further, the output of the three-state output buffer circuit 8 becomes high impedance, and the terminal 1 operates as a normal input terminal. Further, since the control input of the selector circuit 6 becomes low level, the output signal of the combinational logic circuit 4 is outputted to its output.

〔Effect of the invention〕

As explained above, the present invention inputs and outputs the original output terminal of the logic circuit and the 3-state output buffer circuit as the input terminal and input buffer circuit when testing a logic circuit that has a circuit portion that requires direct testing from an external terminal. The input buffer part is used as a shared terminal and input/output buffer circuit configuration, and the original input terminal and input buffer circuit of the logic circuit is used as the output terminal and output buffer circuit during testing. By using the 3-state output buffer section, there is no need to increase the number of external terminals for testing. Moreover, the output of the input buffer circuit that receives input signals from the input terminal during normal operation is not connected to wiring that is not necessary for the original operation, so there is no delay in signal transmission from the input buffer circuit. As a result, it is possible to configure a logic circuit that does not increase the delay time of the logic circuit.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention;
Figure 2 is a circuit configuration diagram of a conventional logic circuit that does not include external test terminals and a test control circuit, and Figures 3 and 4 are circuit diagrams of conventional logic circuits that include external test terminals and a test control circuit. FIG. 1... Logic circuit input and test circuit output common terminal, 2... logic circuit output and test circuit input common terminal, 3... control input terminal, 4... combinational logic circuit, 5... sequential logic circuit, 7 ,10,11...
Input buffer circuit, 8, 9, 23... Output buffer circuit, 6... Selector circuit, 12... Inverter, 21, 31... Logic circuit input terminal, 22,
32...Logic circuit output terminal, 33...Circuit under test input terminal, 34...Circuit under test output terminal, 41...
...Logic circuit input and circuit under test input common terminal, 4
2... Logic circuit output and circuit under test output common terminal.

Claims (1)

[Claims] 1 A sequential circuit including a sequential circuit, a first terminal functioning as an input terminal during normal operation, and a first input buffer circuit connected to the first terminal, and receiving a signal supplied from the first terminal during the normal operation. a first logic circuit that supplies the sequential circuit; a second terminal that functions as an output terminal during the normal operation;
a second logic circuit that includes a first output buffer circuit connected to a terminal of the sequential circuit and transmits a signal output from the sequential circuit during the normal operation to the second terminal; a second input buffer circuit connected to the sequential circuit, the second input buffer circuit being activated during a functional test and transmitting a signal supplied to the second terminal to the sequential circuit; A second output buffer circuit connected to the terminal and activated during the functional test to transmit the signal obtained from the sequential circuit to the first terminal. Semiconductor integrated circuit.