JPH0577330B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] Regarding a method for manufacturing a semiconductor device, particularly a method for forming a fine wiring layer, tungsten (W) is deposited in a groove formed in an insulating layer on a substrate corresponding to a predetermined wiring pattern. By selectively growing high-melting point metals such as metals, we have developed a formation method that can prevent defects such as cavities from occurring in the wiring layer when forming a flat and fine wiring layer in a self-aligned manner. A trench having a shape corresponding to a predetermined wiring pattern and a bottom located at a depth D from the surface is formed in a first insulating layer deposited on the surface of the substrate, A semiconductor layer or a metal layer having a thickness d ₁ (where d ₁ <D) is deposited on the surface of the substrate having the first insulating layer provided with a groove, and a thickness of d 1 is deposited on the semiconductor layer or metal layer. d ₂ (where d+d ₂ <D)
forming an insulating layer, filling the trench covered with the semiconductor layer or the metal layer and the second insulating layer with a mask material for selective removal of at least the second insulating layer; removing the second insulating layer exposed from the mask material to selectively leave the second insulating layer on at least the bottom surface of the groove, the second insulating layer remaining on at least the bottom surface of the groove; is used as a mask, the exposed semiconductor layer or metal layer is removed, the semiconductor layer or metal layer is selectively left on the bottom of the groove, and the mask material and the second layer remaining on at least the bottom of the groove are removed. The insulating layer is selectively removed to expose the semiconductor layer or metal layer on at least the bottom surface of the trench, and a high layer is formed inside the trench using the semiconductor layer or metal layer exposed on at least the bottom surface of the trench as a core. It consists of steps of vapor phase growth of a melting point metal.

[Industrial application field]

The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming a wiring layer having a fine width and a flat surface.

[Conventional technology]

2. Description of the Related Art As semiconductor devices become more highly integrated, there is a demand for finer wiring. Currently, the width is 1.2 μm, which is formed by making full use of lithography technology and etching technology.
Aluminum thin film wiring is mainly used.
However, aluminum wiring is prone to so-called electromigration and stress migration of aluminum (Al) atoms, and especially when the wiring becomes finer, these phenomena can easily lead to disconnections, making it difficult to guarantee reliability. becomes difficult.

On the other hand, there is a method using tungsten (W) as the wiring material. Tungsten has a lower coefficient of thermal expansion than aluminum and has stronger interatomic bonds, so even when tungsten is used in a wiring layer, migration as described above is unlikely to occur. However, in general, tungsten thin films have lower adhesion to the underlying insulating layer than aluminum thin films, and
The stress generated inside the thin film is large. Therefore, there is a problem in that the film is easily peeled off from the base during film formation or post-heat treatment.

That is, tungsten thin films are typically CVD
It is formed by a method such as a method or a sputtering method. The internal stress depends on the film forming conditions, but generally a large compressive stress is generated. When a large compressive stress exists in a tungsten thin film formed on the entire surface of a substrate such as a silicon wafer, stress concentration occurs in areas where the adhesion to the underlying insulating layer is weak, making it easy to peel off there.

On the other hand, as wiring becomes finer, when an interlayer insulating layer or a protective insulating layer is formed thereon, the valleys between the wirings are not completely filled with an insulator, resulting in exposed portions of the wiring. As a result, poor insulation and corrosion of wiring due to long-term residual effects of various chemicals and water used in subsequent processing occur, resulting in a decrease in the reliability of the semiconductor device. For these reasons, it is desirable that the surface on which the fine wiring is formed is flat.

Therefore, a wiring structure has been proposed in which a groove corresponding to a predetermined wiring pattern is provided in an insulating layer formed on a semiconductor circuit board, and the groove is filled with wiring material. (For example, JP-A-62-141740 and JP-A-62-243324) According to this structure, the bonding area between the tungsten thin film and the underlying insulating layer increases, making it difficult for peeling to occur, and the wiring layer is flush with the underlying insulating layer. Therefore, problems such as poor insulation of the interlayer insulating layer formed thereon can be avoided.

[Problem to be solved by the invention]

The above application discloses that when filling a wiring material such as tungsten (W) into a concave groove formed in an insulating layer by reducing a gaseous tungsten compound with hydrogen, the side surface of the groove made of an insulator is A polycrystalline silicon layer is formed in advance. As a result, tungsten selectively grows on the polycrystalline silicon layer, eventually filling the trench. In this way, the tungsten wiring, which forms a flat surface with the insulating layer surface in which the grooves are formed, is formed in a self-aligned manner corresponding to the predetermined wiring pattern.

However, as the groove width becomes smaller, the difference in growth rate on the side surfaces inside the groove becomes significant. That is, the growth rate is higher in the sidewall portions closer to the opening of the groove, and the growth rate is lower in the sidewall portions closer to the bottom of the groove. As a result, before the trench bottom is completely filled with tungsten, the trench opening is filled with tungsten that has grown at a relatively high rate, creating a cavity in the wiring layer filling the trench. This phenomenon is
The problem becomes more pronounced as the depth of the trench increases, that is, as the wiring layer becomes thicker. The thickness of the tungsten layer decreases in the areas where cavities like those described above occur, which not only increases wiring resistance, but also increases contact resistance with the underlying layer, poor contact, or increases in current density. Disconnection is likely to occur due to electromigration accelerated by self-heating.

Therefore, the present invention is capable of self-aligning a flat and fine wiring layer by selectively growing a high melting point metal such as tungsten in a groove formed in an insulating layer on a substrate in accordance with a predetermined wiring pattern. An object of the present invention is to provide a forming method that can prevent defects such as cavities from occurring in the wiring layer when forming the wiring layer.

[Means to solve the problem]

The above object includes a step of forming a groove in a first insulating layer deposited on a substrate surface, the groove having a shape corresponding to a predetermined wiring pattern and having a bottom surface located at a depth D from the surface; The surface of the substrate having the first insulating layer provided with a thickness d ₁ (where d ₁ <D)
forming a second insulating layer having a thickness d ₂ (where d ₁ +d ₂ <D) on the semiconductor layer or metal layer; filling the groove covered by the layer or the metal layer and the second insulating layer with a masking material for selective removal of at least the second insulating layer; removing the second insulating layer to form the second insulating layer at least on the bottom surface of the trench;
selectively leaving the second insulating layer remaining on the bottom surface of the trench, and using the second insulating layer remaining on the bottom surface of the trench as a mask, removing the exposed semiconductor layer or metal layer, and leaving the semiconductor layer on the bottom surface of the trench. selectively leaving the semiconductor layer or metal layer on at least the bottom surface of the groove, and selectively removing the mask material and the second insulating layer remaining on at least the bottom surface of the groove to leave the semiconductor layer or metal layer on at least the bottom surface of the groove. The present invention is characterized in that it includes a step of exposing a layer, and a step of growing a refractory metal in a vapor phase inside the groove using the semiconductor layer or metal layer exposed on at least the bottom surface of the groove as a nucleus. This is achieved by the method for manufacturing a semiconductor device according to the above.

[Effect]

For example, a polycrystalline silicon layer is formed only on the bottom surface of a groove with a predetermined fine width provided in an insulating layer, and a high melting point metal such as tungsten is selectively grown using this polycrystalline silicon as a core. As a result, the trench is filled with tungsten or the like from the bottom or from the bottom and the bottom of the sides, and the area near the opening of the trench is filled last, so no cavities are created in the wiring layer filling the trench, resulting in high reliability. It is possible to form fine and flat wiring layers. Furthermore, since cavities are unlikely to be formed in the wiring layer even if the trenches are made deep, the thickness of the wiring layer can be made larger than before, and wiring with low resistance can be obtained.

〔Example〕

FIG. 1 is a schematic sectional view of a main part showing the steps of an embodiment of the present invention, and the present invention will be described below with reference to FIG.

As shown in FIG. 1a, a silicon (Si) substrate 1
Thereon, a device isolation layer 2 and a PSG (phosphosilicate glass) layer 3, which is an interlayer insulating layer, are formed using a well-known method. The element isolation layer 2 isolates active regions (not shown) defined on the silicon substrate 1. and,
The PSG layer 3 is formed from above the element isolation layer 2 to the active region. A semiconductor element or circuit is formed in this active region, and the PSG layer 3
is provided with a contact window (not shown) corresponding to a contact region in the active region or a lower wiring (not shown) running on the element isolation layer 2, and this contact window is made of, for example, a well-known SiH ₄
It is assumed that the hole is filled with tungsten or the like that has been selectively grown using a reduction method. Note that the thickness of the PSG layer 3 is approximately 0.8 μm.

Next, as shown in FIG. 1b, a well-known method is applied to the entire surface of the silicon substrate 1 on which the PSG layer 3 is formed.
A second PSG with a thickness of approximately 1.2 μm was created using the CVD method.
After forming the layer 4, a resist mask 10 having openings corresponding to predetermined wiring patterns is formed. Then, using, for example, the well-known reactive ion etching (RIE) method, the PSG layer 4 exposed from the resist mask 10 is selectively removed.
As shown in FIG. 1c, grooves 5 are formed in the PSG layer 4. The groove 5 corresponds to the wiring pattern and reaches above the contact window at a position not shown, and the tungsten groove 5 fills the contact window.
It is exposed on the bottom of the.

After forming the grooves 5, the silicon substrate 1 is formed using, for example, the well-known CVD method, as shown in FIG. 1d.
A polycrystalline silicon layer 6 with a thickness of about 1000 Å is formed on the entire surface. Next, a SiO ₂ layer 7 with a thickness of about 700 Å is formed on the surface of the polycrystalline silicon layer 6 by, for example, a thermal oxidation method.
form. In this embodiment, the depth D of the groove 5 is
is equal to the thickness of the PSG layer 4, 1.2 μm, and the relationship d ₁ + d ₂ <D is maintained between the thickness d ₁ of the polycrystalline silicon layer 6 and the thickness d ₂ of the SiO ₂ layer 7. ing.

Next, as shown in FIG. 1e, a polymer layer 8' such as photoresist is coated on the entire surface of the silicon substrate 1, baked at a predetermined temperature, and then subjected to a method such as oxygen plasma treatment. The SiO ₂ layer 7 around the groove 5 is removed until it is exposed. As a result, the polymer layer 8 is buried inside the groove 5, as shown in FIG. 1f.

Using the polymer layer 8 as a mask, the exposed SiO ₂ layer 7 is selectively removed. This is done, for example, by immersing the silicon substrate 1 in a buffered hydrofluoric acid solution. By the selective removal, the polycrystalline silicon layer 6 is exposed around the trench 5 and on the inner side surfaces of the trench 5, as shown in FIG. 1g. As a result of the above selective removal, if the SiO ₂ layer 7 remains at the lower side of the groove 5, RIE is performed using CF ₄ and CHF ₃ as an etching gas to remove the remaining SiO ₂ layer 7, if necessary. . As a result of etching, there is no problem even if some SiO ₂ remains on the lower side of the groove 5.

Next, the silicon substrate 1 is subjected to oxygen plasma treatment to remove the polymer layer 8 inside the groove 5. As a result, it was found that the mask was masked by the polymer layer 8.
A SiO ₂ layer 7 is exposed on the bottom surface of the trench 5, as shown in FIG. 1h. The polycrystalline silicon layer 6 is selectively removed while the bottom surface of the trench 5 is masked with the SiO ₂ layer 7. In this selective removal, isotropic plasma etching using, for example, CF ₄ as an etching gas is used, and as a result, the polycrystalline silicon layer 6 on the inner side surface of the trench 5 is also removed, as shown in FIG. 1i.
In the above, before removing the polymer layer 8 inside the groove 5, the isotropic plasma etching is performed to selectively remove the polycrystalline silicon layer 6, and then the polymer layer 8 is removed by oxygen plasma. This may be the order in which they are removed.

Next, for example, the silicon substrate 1 is immersed in a buffered hydrofluoric acid solution to remove the SiO ₂ layer 7 present on the bottom surface of the groove 5. As a result, the polycrystalline silicon layer 6 remaining on the bottom surface of the groove 5 is exposed, as shown in FIG. 1J.

As described above, a polycrystalline silicon layer 6 is formed on the bottom surface.
Tungsten is selectively grown inside the groove 5 while remaining. As this selective growth method, a hydrogen reduction method is used in which a gaseous tungsten compound such as tungsten hexafluoride (WF ₆ ) is reduced with hydrogen gas to precipitate metallic tungsten. Examples of the conditions are a growth temperature of 400° C., flow rates of WF ₆ and H ₂ of 10 sccm and 2 sccm, and a total reaction gas pressure of 0.2 Torr. As a result, the tungsten layer starts to grow using the polycrystalline silicon layer 6 existing on the bottom surface of the groove 5 as a nucleus, and grows toward the opening. No growth occurs from the sides of groove 5. As a result, as shown in FIG. 1K, the inside of the trench 5 is filled with tungsten grown from the bottom direction, and a tungsten wiring layer 9 having a predetermined width and thickness is formed.

After the above steps, steps similar to those for normal semiconductor devices are performed, including the formation of an interlayer insulating layer (not shown), the formation of contact windows for this interlayer insulating layer, the formation of upper layer aluminum wiring, the formation of a protective insulating layer, and the formation of bonding openings. Through these steps, the semiconductor device of the present invention is completed.

Note that as the polymer layer 8 mentioned above, a polymer material other than the photoresist may be used, such as a polyimide resin. Further, as a method for selectively growing tungsten in the groove 5, it is also possible to use a method of reducing WF ₆ using SiH ₄ (silane) instead of hydrogen. Furthermore, when forming a wiring layer of a high melting point metal other than tungsten, a similar process may be applied using a gaseous compound of the metal instead of WF ₆ . Furthermore, the polycrystalline silicon layer 6 may be replaced with a metal layer such as tungsten silicide containing excessive silicon.

Further, in the above embodiment, the depth D of the groove 5 is
Although the case where the thickness is equal to the thickness t of the PSG layer 4 is shown,
It goes without saying that the present invention is applicable even if the depth of the groove provided in the PSG layer 4 is t<D.

〔Effect of the invention〕

According to the present invention, a wiring layer made of a high-melting point metal such as tungsten can be formed without creating a cavity inside, and has the effect of improving the reliability of high-density semiconductor devices that require fine width and flat wiring. There is.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view of essential parts showing the steps of an embodiment of the present invention. In the figure, 1 is a silicon substrate, 2 is an element isolation layer, 3 and 4 are PSG layers, 5 is a groove, 6 is a polycrystalline silicon layer, 7 is a SiO ₂ layer, 8 is a polymer layer, 9 is a tungsten wiring layer, 10 is a resist mask.

Claims (1)

[Claims] 1. A step of forming a groove in a first insulating layer deposited on the surface of the substrate, the groove having a shape corresponding to a predetermined wiring pattern and having a bottom surface located at a depth D from the surface. , depositing a semiconductor layer or metal layer having a thickness d ₁ (where d ₁ <D) on the surface of the substrate having the first insulating layer provided with the groove; On top, the thickness d ₂ (however
forming a second insulating layer having d ₁ +d ₂ <D); and forming at least the second insulating layer in the groove covered by the semiconductor layer or the metal layer and the second insulating layer. filling with a mask material for selective removal of layers; removing the second insulating layer exposed from the mask material to selectively leave the second insulating layer at least on the bottom surface of the groove; a step of removing the exposed semiconductor layer or metal layer using at least the second insulating layer remaining on the bottom surface of the trench as a mask, and selectively leaving the semiconductor layer or metal layer on the bottom surface of the trench; selectively removing the mask material and the second insulating layer remaining on at least the bottom surface of the groove to expose the semiconductor layer or metal layer on at least the bottom surface of the groove; 1. A method for manufacturing a semiconductor device, comprising the step of growing a high melting point metal in a vapor phase inside the trench using the semiconductor layer or metal layer exposed on at least the bottom surface of the trench as a nucleus. 2. Manufacturing the semiconductor device according to claim 1, which includes a step of performing heat treatment to alloy the semiconductor layer or metal layer with the high melting point metal after the vapor phase growth step of the high melting point metal. Method. 3 doping the semiconductor layer deposited on the surface of the substrate having the first insulating layer with an impurity to serve as a donor or acceptor; and performing heat treatment to lower the resistance of the semiconductor layer doped with the impurity. Claim 1 or 2 characterized in that it includes a step of
A method for manufacturing a semiconductor device.