JPH0578181B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an improvement in a method for forming wiring.

[Technical background of the invention and its problems]

In semiconductor devices, especially integrated circuits, in order to achieve a high degree of integration, it is necessary to reduce the size of elements. Recently, due to advances in optical exposure technology, electron beam exposure technology, and the like, elements with dimensions of 1 micron or submicron have been researched and developed. Along with this,
Hole for electrical connection (contact hole)
There is an increasing need to realize dimensions of about 1 micron.

When the size of a contact hole is about 2 microns, a semiconductor device is generally manufactured as follows. First, a silicon oxide film as an insulator is deposited on a semiconductor substrate that has been subjected to an element formation process, and then a PSG film with a gettering effect is further deposited to form an insulating film of 1 to 1.5 [μm]. . Next, after heat treatment at a high temperature of about 1000 [℃],
A contact hole is opened in a predetermined portion of the insulating film. Subsequently, an Al-Si alloy film of about 1 [μm] is deposited on the entire surface using a vapor deposition method, a sputtering method, or the like. Next, a wiring pattern (resist pattern) made of a photoresist film is formed on the Al-Si alloy film,
Using this resist pattern as a mask, for example,
A wiring layer is formed by dry etching using a CCl ₄ +Cl ₂ mixed gas. After that, by heating the entire board to about 500 [℃],
Ohmic contact between the element and the Al--Si alloy film can be obtained, and electrical connection through the wiring layer becomes possible.

However, when such a wiring formation method is applied to a contact hole with a size of 1 micron or submicron, the adhesion of the Al-Si alloy film inside the contact hole deteriorates, and as shown in Figure 1, the adhesion of the Al-Si alloy film inside the contact hole deteriorates. The thickness of the Al-Si alloy film becomes extremely thin. This reduces the reliability of the wiring and causes problems in the operation of the device. In FIG. 1, 1 is a silicon substrate, 2 is a diffusion layer, 3 is an insulating film, 4 is a contact hole, and 5 is a conductor film (Al--Si alloy film). Additionally, as semiconductor devices become smaller and more sophisticated, the depth Xj of the diffusion layer 2 becomes shallower, 0.2 to 0.1 [μ
m] is also required, but in this case Al
-Si film 5 and diffusion layer 2 react when heated to 500[° C.], causing problems such as destruction of the junction and increased leakage current. Furthermore, after the above heating, Al
-Si in Al-Si near the diffusion layer 2 in the Si alloy film 5
This also caused inconveniences such as the electrical resistance of the wiring increasing at the contact hole portion.

On the other hand, (Electrochemical Society 1982
As seen in Spring Meeting Extended Abstract No. 228), a method has been considered in which a polycrystalline silicon film 6 is formed under a conductive film 5 of Al or the like as shown in FIG. However, in this type of method, the wiring resistance in the contact hole 4 increases due to the presence of the polycrystalline silicon film 6, and
The drawback of reduced reliability due to the reaction between Al and Si still remains. Furthermore, electromigration is likely to occur. That is, when an alloy of Al and Si is formed in Al due to annealing or energization, the resistance of that part is high, making it easy to generate heat, which eventually leads to wire breakage. Further, in order to prevent an increase in resistance within the contact hole 4, it is necessary to dope the polycrystalline silicon film 6 with an impurity, but in this case, an ion implantation process, a thermal process, etc. are required, which complicates the process. Furthermore, when connecting between high-concentration diffusion regions of different conductivity types or between polycrystalline silicon gates in a wiring layer of a C-MOS semiconductor device, the polycrystalline silicon film under the Al wiring is doped with different types of impurities. There were problems such as the need to change the conductivity type of the crystalline silicon film, which made the process even more complicated.

[Purpose of the invention]

The purpose of the present invention is to prevent a decrease in the thickness of a conductor film and an increase in wiring resistance caused by reactions between Al and Si when using fine contact holes, improve wiring reliability, and increase integration density. An object of the present invention is to provide a method of manufacturing a semiconductor device that can be improved.

[Summary of the invention]

The gist of the present invention is to form a high melting point metal or its silicide film under a conductor film such as Al.

That is, the present invention provides a method for manufacturing a semiconductor device that makes electrical connection with a conductive film through a contact hole, in which a contact hole is formed in a predetermined portion of an insulating film deposited on a semiconductor substrate that has undergone an element forming process. After the formation, a first conductive film made of a high melting point metal or a high melting point metal silicide is deposited on the entire surface using a vapor phase growth method, and then a second conductive film made of Al or the like is deposited on this first conductive film. In this method, the second and first conductor films are selectively etched into a desired pattern.

〔Effect of the invention〕

According to the present invention, since the contact hole formed in the insulating film is coated with a high melting point metal or its silicide by the vapor phase growth method, even if the contact hole is minute, electrical connection can be achieved at the contact hole portion. reliability is improved. Here, the first reason why reliability is improved is that since the vapor phase growth method is used, the deposition shape of the first conductor film in the fine contact hole area is improved, and compared to the sputter deposition method, the first conductor film is deposited locally. This is because the thickness of the deposited film is less likely to decrease. The second reason is that the electrical connection inside the contact hole is made with a high-melting point metal or its silicide, so there is no reaction between Al and Si that would occur during normal heat treatment at about 500 [℃], and the P-type This is because the Si layer will not grow inside the contact hole and increase the contact resistance.

Further, since a high melting point metal or its silicide film is formed under the wiring layer (second conductor film) such as Al, alloying with Si is less likely to occur and electromigration is less likely to occur. Furthermore, Al
The processing characteristics of wiring layers are improved by dry etching. In other words, when anisotropic dry etching of an Al film or an Al alloy film is performed using a chlorine-based reactive gas such as CCl ₄ or Cl ₂ , an etching residue is generated at the end of the process, but a high melting point metal film is formed under the wiring layer. If this is done, there is no need to introduce impurities such as Si or Cu into Al, and etching residues can be reduced. Moreover, after etching the wiring layer, the high melting point metal or its silicide is etched.
By performing isotropic plasma etching without etching Al, it is also possible to reliably remove etching residues of Al. At this time, since the high melting point metal or its silicide film under the wiring layer can be made thin, side etching due to isotropic etching is approximately equivalent to the film thickness and hardly poses a problem. In addition, conventionally, after Al film patterning,
When removing unnecessary polycrystalline silicon, there was a risk that the substrate Si would be etched if the mask alignment of the Al film was misaligned, but according to the present invention, the etching selectivity with Si can be maintained, resulting in higher yields. .

Note that if the thickness of the first conductor film formed in the contact hole exceeds a certain limit, an overhang shape will occur, and a so-called "shape" will occur. Therefore, the film thickness D of the first conductor film deposited by the vapor phase growth method is 1/1/1 of the aperture size A of the contact hole.
It is desirable that it be 3 or less (D<A/3). Furthermore, in order to prevent the above-mentioned "s" from occurring, it is desirable to provide the upper part of the contact hole with a taper that widens toward the opening side. Further, in order to reduce the surface unevenness of the wiring layer caused by the second conductor film, it is desirable that the first conductor film remain only in the contact hole.

[Embodiments of the invention]

3A to 3E are cross-sectional views showing a semiconductor device manufacturing process according to an embodiment of the present invention. First, the third
As shown in Figure a, an element forming process is performed on a P-type silicon substrate 21. Here, in the figure, 22 is a field oxide film, 23 is a gate electrode of a MOS transistor,
24 is a gate oxide film, 25 is an n ⁺ diffusion layer forming a source or drain, and 26 is another
It shows an n ⁺ diffusion layer that forms the source or drain of a MOS transistor.

Next, as shown in FIG. 3b, a silicon oxide film (insulating film) 27 is deposited on the entire surface to a thickness of 1 μm, and openings are formed in the portions of this silicon oxide film 27 located on the diffusion layers 25 and 26. Contact holes 28 each having a hole size of 1 [μm] were formed. Next, as shown in FIG. 3c, a molybdenum film (first conductor film) 29 was deposited to a thickness of 0.2 [μm] over the entire surface using a vapor phase growth method. At this time, the molybdenum film 29 maintains a film thickness of approximately 0.2 [μm] even inside the contact hole 28. In addition, the film thickness D of the molybdenum film 29
(D = 0.2 μm) is set to 1/3 or less (D < A/3) of the opening dimension A (A = 1 μm) of the contact hole 28, so inconveniences such as "s" occurring inside the contact hole 28 are avoided. It did not occur.

Next, as shown in FIG. 3d, an aluminum film (second conductor film) 30 is deposited on the entire surface using a sputter deposition method.
It was deposited to a film thickness of 0.5 [μm]. Thereafter, a desired wiring resist pattern was formed, and using this pattern as a mask, the aluminum film 30 and molybdenum film 29 were etched to form a wiring layer as shown in FIG. 3e. At this time, by using an anisotropic dry etching method for etching the aluminum film 30, it is possible to improve the dimensional accuracy of the wiring layer, and by using an isotropic plasma etching method for etching the molybdenum film 29, the above-mentioned aluminum The residue generated during etching of the film 30 could be completely removed.

In the semiconductor device thus created, although the opening size of the contact hole 28 is extremely small at 1 [μm], it is possible to prevent the thickness of the wiring layer within the contact hole 28 from becoming extremely thin.
Wiring reliability can be improved. In addition, it is possible to further reduce the opening size of the contact hole 28, and the degree of integration can be improved. Further, when polycrystalline silicon is used as the first conductor film, there is no reaction of Al-Si or complication of the process, and its practicality is extremely high.

Note that the present invention is not limited to the embodiments described above. For example, the shape of the contact hole is not limited to a rectangular shape, but may have a taper that widens toward the opening as shown in FIG. 4. In this case, as is clear from FIG. 4, the overhang of the conductor film is reduced, and the occurrence of "s" can be more reliably prevented. Further, as a pre-process for depositing the second conductor film, the first
By removing the portions of the conductor film other than the contact holes, it becomes possible to reduce the unevenness of the substrate surface as shown in FIG. Furthermore, the present invention is not limited to connection between diffusion layers of the same conductivity type, but can also be applied to connection between diffusion layers of different conductivity types, as shown in FIG. In this case, there is no need to dope the two types of diffusion layers with p-type and n-type impurities, unlike the conventional method in which polycrystalline silicon is used as the first conductor film, and the process does not become complicated. In addition, Fig. 6 shows an example of a C-MOS inverter, and 3 in the figure shows an example of a C-MOS inverter.
1 indicates an n-well, and 32 indicates a p ⁺ diffusion layer.

Further, the first conductive film is not limited to molybdenum, and may be any high-melting point metal such as tungsten, titanium, tantalum, or the like, or may be a silicide of these metals. Furthermore, the second conductive film is not limited to aluminum, and may be made of aluminum alloy or other low-resistance materials. Also,
The film thicknesses of the first and second conductor films can be changed as appropriate depending on the opening size of the contact hole and other conditions.

It is also possible to form the aluminum film 30 by lift-off in the process shown in FIG. 3d. That is, as shown in FIG. 7, a resist pattern 33 is formed in a region other than the wiring, and then an aluminum film 30' is deposited. Then, the resist pattern 33 and the aluminum film 30' thereon are removed, and the resist pattern 33 is further removed and the unnecessary molybdenum film 29 is etched, as shown in FIG.
The shape shown in is obtained. In addition, the molybdenum film 29
It uses high melting point metals such as and their silicides,
Since the substrate silicon can be selectively removed by etching, there is no need to thicken the wiring pattern in the contact hole portion in consideration of the alignment margin. That is, as shown in the plan view of FIG. 8, it is possible to use a wiring pattern having the same width as the contact hole, which is advantageous for high integration. In short, the present invention can be implemented with various modifications without departing from the gist thereof.

[Brief explanation of drawings]

1 and 2 are cross-sectional views for explaining the problems of the conventional method, respectively. FIG. 7 is a sectional view for explaining the modified example, and FIG. 8 is a plan view for explaining the modified example. 21...Silicon substrate (semiconductor substrate), 22...
...Field oxide film, 23...Gate electrode, 24
...gate oxide film, 25,26...n ⁺ diffusion layer,
27... Silicon oxide film (insulating film), 28... Contact hole, 29... Molybdenum film (first conductor film), 30... Aluminum film (second conductor film), 31... N-well, 32 ... p ⁺ diffusion layer.

Claims (1)

[Claims] 1. A step of forming a contact hole in a predetermined portion of an insulating film deposited on a semiconductor substrate that has been subjected to an element forming step, and a step of forming a contact hole on a predetermined portion of the insulating film and substrate using a vapor phase growth method. A step of depositing a first conductor film made of a melting point metal or a high melting point metal silicide, a step of depositing a second conductor film on the first conductor film, and a mask on the second conductor film. After forming the pattern, the second conductor film is selectively etched by anisotropic etching using the pattern as a mask, and then the first conductor film is etched by isotropic etching using the second conductor film as a mask. A method for manufacturing a semiconductor device, comprising the step of selectively etching. 2. The semiconductor device according to claim 1, wherein the film thickness D of the first semiconductor is set to D<A/3, where A is the minimum dimension of the contact hole. manufacturing method. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the second conductor film is made of aluminum or an aluminum alloy.