JPH057863B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for taper etching a semiconductor substrate used in an element isolation process or the like.

[Technical background of the invention]

As an element isolation technology for semiconductor devices such as ICs, especially silicon semiconductor devices using silicon,
The LOCOS method, which selectively oxidizes the surface of a silicon substrate to form an element isolation oxide film, has been commonly used in the past. However, device separation using the LOCOS method has the problem of large dimensional conversion differences due to the formation of bird's beaks, making it unsuitable for microfabrication.
For this reason, manufacturing of high-density devices that require a high degree of microfabrication requires element isolation technology with smaller dimensional conversion differences. One method is the BOX method, in which the element isolation region of the silicon substrate is etched into a tapered shape with the sidewalls expanding upward, and the etched groove is filled with CVD-SiO ₂ to form a buried oxide film. Are known.

By the way, one of the methods for taper etching a silicon substrate in the BOX method mentioned above is as follows.
Anisotropic plasma etching (RIE) is known in which a gas species that forms non-volatile products upon reaction with silicon is mixed into a reaction gas. In this conventional method, etching of silicon by plasma and deposition of the non-volatile products (mainly at the corners of the groove bottom) proceed simultaneously, resulting in the formation of tapered sidewalls.

[Problems with the Inventive Technique] As mentioned above, taper etching of silicon substrates conventionally performed using anisotropic plasma etching utilizes the deposition of non-volatile products within the etched surface. This non-volatile product is simultaneously deposited on the inner walls of the etching reaction chamber. As a result, the etching characteristics change over time, such as a decrease in the silicon etching rate and deterioration in the uniformity of the etching rate, resulting in poor etching reproducibility and problems in that the number of wafers that can be etched continuously is limited.

In addition, in order to restore the etching characteristics, the etching reaction chamber must be frequently cleaned to remove deposits, which poses a problem of poor mass productivity.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and is an etching method that performs taper etching on a silicon substrate using only dry etching, with excellent dimensional control. An etching method is provided.

[Summary of the invention]

A method for manufacturing a semiconductor device according to the present invention includes the steps of: covering a silicon substrate with a silicon oxide film, depositing a polycrystalline silicon layer on the silicon oxide film, and then implanting impurity ions into the polycrystalline silicon layer;
A step of forming a resist pattern having a predetermined opening on the ion-implanted polycrystalline silicon layer, and dry etching the polycrystalline silicon layer under isotropic etching conditions using the resist pattern as a mask. a step of forming an aperture portion whose end surface expands and tapers upward;
After removing the resist pattern, the polycrystalline silicon layer is removed by anisotropic plasma etching to form an opening with a tapered end surface in the silicon oxide film, and the silicon substrate is exposed in the opening. A side wall is formed on the silicon substrate by exposing the surface and etching the silicon substrate using anisotropic plasma etching under etching conditions in which the tapered end face of the opening gradually recedes using the silicon oxide film as a mask. The method is characterized by comprising a step of forming a concave groove that widens and tapers upward.

The above-mentioned constituent elements of the present invention can be divided into two components. That is, one is the process of forming an opening with a tapered end face in the silicon oxide film, and the other is the process of forming an anisotropic pattern on the silicon substrate using the silicon oxide film with the opening as a mask. This is the process of applying plasma etching. The former process utilizes the fact that the way a polycrystalline silicon layer into which ions have been implanted is etched changes due to the influence of a damaged layer. In other words, the polycrystalline silicon layer is easily etched in the lateral direction due to the damage layer caused by ion implantation, so when selective etching is performed using dry etching under isotropic etching conditions, the etched end surface becomes a tapered layer that expands upward. It becomes a surface. Therefore, by patterning the underlying silicon oxide film by etching using the polycrystalline silicon layer as a consumable mask, the tapered surface formed in the polycrystalline silicon layer is transferred to the end face of the silicon oxide film pattern. .

On the other hand, in the latter process, the silicon oxide film pattern with the tapered end face is used as a consumable mask, and the underlying silicon substrate is anisotropically etched by RIE while the end face of the mask is retracted. This forms an etched groove with tapered side walls. At that time, the selection ratio is maintained by masking the silicon oxide film, so
Grooves deeper than the mask film thickness can be formed. Further, since the taper angle of the side wall of the etching groove changes depending on the etching selection ratio, any desired taper angle can be obtained by changing the etching selection ratio.

As described above, in the method of the present invention, taper etching of a silicon substrate can be performed without involving non-volatile reaction products as in the conventional method, so that problems that have conventionally occurred can be avoided.

[Embodiments of the invention]

An embodiment of the present invention will be described below.

(1) First, specific resistance 6 to 8 Ω・cm, diameter 5 inches,
After depositing a SiO ₂ film 2 with a thickness of 4500 Å on a P-type silicon substrate 1 with a plane orientation of (100) by vapor phase growth (CVD), it was deposited in an oxygen gas atmosphere in a diffusion furnace heated to 850°C. Heat treatment was performed for 40 minutes. Subsequently, a polycrystalline silicon layer 3 with a thickness of 4000 Å was deposited by low pressure vapor deposition (LPCVD), and then the polycrystalline silicon layer was deposited at an acceleration voltage of 40 keV and a dose of 3×10 ^-5 atoms/cm ² . Phosphorus was ion-implanted (as shown in FIG. 1A).

(2) Next, a positive photoresist was applied and exposed and developed to form a resist pattern 4 having openings 5 on the area to be etched (as shown in FIG. 1B). Next, using the resist pattern 4 as a mask, dry etching was performed by microwave discharge using Freon gas, and the polycrystalline silicon layer 3 was etched under isotropic etching conditions resulting in 20% overetching. As a result, a polycrystalline silicon pattern 3' having openings at positions corresponding to the openings 5 of the resist pattern 4 was formed (as shown in FIG. 1C).

Note that a damaged layer is formed in the polycrystalline silicon layer 3 by the previous ion implantation, and the etching rate in the lateral direction is increased due to the influence of the damaged layer. Therefore, in the above etching, etching was not performed isotropically, but an etched end face having an inclination of 30°±5° as shown in the figure was formed.

Further, the etching selection ratio between the polycrystalline silicon layer 3 and the silicon oxide film 2 is 20:1, and the thickness of the silicon oxide film etched during 20% over-etching is 50 Å or less.

Furthermore, when the dimensional conversion difference was examined using a SEM (scanning electron microscope), it was found that the difference between the dimensions of the resist pattern 4 and the dimensions of the polycrystalline silicon pattern 3' was controlled within 0.10 μm.

(3) Next, the resist pattern 4 was removed using a barrel-type ashing device using oxygen gas (as shown in FIG. 1D).

Subsequently, anisotropic etching was performed using a reactive ion etching device (RIE device) with a 13.56 MH high frequency power source using Freon gas as a reaction gas. At this time, the etching selection ratio between the polycrystalline silicon pattern 3' and the silicon oxide film 2 is 1:1, and after the polycrystalline silicon pattern 3' is completely removed, the etching conditions are such that an additional 10% over-etching is performed. Set. Since the etching selection ratio is 1:1, as this RIE etching progresses, the shape of the polycrystalline silicon pattern 3' is transferred to the silicon oxide film 2, and the taper angle of the end face is 30°.
A silicon oxide film pattern 2' having an angle of ±5° was formed (as shown in FIGS. 1E and F).

The thickness of the silicon oxide film pattern 2' was about 4000 Å due to the 10% overetching, and the silicon single crystal substrate 1 was also etched by about 500 Å. Further, the difference in dimension change from the polycrystalline silicon pattern 3' to the silicon oxide film pattern 2' could be controlled to ±0.05 μm.

(4) Next, the silicon oxide film pattern 2' was used as a consumable mask, and Freon gas was used as a reactive gas.
Anisotropic etching of approximately 1 μm was performed on the silicon substrate 1 using an RIE apparatus equipped with a 13.56 MH high frequency power source. Although it depends on the etching selectivity, since RIE is performed under conditions where the silicon oxide film pattern 2' becomes a consumable mask, the silicon oxide film pattern 2' is also etched back as the silicon substrate is anisotropically etched. . As a result, the anisotropic etching of the silicon substrate progresses while the tapered end surface of the mask 2' gradually recedes, and the side surfaces of the etching grooves formed in the silicon substrate become tapered surfaces that widen upward. (Illustrated in Figure 1 G and H).

Incidentally, the taper angle of the side surface of the etching groove formed in the silicon substrate 1 changes depending on the etching selectivity of RIE. Therefore, we changed the conditions related to the etching selectivity to obtain the same results as above.
When RIE was performed and the taper angle and the thickness of the silicon oxide film 2' etched until the silicon substrate was etched by 1 μm were investigated, the results shown in FIG. 2 were obtained. In the figure, the solid line curve represents the relationship between taper angle/selectivity ratio, and the broken line curve represents the relationship between SiO ₂ etching amount/selectivity ratio. As shown in this result, if the selection ratio is 3.0±0.5, the taper angle can be set to 60°±5°,
Furthermore, by varying the selection ratio, any desired taper angle could be obtained. However, if the selection ratio is changed, the amount by which the silicon oxide film pattern 2' is etched also changes, so it is necessary to set the silicon oxide film pattern 2' to an appropriate thickness accordingly.

(5) Finally, the remaining silicon oxide film pattern 2' was removed using an HF-based etching solution to obtain a silicon substrate having etched grooves with tapered side walls (as shown in FIG. 1I). After that, the conventional
By performing the same method as the BOX method, CVD-SiO ₂ is buried in the etching groove 6, and an element isolation structure can be obtained.

In addition, prior to etching with HF solution,
By thermally oxidizing the surface of the etching groove 6 by several hundred Å and then removing all the oxide film with HF, it is possible to remove the damaged layer formed on the surface of the etching groove of the silicon substrate by RIE.

According to the above embodiment, excellent dimensional controllability can be obtained when etching grooves 6 with tapered sidewalls are formed in sidewalls 1 of a silicon substrate, and problems in conventional methods can be solved.

That is, since non-volatile products are not generated during RIE, the reaction products do not accumulate in the etching reaction chamber and reduce the etching rate.
Processing uniformity and mass productivity can be improved. Furthermore, since the number of times the etching reactant is washed is reduced, the operating efficiency of the apparatus can be improved and productivity can be greatly improved.

[Effects of the Invention] As described in detail above, according to the present invention, when etching a silicon substrate with tapered sidewalls in an element isolation process, etc. when manufacturing a semiconductor device, only dry etching is used to improve the dimension. Remarkable effects such as etching processing with excellent control and greatly improved reproducibility and mass productivity can be obtained.

[Brief explanation of drawings]

FIGS. 1A to 1I are cross-sectional views showing step by step the manufacturing process according to an embodiment of the present invention, and FIG. 2 shows taper etching on the silicon substrate from the state shown in FIG. 1F using the silicon oxide film pattern as a mask. FIG. 3 is a diagram showing the relationship between the etching selectivity, the taper angle of the etched end face, and the amount of silicon oxide film pattern etching. 1...Silicon substrate, 2...Silicon oxide film,
2'...Silicon oxide film pattern, 3...Polycrystalline silicon layer, 3'...Polycrystalline silicon pattern,
4...Resist pattern.

Claims (1)

[Claims] 1 A step of covering a silicon substrate with a silicon oxide film, depositing a polycrystalline silicon layer on the silicon oxide film, and then ion-implanting impurities into the polycrystalline silicon layer; By forming a resist pattern having a predetermined opening on the top, and dry etching the polycrystalline silicon layer under isotropic etching conditions using the resist pattern as a mask, the end face is expanded upward. After forming a tapered opening and removing the resist pattern,
forming an opening with a tapered end surface in the silicon oxide film by removing the polycrystalline silicon layer by anisotropic plasma etching, and exposing the surface of the silicon substrate through the opening; Using the silicon oxide film as a mask, the silicon substrate is etched by anisotropic plasma etching under etching conditions in which the end face of the tapered opening gradually recedes, so that the side wall of the silicon substrate expands upward and tapers. 1. A method of manufacturing a semiconductor device, comprising the step of forming a groove.