JPH05800B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention generally relates to a method of driving a Josephson storage circuit that stores at least one piece of information in the form of a circulating current. More specifically, reading stored binary information non-destructively (hereinafter referred to as NDRO)
Concerning the Josephson memory circuit that can be used. More particularly, the present invention provides that in the storage device one of the pairs of branches forming a superconducting closed loop is
Josefson with two write gates
This relates to the NDRO storage circuit. More specifically, the present invention relates to a method for driving a Josephson NDRO memory circuit, in which the second gate is disposed within the control line of the first gate in the memory circuit.

FIG. 1 is a diagram for explaining one of the conventional examples of Josephson NDRO storage circuit. In this example, the switch element 8 and the switch element 9 each have the characteristics shown in FIG. It was necessary to use two levels of current.

That is, switch elements 8 and 9 have the following characteristics (a) and (b), respectively.

A Control current (1-K) I _Y and (1-K) I _Y +Icirc
Bias current I in zero voltage state for _X1 region and control current (1-K) I _Y Bias current I in zero voltage state and in voltage state for _Y +Icirc _X0 region (Fig. 2b) (b) With _the bias current I _X0 as the control current, the bias current is KI _Y with respect to the control current _I , and _{the bias} current is
It is in a voltage state both in the case of KI _Y and also in the case of KI _Y −Icirc (Fig. 2a). However, I _Y is the bias current flowing into the column line 5 and flowing into the superconducting closed loop 2, and K is (min. It is a circuit constant determined from (self-inductance of branch 4)/(sum of self-inductance of branches 3 and 4),
Icirc is the circulating current held in the superconducting closed loop 2, I _X0 is the current flowing through the row line 7 during reading, I _X1 is the current flowing through the row line 7 during writing, and _I This is the control current that flows. In order to cause the circulating current _Icirc to flow in the superconducting closed loop 2 regardless of the initial state, bias current I _Y and control currents _I Then, the switch element 8 is temporarily put in a voltage state, and the remaining current I _Y −Imin obtained by subtracting the lowest drive current Imin of the switch element 8 from I _Y is passed through the branch 4, and then the bias current I _Y and control current _I Set all I _Y ′ to 0. As a result, a circulating current exists within the superconducting closed loop 2.
Icirc is retained. In order to prevent the circulating current Icirc from flowing in the superconducting closed loop 2 regardless of the initial state, the bias current I _Y is set to ₀ and only the control currents _I If there is already a circulating current Icirc in 2, Icirc
When the circulating current Icirc is already 0, there is no current flowing into the superconducting closed loop 2, so if _the control currents _I not exist.

In order to read whether or not the circulating current Icirc is flowing in the superconducting closed loop 2, a bias current I _Y and a control current I _X0 are simultaneously passed through the column line 5 and the row line 7, respectively. As a result, if the circulating current Icirc is maintained, the current flowing in branch 4 is (1-K)I _Y
+Icirc, and the switch element 9 enters the voltage state according to the control characteristics shown in Figure 2b, or if the circulating current Icirc is not maintained, the current flowing in the branch 4 is (1-K)I _Y , and the switch element 9 becomes the Figure 2b
The zero voltage state is maintained by the control characteristics shown in Figure 1, and these two states are discriminated.

During the write process, the switch element 9 maintains a zero voltage state with the control characteristics shown in FIG. 2b, while in the read process, even if current _IX0 is applied to the row line 7, the switch element 8 maintains the control characteristics shown in FIG. 2a. The zero voltage state is maintained by

That is, in the prior art, it was necessary for the current level to be applied to the row line to be different between writing and reading.

SUMMARY OF THE INVENTION An object of the present invention is to provide a novel method for driving a Josephson memory circuit, which simplifies its operating mechanism while maintaining conventional circuit functions.

According to the present invention, a superconducting closed loop consisting of a first branch and a second branch, a first switch element arranged in the first branch and capable of flowing Josephson current, and a superconducting closed loop comprising a first branch and a second branch; a plurality of control lines arranged so as to be electromagnetically coupled to the element; and within at least one of the control lines, a Josephson arranged so as to be electromagnetically coupled to the second branch. a second switch element capable of passing a current; the first switch element is used as a write gate to store lead information in the superconducting closed loop as circulating currents flowing in different directions or as the presence or absence of circulating current; In the Josephson memory device using the first switch element as a read gate, the second switch element maintains a zero voltage state with respect to the bias current in the first direction regardless of the presence or absence of the circulating current; With respect to the bias current in the opposite direction to the first direction, the second switch has an asymmetric characteristic in which it maintains a zero voltage state when there is no circulating current and becomes a voltage state when there is the circulating current. There is obtained a method of driving a Josephson memory circuit characterized in that the direction of the current flowing through the control line of the first switch element including the element is driven to be different during writing and reading.

The present invention will be described in detail below with reference to the drawings.
The principle of the present invention is based on the control characteristics shown in _{Fig . 3a} and _b , respectively. _{When I X} = _-I Characteristics having positive _and negative bias current I _X0 regions in a voltage state ( _Fig . 3b) When the bias current is KI _{Y and} when KI _Y −Icirc _, it is in a zero voltage state _, and with respect to the control current _I The two switch elements having the characteristic (FIG. 3a) in the state of FIG. Further, control lines 6 and 7 are provided which are electromagnetically coupled to the write switch 8, and one of the control lines 7 is connected to the second branch 4 that constitutes the superconducting closed loop 2. The purpose of the present invention is to provide a read gate using a switch element 9 which is coupled to a switch element 9 and has a characteristic A. However, I _Y is the bias current flowing through the column line 5 and flowing into the superconducting closed loop 2, and K
is a circuit constant determined from (self-inductance of branch 4)/(sum of self-inductance of branches 3 and 4), Icirc is the circulating current maintained in superconducting closed loop 2, and _I -I _xp is the current flowing through the row line 7 during readout, and I _Y ' is the control current flowing through the column line 6 during reading.

Next, an example will be given and explained. FIG. 4 shows a 2×2 array of Josephson NDRO storage devices to be driven in a diagram for explaining the present invention.

Switch elements 8 and 9 are shown in FIG. 3a and b, respectively.
It is designed to have the control characteristics of Circulating current in superconducting closed loop 2 of A regardless of the memory state of A
To flow Icirc, bias current I _Y and control current acting on memory cell 1 including superconducting closed loop 2 of A
_{I _}
According to the control characteristics of the switch element 8 of sink A from 11, the switch element 8 of A is temporarily put in a voltage state, and the remaining current I _Y −Imin obtained by subtracting the minimum drive current Imin of the switch element 8 of A from I _Y is branched to A. 4, the bias current I _Y and control currents I _X and I _Y ' are all set to zero. As a result, the circulating current Icirc is maintained within the superconducting closed loop 2 of A.

In order to prevent the circulating current Icirc from flowing in the superconducting closed loop 2 of A regardless of the storage state of A, the memory cell 1 of A is
Only control currents I _X0 and I _Y ' are allowed to flow through the row line 7 and column line 6 that act on A, respectively, and no bias current I _Y is caused to flow through the column line 5 that affects A. As a result, the switch element 8 of A becomes in a voltage state, and if there is already a circulating current Icirc in the superconducting closed loop 2, Icirc
is set to 0, and if the circulating current Icirc is already 0, then A
Since there is no current flowing into the superconducting closed loop 2, if the control currents _IX and _IY ' are then all set to 0, no circulating current will exist in the superconducting loop 2. In the above process, even if _IX0 is applied to the row line 7 of A, the switch element 9 of A maintains a zero voltage state due to its control characteristics. In order to read whether or not the circulating current Icirc is flowing in the superconducting closed loop 2 of A, the bias current I _Y and the control current _-I It flows to the related column line 5 and row line 7. As a result, if the circulating current Icirc is maintained, A
The current flowing in the branch 4 of is (1-K)I _Y +Icirc, and the switch element 9 of A becomes a voltage state due to the control characteristics shown in Fig. 3b, or the circulating current Icirc
If the current is not maintained, the current flowing in the branch 4 of A is (1-K)I _Y , and the switch element 9 maintains the zero voltage state according to the control characteristics shown in Figure 3b, and these two states become A. Discrimination is made by the associated detector 13.
In this case, even if a current -I _X0 is applied to the row line 7 related to A, the switch element 8 of A will not switch due to the control characteristics shown in FIG. 3a. As a result of the above, in the Josephson NDRO memory circuit, it is possible to maintain the function of the memory circuit by reducing the number of wiring lines and the number of corresponding power supplies, and to simplify the circuit operation mechanism.

FIG. 6 is a diagram for explaining another preferred embodiment of the present invention, in which the binary information to be stored is 2×2 of the Josephson NDRO storage circuit according to the direction of the circulating current.
An array is shown. Switch elements 8 and 9 are designed to have the control characteristics shown in FIGS. 5a and 5b, respectively. Superconducting closed loop 2 of A regardless of the memory state of A
In order to flow clockwise Icirc (hereinafter referred to as +Icirc), a control current I _D is applied to the control line 6 and row line 7 related to A, and a bias current I _Y is applied to I _X0 and column line 5 related to A at the same time. According to the control characteristics of the switch element 8 of A, the switch element 8 of A is temporarily put in a voltage state, and the current I _Y −Imin obtained by subtracting the lowest drive current Imin of the switch element 8 of A from the bias current I _Y is applied to the branch 4 of A. After that, the control currents I _D and I _X and the bias current I _Y are all set to 0. As a result, +Icirc is maintained within the superconducting closed loop of A.

A counterclockwise circulating current Icirc (hereinafter referred to as −Icirc) is generated in the superconducting closed loop 2 of A regardless of the memory state of A.
In order to flow the control line 6 and row line 7 related to A.
A bias current -I _Y is simultaneously applied to the control currents I _D and _I A current obtained by subtracting the lowest driving current -Imin of the switch element 8 of A from I _Y (I _Y - Imin) is passed through the branch 4 of A, and then all of the control currents I _D and I _X and the bias current - I _Y are passed through the branch 4 of A. Set to 0. As a result, -Icirc is maintained within the superconducting closed loop of A. In the above two write processes, the switch element 9 maintains the zero voltage state due to the control characteristics shown in FIG. 5b.

To determine in which direction the circulating current Icirc is flowing in the superconducting closed loop 2 of A, a bias current I _Y is applied to the column line 5 related to A, and a readout current −I _X0 is applied to the row line 7 related to A. are simultaneously applied, and as a result, if +Icirc is maintained, a current of (1-K)I _Y +Icirc flows in branch 4 of A, and switch element 9 becomes in a voltage state according to the control characteristics shown in Figure 5b. When Icirc is maintained, a current of (1-K)I _Y -Icirc flows through the branch 4 of A, and the switch element 9 maintains a zero voltage state, and these two states are detected by the detector 15 related to A. It is distinguished by In this readout process, even if a current -I _X0 is applied to the row line 7 related to A, the switch element 8 of A is
There is no switching due to the control characteristics shown in .

Although the embodiments have been described above, the main part of the present invention is that the second
The memory function can be realized by changing the direction of the current flowing through the control line of the first gate including the gate during writing and reading.

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating one cell of a Josephson NDRO storage circuit for explaining the prior art and the present invention. FIGS. 2a and 2b are diagrams showing the control characteristics of the conventional switch element used in the cell of FIG. 1, respectively. FIG. 3 is a diagram showing control characteristics of a switch element for explaining one embodiment of the present invention. FIG. 4 is a diagram for explaining one embodiment of the present invention, and is a diagram for explaining an embodiment of the present invention.
FIG. 2 is a diagram showing two arrays. FIG. 5 is a diagram showing control characteristics of a switch element for explaining another embodiment of the present invention. FIG. 6 is a diagram illustrating a 2×2 array of Josephson NDRO storage circuits to illustrate another embodiment of the present invention. In the figure, 1 is a storage cell, 2 is a superconducting closed loop, 3 and 4 are branch circuits, 5 is a column line, 6 is a control column line, 7 is a row line, 8 and 9 are switch elements,
10, 11, and 12 are power supplies, and 13 is a detector.

Claims (1)

[Claims] 1. A superconducting closed loop consisting of a first branch and a second branch, a first switch element arranged in the first branch and capable of flowing Josephson current, and A Josephson current is passed through at least one of the plurality of control lines arranged so as to be coupled to the second branch electromagnetically. and a second switch element that is
The second switch element is used as a write gate to store binary information in the superconducting closed loop as circulating currents flowing in different directions or the presence or absence of the circulating current, and the second switch element is used as a read gate to drive a Josephson memory circuit. The second switch element maintains a zero voltage state with respect to the bias current in the first direction regardless of the presence or absence of the circulating current, and maintains a zero voltage state with respect to the bias current in the opposite direction to the first direction. It has an asymmetrical characteristic that maintains a zero voltage state when there is no circulating current and becomes a voltage state when there is a circulating current, and flows in the control line of the first switch element including the second switch element. A method for driving a Josephson memory circuit characterized by driving the current in different directions during writing and reading.