JPH0580174B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention particularly relates to an improved electronic device which is configured to have, for example, a timer function and is effectively applicable to various electronic equipment systems. The present invention relates to a programmable logic array configured as a single-chip semiconductor integrated circuit.

[Background Art] A programmable logic array is composed of an AND plane and an OR plane. A logic function is set on the AND plane, and the data input to the AND plane is processed with logical operations to form an OR plane. It is now being sent to A sequential logic circuit is constructed by feeding back the output data from the OR plane to the AND plane. In this case, the logic to be implemented is one that can be easily programmed and is effectively used, for example, in input/output circuits of large computer systems.

That is, a feedback loop is formed between the OR plane and the AND plane by, for example, an exclusive OR circuit and a flip-flop circuit,
The output from the OR plane is supplied to the AND plane, but in this case it is difficult to set functions such as a timer, so the effects of high-speed data processing in this programmable logic array are limited. Despite this, its scope of use is still limited.

[Problems to be Solved by the Invention] The present invention has been made in view of the above-mentioned points. For example, it is possible to easily set a timer function and perform logical operation processing on input data. , a programmable logic array that can be effectively applied not only to the electronic equipment set up above, but also to more electronic equipment systems, and in particular to a state that can be effectively realized with a single-chip semiconductor integrated circuit. This is what we are trying to provide.

[Means for Solving the Problems] That is, the programmable logic array according to the present invention executes logical operation processing based on the input data on the AND plane to which input data is supplied, and the processed data is The signal is supplied to the OR plane and output from the OR plane, and a timer means is set to be activated in response to the rise of the output signal from the OR plane. In this timer means, a signal is supplied to the AND plane while measuring the elapse of a specified time from the rise of the output from the OR plane.

[Operation] In the programmable logic array as described above, a feedback loop having a timer function is formed between the AND plane and the OR plane. Therefore,
Logical operation processing with a timer function is executed in order, and after a specified time has elapsed since the output is generated from the OR plane, the next logical operation processing is executed on the AND plane. The present invention can be implemented and effectively applied in various electronic equipment systems.

[Embodiment of the Invention] An embodiment of the invention will be described below with reference to the drawings. The attached drawings show the configuration, and the main body element 11 portion of the programmable logic array is constituted by an AND plane 12 and an OR plane 13. For example, 4-bit input signals input from input terminals 14a-14d are supplied to the AND plane 12 via 1-bit decoders 15a-15d, respectively. Then, in this AND plane 12, a predetermined logical operation process is executed in response to a program command set based on the input data, and the processed data is supplied to the OR plane 13 and output. The signals are output from output terminals 17a to 17c via buffers 16a to 16c. A first feedback loop 2 formed by an exclusive OR circuit and an SR flip-flop circuit 19 is connected between the OR plane 13 and the AND plane 12.
0 is formed.

Further, a second feedback loop 21 further provided with a timer function is formed between the OR plane 13 and the AND plane 12. In this second feedback loop 21, the output signal line A from the OR plane 13 is reset-controlled by the RS flip-flop circuit 22 connected to the reset terminal R, and the output signal Q of this flip-flop circuit 22 when the flip-flop circuit 22 is set. A 4-bit counter 23 for example, an AND plane 24 that decodes the output signal of the counter 23, and a 1-bit decoder 25 that inputs the output signal from the AND plane 24 to the AND plane 12 of the programmable logic array 11. It is composed of.

Here, the main body element 11 section and the first and second feedback loops 20 and 21 of the programmable logic array are configured as a single-chip semiconductor integrated circuit, and the AND plane 12 of the main body element 11 section is configured as a single-chip semiconductor integrated circuit. and counter 2
The three AND planes 24 are adapted to be programmed simultaneously by similar means. Then, the AND plane 24 generates an output signal on the signal line B corresponding to the count value specified by the counter 23, and this signal is supplied to the decoder 25, and the counter 23 further performs counting. When the counting reaches the next specified count value, an output signal is generated on the signal line C to set and control the flip-flop circuit 22.

The counter 23 is incremented by a clock pulse signal generated by an oscillator 26. Although the oscillator 26 may be integrated into the single-chip semiconductor integrated circuit, it may be configured independently. It may also be configured separately and connected as an external circuit element.

That is, in the programmable logic array configured as described above, the input terminal 14a
Input data inputted from ~14d is decoded by decoders 15a~15d, respectively, and inputted to AND plane 12. In this AND plane 12, logical operation processing is executed according to a set program based on the input data and sent to the OR plane 13, and a part of this processed data is sent to an output buffer 16a. ~16c
It comes to be outputted from the output terminals 17a to 17c via. The delay time of output generation with respect to this input is, for example, about 50 nS, which allows arithmetic processing and output to be performed at a much higher speed than, for example, a microcomputer.

Further, the remaining part of the processed data is transmitted to the first and second feedback loops 20 and 21.
It comes to be returned to the AND plane 12 via .
A sequential logic circuit can be realized using this programmable logic array.

Here, the second feedback loop 21
Assuming a conventional case in which there is no such function, it is not possible to execute calculation operations including a timer function, such as turning on after 1 second and turning off after 3 seconds. However, if the timer function is set by the second feedback loop 21, the above-mentioned arithmetic processing will also be executed.

That is, when the output line A output signal of the OR plane 13 of the main body element 11 of the programmable logic array is generated and becomes a high level state, the flip-flop circuit 22 is fixed in the reset state, and the reset state of the counter 23 is released. ,
This counter 23 is operated by a clock pulse signal from an oscillator 26. When the count value of this counter 23 reaches a specified value, the signal line B is selected by the AND plane 24 and becomes high level, and a signal is input from the 1-bit decoder 25 to the AND plane 12. .

Then, when the counter 23 is further incremented and reaches the next specific counting state, the signal line C is selected and the flip-flop circuit 22 is set, and the reset input of the counter 23 becomes high level. Counting operation is now stopped. That is, a timer function is set by this counter 23, and the second feedback loop 21 having this timer function receives the output of the OR plane 13 and sends a signal to the AND plane 12 after a specified time has elapsed. It is something that comes to be supplied.

[Effects of the invention] As described above, the programmable
In the case of logic arrays, the timer function is set during the process of setting the logic operation processing operation, so it can not only be used for input/output circuits of large computer systems, but also for general use. This programmable system can be effectively applied to small and medium-sized electronic control systems currently in use.
This makes it possible to effectively expand the range of applications of logic arrays.

[Brief explanation of the drawing]

The accompanying drawing is a circuit configuration diagram for explaining a programmable logic array according to an embodiment of the present invention. 11... Main body element of programmable logic array, 12... AND plane, 13... OR plane, 14a-14d... Input terminal, 17a-17
c... Output terminal, 20... First feedback loop, 21... Second feedback loop (with timer function).

Claims (1)

[Claims] 1. A first AND plane that performs predetermined logical operation processing based on input data, an OR plane that outputs processed data calculated on this AND plane, and a rising edge of the output from this OR plane. Detected,
a timer means that is activated in response to the rise of the output and measures the elapse of a specified time; the timer means is provided with a counter that is activated in response to the rise of the output from the OR plane; A second AND plane is provided with the output signals from each stage of the counter, the second AND plane being programmed with the first AND plane to detect a count value corresponding to a specified time. The programmable computer is characterized in that the output from the second AND plane is supplied to the first AND plane, and data processing having a timer function is executed.
logic array.