JPH0581090B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a frequency converting synthesizer,
PLL (Phase Locked) is widely used for phase shifting, motor phase control, etc.
The present invention relates to a PLL fluctuation compensation device that improves the accuracy of PLL (Loop) circuits.

Conventional technology In recent years, PLL has been used not only for synthesizers and motor phase control in electronic musical instruments and transceivers, which have been used for a relatively long time, but also for the computerization, as represented by CDs (compact discs). Also, in the field of data extraction clock generation circuits for digital signal recording and video processing,
It has begun to be widely used as a clock generation circuit for analog-to-digital or digital-to-analog conversion.

Below, with reference to the drawings, the conventional
An example of PLL will be explained.

FIG. 6 shows a general configuration example of a conventional PLL circuit. In FIG. 6, reference numeral 1 denotes a voltage controlled oscillator (hereinafter referred to as VCO), whose oscillation frequency is controlled by a control voltage input to point a, and outputs an oscillation output with a frequency proportional to this to point b. A type that changes the bias of an oscillation circuit using C (capacitor), R (resistance), or L (inductance) is common, but the variable range is small especially in devices that require precision. In some cases, a crystal resonator or a resonator with similar performance is used. In addition, in the motor phase control system,
Frequency generator (FG) mounted on the motor shaft
A pulse generator (PG) that generates a pulse once per rotation is equivalent to a VCO.

Reference numeral 2 denotes a frequency divider, which divides the output of the VCO 1 into a frequency of 1/N as necessary.

Reference numeral 3 denotes a pulse generator which determines the reset width of the triangular wave generating circuit 4, and the output of the frequency divider 2 may be directly input to the triangular wave generating circuit 4. As the triangular wave generating circuit 4, a time constant charging/discharging circuit using C and R, a constant current charging/discharging circuit, or the like is generally used.

5 is a sample pulse generation circuit that pulses the reference input input to Fi, which is supplied to a sample and hold (hereinafter abbreviated as SH) circuit 6, which samples and holds the triangular wave output from the triangular wave generator 4. , an output signal obtained by comparing the phases of the output of the frequency divider 2 and the reference input Fi is obtained at point c.

Reference numeral 7 denotes a loop filter that determines the responsiveness required of the PLL of this example, the amount of noise suppression, etc., and its output is input to the addition point of the adder 8.

9 is a bias circuit, which connects the reference input Fi and VCO
This is used when it is necessary to adjust the phase with the output F1 of the frequency divider 1 or the output F2 of the frequency divider 2. 10 is an amplifier, which together with the aforementioned filter 7 is a PLL.
Determine the response characteristics of Moreover, when driving a motor, it plays a role as a power amplification circuit.

Next, a specific example of the above-mentioned phase comparison part will be explained in the seventh section.
A brief explanation will be given with reference to FIG. 8 and its waveform example.

A1 is an operational amplifier which functions as a constant current limiter and an integrator, and when the switch SW1 is turned on by the output of the pulsing circuit 3, the charged capacitor C1 is reset. When switch SW1 is turned off, A1 output Vt
is the potential Vr of the non-inverting input of A1 and the resistance of the inverting input
R1, determined from the above C1, is expressed by the following formula,
Generates an output proportional to time.

Vt=Vr+{Vr/(R1×C1)}×t t: Time after C1 reset This Vt becomes a sawtooth wave (triangular wave) as shown in Figure 8, and is a reference waveform for converting time or phase into voltage. becomes.

The switch SW2 is a sampling switch, and is controlled by the output of the sample pulse generation circuit 5 that pulses the input reference signal, and a voltage is applied to the hold capacitor C2 according to the phase of the VCO or the frequency divider and the input reference signal. is output to the output Vo of hold amplifier A2. The situation when the phase changes is shown in FIG. 8 as the sample pulse Sp and the output voltage Vo.

Here, as a phase comparator, it is resistant to noise and
Although the sample-and-hold circuit type with good detection frequency characteristics has been described, other types of phase comparators such as EX-OR circuits and charge pumps can be used.

Since the configurations other than the PLL operation and the phase comparator are the same, their explanation will be omitted here.

With the PLL configured in this way, the frequency N times the reference input Fi is sent to the output F1 of the VCO1, and
An output synchronized with Fi and whose phase is shifted by an arbitrary amount can be obtained as the output F2 of the frequency divider 2.
By using the outputs of F1 and F2 as the clocks for extracting the digital data mentioned above, it is possible to realize stable data reading that is not easily affected by the speed of the recording medium (disc, etc.).

In addition, in the case of motor phase control, rotation control with extremely small speed fluctuations is required, and in video equipment, etc., the phase during one rotation is kept in a constant phase relationship with the reference input Fi, and the input image and output are This makes it possible to synchronize images.

Problems to be Solved by the Invention However, in the above configuration, the VCO
Even if a high-precision crystal resonator is used in 1, constant fluctuations due to temperature and humidity of C and R used in the triangular wave generation circuit of the phase detection stage, temperature drift of constant current source and amplifier, power supply voltage and earth point Frequency fluctuation (jitter) of the outputs F1 and F2 of VCO1 and frequency divider 2 mentioned above due to the influence of ripple fluctuation etc.
This has the problem of causing fluctuations in the amount of phase shift and decreasing operational stability and accuracy in the various fields of use mentioned above.

In view of the above-mentioned problems, the present invention provides extremely stable output frequency characteristics and phase shift characteristics even when there are fluctuations in the characteristics of the circuit elements due to the environment such as temperature and humidity, and fluctuations in conditions within the circuit such as fluctuations in the power supply. An object of the present invention is to provide a PLL fluctuation compensation device having the following.

Means for Solving the Problems In order to solve the above problems, in the present invention, a signal that always has a constant phase relationship with the output of the VCO whose phase is compared with a reference input is obtained from the output of the VCO (for example, a signal with an antiphase signal, output signal of an appropriate frequency-divided wave, etc.), the correction signal obtained by phase comparison with the output of the VCO is combined with the original phase comparison output, and the VCO is controlled by the difference signal. It is something that

Furthermore, the present invention also proposes a method for compensating for the characteristic fluctuations of the triangular wave generating circuit described above using the correction signal.

Effects According to the present invention, with the above-described configuration, an extremely stable output of the PLL circuit can be obtained in a very simple manner by compensating for fluctuations in detection in the phase comparison stage described above. In addition, by dramatically improving the accuracy in the detection stage of phase comparison with the present invention, it is possible to use commonly used oscillation circuits such as C, R, and L.
Even in the case of a PLL circuit using a VCO, stable PLL characteristics can be obtained by appropriately setting the loop gain.

Embodiment Hereinafter, a PLL fluctuation compensation device according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows the first embodiment of the present invention.
This figure shows the configuration of a PLL fluctuation compensation device. In FIG. 1, blocks having the same functions as those in FIG. 6 of the conventional example are given the same numbers and their explanations will be omitted here.

1 is a VCO, the output of which is input to a first phase comparator 12 and an inverter 11. 13 is a second phase comparator, which is originally used for phase comparison.
A signal with a phase opposite to that of the output of the VCO 1 is supplied to a second phase comparator 13 having the same characteristics as the first phase comparator 12.
A difference signal of the output of is taken, and a signal from which environmental fluctuation factors in the phase comparison stage are removed is supplied to the loop filter 7 described above. As a result, the phase comparison output that has compensated for fluctuation factors in the detection stage related to temperature, humidity, power supply fluctuations, etc., is sent to the VCO 1 through the adder 8 and the amplifier
can be supplied to

In this manner, by providing a sub-loop that compensates for fluctuations in the phase comparison stage itself, it is possible to realize a PLL circuit in which the influence of fluctuations in the phase comparison stage is extremely small.

Furthermore, depending on the amount of phase shift to be realized, it is also an effective means to insert an attenuator between the second phase comparator 13 and the comparator 14. Here, the phase comparator is not limited to a sample-and-hold type, and other types of circuits such as EX-OR circuits and charge pumps are also effective.

Next, a second embodiment of the present invention will be described using FIG. 15 is a frequency divider similar to frequency divider 2, but also plays the role of a phase shifter that generates an output F3 having a different phase from the original output F2. 16
is a pulsing circuit, which preferably has exactly the same characteristics as the pulsing circuit 3. Reference numeral 17 denotes a second sample-and-hold circuit, which also desirably has the same characteristics as the sample-and-hold circuit 6. The triangular waves supplied to both sample and hold circuits 16 and 17 are exactly the same, and the comparator 14 takes the difference signal between the output of the second sample and hold 17 and the output of the first sample and hold 6. This makes it possible to handle signals with extremely reduced phase comparator fluctuations.
A highly stable PLL circuit can be realized using extremely simple means.

The above operation will be explained using FIG. 9 using the main waveforms in FIG. 2. In the figure, from the top, S15 is the frequency divider 15, S3 is the pulse generator 3,
S16 is the pulsing circuit 16, S5 is the pulsing circuit 5,
S4 is triangular wave generation circuit 4, S17 is second S&H, S6
represents the output of the first S&H, and S14 represents the output of the comparator 14, respectively. Also, the left half of the figure is the temperature
The waveform of each part at 20℃, the right half shows the waveform of each part at 0℃.To make the operation easier to understand, the drift amount of the triangular wave generation circuit at 0℃ is emphasized, and the slope sensitivity is increased by about 50%. is showing. S3 is used to reset the triangular wave S4, and is supplied to a constant current circuit as shown in FIG. 7 to periodically generate the triangular wave S4. S16 is S3
In the case of the figure, S16 and S3 have a phase difference of π since they are generated by the reverse polarity pulse of the frequency divider 15.
S5 is a pulse supplied from the outside to synchronize VCO1. Here, S5 is set at almost the same position as S16, which is the center of the triangular wave, and is treated as having jitter, which is a slight phase variation.
As shown in S17, the outputs of the second S&H at each temperature are the same because S16 and S3 are in phase, VR1=VR2, VR3=VR4. However, the output at different temperatures differs greatly, and in the case of the same figure, VR3>VR1. Also, it is input with almost the same phase as P1.
The output of the first S&H6 for P3, P2, and P4 increases by the amount that the slope sensitivity of the triangular wave increases, so that VP3>PV1 and VP4>VP2.

In a normal PLL, if the above condition occurs transiently, assuming that the VCO temperature fluctuation is small.
In response to the VCO, the phases of the triangular wave S4 and the pulse generator S5 change, and become stable at the points P3' and P4'. This point is the phase where the voltage is almost the same as that of VP1 and VP2, and if it is desired to maintain a constant relationship between the phases of S3 and S5, this amount of movement becomes the amount of variation in phase synchronization. Second
In the second embodiment of the present invention explained in the drawings, as shown in FIG. VCO via 10
As shown in the output of S14 in FIG. 9, even if the slope sensitivity of the triangular wave S4 fluctuates greatly, the voltage supplied to the VCO hardly fluctuates. As a result, S3 and
The phase of S5 can be maintained in a very stable and constant relationship. In the figure, the output of S14 to P2 and the output to P4 change slightly, but this is due to a fluctuation in the detection gain due to jitter, and the center of the operating point does not change. As described above, the smaller the difference between the operating point for phase synchronization and the phase sampled at the second S&H, the greater the effect.

As you can see in the above explanation, VCO or VCO
The signal to be synchronized with an external signal is frequency-divided and the phase is compared with the signal that always has a constant phase, and the output of detecting the amount of variation in the PLL is used to output the phase comparison between the signals to be synchronized. By separating and removing only the amount of variation using a differential, the phase of the external input and VCO can be kept extremely stable and constant.

The above explanation has been made regarding the variation in the slope sensitivity of the triangular wave, but the same reason is also valid for the variation in the oscillation frequency of the VCO.

FIG. 3 shows a third embodiment. It has almost the same configuration as the one in Figure 2, but the characteristics of the triangular wave generation circuit 4 are corrected by the output of the second sample and hold circuit 17, and the emphasis is placed on correction of the detection stage itself. It is something.

Specific methods of correction include using a FET instead of the resistor R1 in FIG. 7 and using a signal obtained by amplifying the output of the second sample-and-hold circuit 17 as the gate voltage, or Connect the resistor connected to the terminal to the terminal of the signal which amplified the output of the second sample hold circuit 17.
There are methods such as varying the current value supplied to C1. In addition, it is also possible to control Vr, C1, etc. in FIG.

4 shows a fourth embodiment in which the components are the same as those in FIG. 2, but the relationship between the input reference signal and the VCO is reversed, and the phase shift circuit 18 and
The configuration and operation are the same as those in FIG. 2, except that the pulse generator 19 is inserted on the reference input side. As the phase shift circuit 18, a memory, a delay line, etc. which is a delay element and is stable against temperature etc. is desirable, but a mono-multivibrator etc. which performs temperature compensation is also possible.

FIG. 5 shows a fifth embodiment. A peak hold circuit 20 is similar to those in FIGS. 2 and 4, but detects the peak of the output of the triangular wave generation circuit 4 instead of the phase-shifted sampling pulse.
By taking the difference signal between the output of the sample and hold circuit 6, which is the first phase comparison output, and the comparator 14, a phase comparison output with extremely small phase comparison errors caused by fluctuations in the detection stage can be obtained, resulting in a stable output. Na
It constitutes a PLL loop.

In addition, although each individual operation|movement was demonstrated above, the combination of two or more sets of the 1st to 5th Example is also possible, and can make it possible to further improve accuracy.

Effects of the Invention As described above, according to the present invention, a signal that always maintains the same phase is generated in the circuit separately from the signal whose phase is originally compared, and the phase is compared in the same way as the signal whose phase is originally compared. By controlling the VCO with a signal that differs from the original phase comparison output, or by providing a sub-loop that corrects the characteristics of the original phase comparator, various types of phase comparison stages, which are the most important in PLL, can be controlled. It is possible to extremely reduce the influence of fluctuation factors in the PLL, and to achieve a very stable PLL output frequency and phase.

[Brief explanation of the drawing]

FIGS. 1 to 5 show examples of the present invention, respectively.
A configuration block diagram of a PLL fluctuation compensation device, FIG. 6 is a configuration block diagram of a conventional PLL device, FIG. 7 is a circuit diagram of a specific circuit example of a phase comparison stage, and FIG.
FIG. 9 is an operational waveform diagram of the main part of the figure, and a time chart showing the operation of the present invention. 1...VCO, 2...Frequency divider, 3, 5, 16,
19...pulsing circuit, 4...triangular wave generation circuit,
6, 17...Sample hold circuit, 7...Filter, 8...Adder, 9...Bias circuit, 1
0...Amplifier, 11...Inverting circuit, 12, 13...
... phase comparator, 14 ... comparator, 15 ... frequency divider with phase shift circuit, 18 ... phase shift circuit.

Claims (1)

[Claims] 1. Phase comparison between a voltage controlled oscillator whose oscillation frequency is changed by an applied control voltage, the output of the voltage controlled oscillator or its frequency-divided output, and an external reference signal input from the outside. a first phase comparator that obtains from its output a signal that maintains a constant phase relationship with the output of the voltage controlled oscillator, and the output of the voltage controlled oscillator or its frequency-divided output and the phase shift circuit. a second phase comparator that compares the phase of the output signal of the first and second
The voltage controlled oscillator is controlled by a difference signal between the outputs of the phase comparators.
PLL fluctuation compensation device. 2 As the first and second phase comparators, a signal generator that generates a triangular wave or trapezoidal wave using the output of the voltage controlled oscillator or its frequency-divided output, and a first pulse and phase shift circuit that pulses the external reference signal. and a circuit that samples and holds the output of the signal generator using a second pulse obtained by pulsing the output of the signal generator, and a first phase comparison output and a second phase comparison output from the sample and hold circuit. 2. The PLL fluctuation compensating device according to claim 1, wherein 3. The PLL fluctuation compensation device according to claim 2, wherein the slope of the triangular wave or trapezoidal wave of the signal generator is controlled by the second phase comparison output. 4 As the first and second phase comparators, a signal generator that generates a triangular wave or a trapezoidal wave based on an external reference signal, a first pulse obtained by pulsing the output of the voltage controlled oscillator or its frequency-divided output, and the external reference. and a circuit that samples and holds the output of the signal generator using a second pulse obtained by pulsing a signal obtained by shifting the phase of the signal by a certain amount, and outputs a first phase comparison output and a second pulse from the sample and hold circuit. 2. The PLL fluctuation compensation device according to claim 1, wherein the PLL fluctuation compensation device obtains two phase comparison outputs. 5. Claims 2 and 3 further comprising a peak hold circuit that detects the maximum value or minimum value of the output of the signal generator, and the output of the peak hold circuit is used in place of the second phase comparison output. Or the PLL fluctuation compensation device described in 4.