JPH0581928B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a microcomputer reset device, and more particularly to a microcomputer reset device for performing a reset operation when a program is not being processed normally.

(Prior Art) Microcomputers are sometimes provided with means for detecting runaway of a program and performing a reset operation to return the program to normal operation (cancellation of runaway). FIG. 6 shows an example of the above runaway canceling means.

The figure shows an example of a microcomputer for use in a vehicle, and the main power source 1 is a battery. This main power supply 1
is branched into two parts, one of which is connected to the V _CC power supply circuit 2 via the ignition switch (main switch) SW1, and the other to the V _DD power supply circuit 3.

The V _CC power supply circuit 2 creates a constant voltage power supply for operating the peripheral circuit 4, and the V _DD power supply circuit 3 creates a constant voltage power supply for operating the peripheral circuit 4.
Specific circuits such as CPU or RAM (hereinafter simply referred to as
A constant voltage power supply is created to operate the CPU (5).

The watchdog timer 8 monitors the interval of the signal A output from the CPU 5 at a constant interval T1,
If the signal A from the CPU 5 is not detected for a period longer than T1, it is determined that a program runaway has occurred and a reset signal B is output to the OR gate 9.

This reset signal B is a signal that is output only one pulse when a program runaway is detected.
When a reset operation is performed in response to this signal B, the program rises from its initial state and returns to normal operation. In this case, if the cause of the program runaway has not been eliminated, the reset operation will be performed again.

In this manner, the watchdog timer 8 detects program runaway and performs a reset operation to release the program from runaway.

On the other hand, the above-mentioned reset operation is also performed when the main power supply 1 has a trouble related to the main power supply, such as consumption or disconnection. That is, when the above trouble occurs, the output voltage of the V _DD power supply circuit 3 decreases.
This voltage drop is detected by a V _DD voltage drop detection circuit (hereinafter referred to as a V _DD detection circuit) 7 and outputs a reset signal C to the OR gate 9 .

In this way, all operations of the CPU 5 are stopped by the logical sum signal D of the signals B and C, and when this signal D is released, the initial start of the program is made.

In addition, when the main switch SW1 is turned off and the power supply to the V _CC power supply circuit 2 is cut off, the V _CC
Voltage drop detection circuit (hereinafter referred to as V _CC detection circuit)
6, a drop in the output voltage of the V _CC power supply circuit 2 is detected, and a power down trigger E1 is output to the CPU 5.

The progress of the program is stopped by this power down trigger E1, and the program enters a state (hereinafter referred to as power down mode) in which only some functions, such as the function of storing data in memory, are retained. This power-down mode can dramatically reduce current consumption.

Switching to the power down mode is a particularly important function in terms of saving power consumption in cases where a battery is used as the main power source 1, such as in a vehicle-mounted microcomputer.

Note that since the operation of the watchdog timer 8 is stopped by the signal E2 output from the V _CC detection circuit 6 at the same time as the power down trigger E1,
After entering the power down mode transition operation, the reset signal B is not output.

Various signals are exchanged between the peripheral circuit 4 and the CPU 5.

(Problem to be Solved by the Invention) As explained above, in the conventional technology, since the watchdog timer was used to monitor whether the program was operating normally, the watchdog timer was not included. There were problems such as the need to secure mounting space for a large additional circuit and the complexity of the circuit.

Also, after the power down trigger is output,
Since the watchdog timer does not perform monitoring operation,
It is not possible to determine whether or not the system has actually entered power down mode. As a result, a problem arises in that backup current is supplied to the CPU not only to maintain the contents of RAM but also to operate the CPU.Especially when the power supply is battery-powered, the battery may become overcharged when not in use for a long time. There is a problem that discharge may occur.

SUMMARY OF THE INVENTION An object of the present invention is to provide a reset device for a microcomputer that solves the above-mentioned problems and that uses a simple circuit configuration to perform a reset operation when a program runs out of control, so that normal program processing can be performed from the initial state. It's about doing.

(Means and Effects for Solving the Problems) In order to solve the above problems and achieve the objects, the present invention provides a system for detecting that the main power is cut off and supplying a power down trigger to the CPU. After that
means for limiting the current supplied to the V _DD power supply circuit;
If more current is consumed than the planned value required to keep the CPU in power-down mode, a drop in the output voltage of the V _DD power supply circuit caused by the excess current consumption is detected and a reset signal is sent to the CPU. V _DD output voltage detection means for supplying VDD, and
A feature of the present invention is that when the output voltage of the V _DD power supply circuit falls below its guaranteed operation voltage, the output of the V _DD power supply circuit is stopped.

In the present invention having the above characteristics, the output voltage of the V _DD power supply circuit decreases when a current greater than the value required in the power down mode is supplied. By detecting this drop in output voltage, a power down trigger is provided to the CPU.
It is detected that the CPU is not in power down mode.

When the V _DD output voltage detection means detects that the CPU is not in power down mode, it is determined that the program is running out of control and a reset signal is output to the CPU.

Therefore, there is no need to monitor abnormalities in operation using a watchdog timer as in the prior art.

In addition, if the reset state continues for a long time and the output voltage of the V _DD power supply circuit becomes lower than its guaranteed operation voltage, the output of the V _DD power supply circuit will be stopped.
Over-discharge is prevented.

(Example) Examples of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. In this figure, the same reference numerals as in FIG. 6 indicate the same or equivalent parts.

In the figure, the current limit circuit 11 provided between the main power supply 1 and the V _DD power supply circuit 3
The current input to the V _DD power supply circuit 3 is limited. When the main switch SW1 is turned off, the V _IG voltage drop detection circuit (hereinafter referred to as the V _IG detection circuit) 10 detects that the input voltage V _IG of the V _CC power supply circuit 2 has fallen below the third reference value. A detection signal F is output. This detection signal F is supplied to the switch SW2 and the switch SW2 is opened. As a result, the circuit that was supplying current directly from the main power supply 1 to the V _DD power supply circuit 3 is changed from the main power supply 1 to the current limiting circuit 1.
1 to a circuit that supplies current to the _VDD power supply circuit 3. That is, a circuit is formed in which a current limiting circuit is inserted in series between the main power supply and the _VDD power supply circuit 3.

When the input voltage V _IG of the V _CC power supply circuit 2 is equal to or higher than the third reference value, the switch SW2 is closed, so the current from the main power supply 1 is routed to the V _DD power supply circuit 3 without passing through the current limiting circuit 11. Supplied directly.

In the current limit circuit 11, the current has the following value
I Limited to _LMT . In other words, the total current consumed by the CPU 5, the V _DD power supply circuit 3, and the V _DD detection circuit 7 is
I _LMT is limited so that the relationship I _ERR > I _LMT > I _BU holds, where I _ERR and I _BU are the case where the I LMT operates normally and enters the power down mode, respectively.

Since the current supplied to the V _DD power supply circuit 3 is limited to the value I _LMT where the above relationship holds, this limited current
When a current exceeding I _LMT is about to be consumed, the output voltage of the V _DD power supply circuit 3 decreases, and the V _DD detection circuit 7 detects this voltage drop and outputs a reset signal C.

Note that the V _CC detection circuit 6 and the V _IG detection circuit 10
The first and third reference values respectively set in the main switch SW1 are used to perform necessary processing when transitioning to power down mode when the main switch SW1 is turned off and the current supply is cut off, such as backing up the contents of the register. The settings are made so that time (hereinafter referred to as power-down processing time) can be secured for performing well-known processing (power-down processing) when the power is turned off, such as transferring data to a dedicated RAM. In other words, the first reference value set in the V _CC detection circuit 6 is
V CC is set to a value higher than the third reference value set in the V _IG detection circuit 10, and when the current supply is cut off, V _CC
Due to the decrease in the output voltage of power supply circuit 2, V _CC
A power down trigger E is outputted from the detection circuit 6, and thereafter, a detection signal F is outputted from the V _IG detection circuit 10 due to a decrease in the input voltage of the V _CC power supply circuit 2. Then, specific values of the first and third reference values are determined so that the time from when the power down trigger E is output to when the detection signal F is output corresponds to at least the power down processing time. be done.

In the above configuration, when the main switch SW1 is opened and the power down trigger E and the detection signal F are sequentially output, the CPU 5 executes power down processing in response to the power down trigger E.
CPU5 is in power down mode, that is, the CPU5 is in power down mode.
transitions to a state where it only retains the contents of RAM within. Further, SW2 is opened by the detection signal F,
Current is now supplied from the main power supply 1 to the V _DD detection circuit 7 via the current limiting circuit 11 .

The current consumption I _BU at this time is less than the limit current I _LMT , and the output voltage of the V _DD power supply circuit does not drop, so
The reset signal C is never output from the V _DD detection circuit 7.

By the way, if the program is not processed normally, the power down mode will not be entered even if the power down trigger E is output, so a large current I _ERR required for the entire operation of the CPU 5 will flow. However, since the current is limited to _ILMT , the output of the V _DD power supply circuit 3 decreases. This V _DD power supply circuit 3
When the output of the CPU 5 becomes equal to or less than the second reference value set in the V _DD detection circuit 7, a reset signal C is outputted from the V _DD detection circuit 7 and the CPU 5 is reset.

Next, referring to FIG. 2, the V _IG detection circuit 10,
A circuit example of the switch SW2 and the current limiting circuit 11 will be explained.

In the figure, the current limiting circuit 11 includes a resistor R1,
The V _IG detection circuit 10 consists of resistors R3 and R4 and a transistor Q4. The switch SW2 consists of a transistor Q3 and resistors R5 and R6. In addition, V _DD power supply circuit 3
consists of the V _DD regulator and transistor Q1.

When main switch SW1 is closed,
The voltage V _IG of main power supply 1 is applied to the base of transistor Q4.
Transistor Q4 is in an on state because a forward bias is applied from . When transistor Q4 is on, transistor Q3 is on,
Since resistor R1 is shorted, the current supplied to V _DD power supply circuit 3 is limited only by resistor R2.

When the main switch SW1 is opened and the voltage applied to the base of the transistor Q4 drops and the transistor Q4 is turned off, Q3 is also turned off, so the current supplied to the V _DD power supply circuit 3 flows through the resistor R1.
and the current determined by the value of R2, that is, the limiting current I _LMT . The voltage V _IG at which transistor Q4 turns off is determined by the combination of resistors R3 and R4.

Next, a second embodiment of the present invention will be described with reference to FIG. In this figure, the same reference numerals as in FIG. 1 indicate the same or equivalent parts. In this second embodiment, the output voltage drop of the V _CC power supply circuit 2 is reduced by the first V _CC
The configuration is such that a voltage drop detection circuit (first V _CC detection circuit) 6 and a second V _CC voltage drop detection circuit (second V _CC detection circuit) 12 are used for detection. With this configuration, as the V _CC voltage output from the V _CC power supply circuit 2 decreases, the power trigger E is output first, and then the detection signal F is output.

For this purpose, the first reference value for outputting the power trigger E from the first V _CC detection circuit 6 is set to V _CC 3, and the fourth reference value for outputting the detection signal F from the second V _CC detection circuit 12 is set to V CC 3. When the reference value is V _CC 4,
Select and set the values such that V _CC 4 < V _CC 3.

It also detects the output voltage of V _CC power supply circuit 2.
It is also possible to use only one V _CC detection circuit and provide a delay circuit to this V _CC detection circuit so that the two signals E and F are output at different timings. A delay time is set in the delay circuit to ensure the power down processing time so that current limitation is not applied before the power down processing is completed. By doing so, the second V _CC detection circuit 12 can be omitted.

In the embodiment described above, runaway of the program can be detected and the program can be reset, but in the reset state of the program, generally,
Since the amount of current consumption cannot be extremely limited, after performing a reset, turn on main switch SW1, run the program under normal conditions, and then turn off main switch SW1 again to end the operation in power down mode. You must do so.

With the in-vehicle microcomputer, the driver can sense the actual malfunction of the engine and operate the main switch SW1 as described above. It may also be possible to notify the user of a runaway program.

Next, a third embodiment of the present invention will be described with reference to FIG. In the figure, the same symbols as in Figure 1 are the same.
or indicate equivalent parts.

This third embodiment is an example in which measures have been taken in consideration of the above-mentioned situation in which the current consumption of the CPU 5 does not drop extremely because the internal clock of the CPU 5 is generally not stopped even when the CPU 5 is reset.
In a situation where a reset is required because the program is not operating normally, the supply of current to the CPU 5 is stopped.

In FIG. 4, a rectifier 13 is provided between the V _CC power supply circuit 2 and the V _DD power supply circuit 3 to allow current to flow only in the direction from the V _CC power supply circuit 2 to the V _DD power supply circuit 3. This rectifier 13 may be a switch that is turned on when V _CC >V _DD and turned off when V _CC <V _DD .

Further, the V _DD power supply circuit 3 is configured as a constant voltage circuit (see FIG. 5) that maintains its own output voltage at a predetermined value based on its output. The current value limited by the current limiting circuit 11 is set using the same criteria as the setting criteria for the current _ILMT .

With this configuration, the main switch
1 is opened, the current supplied to the V _DD power supply circuit 3 is limited to _ILMT by the current limit circuit 11 if the program is not operating normally.

In this state, if a current exceeding the limit of the current limit circuit 11 is consumed for the operation of the CPU 5, the V _DD voltage drop detection circuit 7, and the V _DD power supply circuit 3, the output of the V _DD power supply circuit 3 decreases. The V _DD detection circuit 7 detects this output drop and outputs a reset signal C to stop (reset) the operation of the CPU 5.

Further, as will be described in detail later with reference to FIG. 5, the V _DD power supply circuit 3 is configured to stop operating and set the output voltage V _DD to 0V when its output voltage drops below its own guaranteed operating voltage. be done.

When the main switch SW1 is turned on again, V _DD power supply circuit 3 is connected via the rectifier or switch 13.
A voltage V CC is applied from the V _CC power supply circuit 2 to the V _CC power supply circuit 2 . _VDD
When the voltage V _CC is applied, the power supply circuit 3 outputs the expected voltage again.

In this way, even if the program is not operating normally, when the main switch SW1 is opened, no power from the main power supply 1 is consumed. Therefore, for example, if a program in a car's microcomputer is not working properly and the engine is running poorly, the car may be left in a garage for a long time waiting for repairs. Even if this happens, it is possible to avoid the battery (main power supply 1) being discharged during that time.

FIG. 5 shows an example of the V _DD power supply circuit 3 suitable for the embodiment of FIG. 4.

In the figure, when a switch (not shown) corresponding to the switch SW1 is turned on, V _CC
The voltage V _CC is supplied from the power supply circuit 2 to the comparator 14 as an operating power source via the rectifier 13, and V _DD
The power supply circuit 3 becomes operational. When the voltage divided by resistors R7 and R8, which is one input of the comparator, is higher than the reference voltage which is the other input, the output of the comparator 14 turns on the transistor Q1. Once transistor Q
1 is turned on, the _VDD power supply circuit 3 continues to output even if no current is supplied from the _VCC power supply circuit 2.

When a switch (not shown) corresponding to the switch SW1 is turned off from this state, if the program is operating normally, the program operates in the same manner as the first embodiment explained in FIG. 1, and the V _DD power supply circuit 3 continues outputting.

However, if a program operation error occurs and the power down mode cannot be entered, the current I _ERR necessary for normal operation will flow. However, since the supplied current is limited to I _LMT , the output of the V _DD power supply circuit 3 decreases, and when it drops below the operation guaranteed voltage of the comparator 14, the transistor Q1 turns off, and the output voltage V _DD becomes "0". become. When transistor Q1 is off,
When a voltage higher than the guaranteed operation voltage is supplied to the comparator 14 again from the V _CC power supply circuit 2, the comparator 14 is released.

As described above, in the present invention, by providing the current limiting circuit 11, even if the main switch is turned off when the program operation is not normal, if the current is about to be consumed beyond the limit current, the V _DD power supply circuit 3 output decreases. As a result, the V _DD detection circuit 7 detects a voltage drop and outputs a reset signal C.

Furthermore, as shown in the third embodiment, in a state where the reset signal C is output, the supply of current is completely stopped, and if the main power source 1 is a battery, this battery is prevented from discharging. Made it possible to avoid it.

Further, the third embodiment, that is, the V _DD power supply circuit 3 having the configuration shown in FIGS. 4 and 5, can also be applied to the embodiments described with reference to FIG. 1 or 3.

In this embodiment, the reset signal is output by detecting a drop in the output voltage of the V _DD power supply circuit 3, but it is also possible to detect the current flowing through the current limiting circuit 11 and output the reset signal. Specifically, for example, the current flowing through the resistor R1 in FIG. 2 may be detected.

(Effects of the Invention) As is clear from the above explanation, according to the present invention, whether the program is operating normally or not is determined based on whether or not it has entered the power down mode. There is no longer a need for monitoring with the Tsuchidotsugu timer. As a result, the space required for installing a watchdog timer was saved, and the circuit configuration of the microcomputer became simpler.

In addition, if the power down mode is not entered, the supply of current from the main power supply can be completely stopped after resetting, so even if the main switch is turned off while the program is not operating normally, the current consumption will be reduced. This can be significantly reduced.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a first embodiment of the present invention, Fig. 2 is a main circuit diagram of the first embodiment, Fig. 3 is a block diagram showing a second embodiment of the invention, and Fig. 4 is a block diagram showing a second embodiment of the invention. FIG. 5 is a block diagram showing a main part of the third embodiment, and FIG. 6 is a block diagram showing a conventional technique. 1...Main power supply, 2...V _CC power supply circuit, 3...
V _DD power supply circuit, 5...CPU, 6, 7, 10, 12
... Voltage drop detection circuit, 11 ... Current limiting circuit,
13... Rectifier.

Claims (1)

[Claims] 1. A V _CC power supply circuit for operating peripheral circuits, a V _DD power supply circuit for operating the CPU, and a common main power supply circuit for supplying power to the V _CC power supply circuit and the V _DD power supply circuit. The battery as a power source and the V _CC
V _CC output voltage detection means for supplying a power down trigger to the CPU when the output voltage of the power supply circuit drops below a first reference value;
A microcomputer reset device configured to shift a CPU to a power down mode, comprising current limiting means for limiting the current supplied to the V _DD power supply circuit to a current value necessary to maintain the power down mode. , circuit switching means for forming a circuit for inserting the current limiting means in series between the main power supply and the V _DD power supply circuit when the power down trigger is supplied to the CPU _; V DD output voltage detection means detects that the output voltage of the circuit has fallen below a second reference value and outputs a reset signal to the CPU, and the _{V DD power} supply circuit has an output that is lower than the second reference value _. A reset device for a microcomputer, characterized in that the reset device for a microcomputer is configured to stop output when the voltage drops below the guaranteed operation voltage of a power supply circuit. 2. A V _CC power supply circuit for operating peripheral circuits, a V _DD power supply circuit for operating the CPU, and a battery serving as a common main power supply for supplying power to the V _CC power supply circuit and the V _DD power supply circuit; Said V _CC
V _CC output voltage detection means for supplying a power down trigger to the CPU when the output voltage of the power supply circuit drops below a first reference value;
A microcomputer reset device configured to shift a CPU to a power down mode, comprising current limiting means for limiting the current supplied to the V _DD power supply circuit to a current value necessary to maintain the power down mode. , circuit switching means for forming a circuit for inserting the current limiting means in series between the main power supply and the V _DD power supply circuit when the power down trigger is supplied to the CPU; and the current limiting means. current detecting means for detecting this and outputting a reset signal to the CPU when the current limiting means is activated to cause a current exceeding a predetermined value required in the power down mode to flow; A reset device for a microcomputer, characterized in that the V _DD power supply circuit is configured to stop outputting when its output drops below the guaranteed operation voltage of the V _DD power supply circuit. 3. V _CC input voltage detection means for detecting that the input voltage of the V _CC power supply circuit has fallen below a third reference value lower than the first reference value and outputting a switching signal for the switching means. A microcomputer reset device according to claim 1 or 2, characterized in that: 4. When the output voltage of the V _CC power supply circuit decreases to a fourth reference value lower than the first reference value,
3. The microcomputer reset device according to claim 1, further comprising second V _CC output voltage detection means for outputting a switching signal of said switching means. 5. The microcomputer reset according to claim 1 or 2, further comprising a delay means that is activated in response to the power down trigger and outputs a switching signal for the switching means after a power down processing time has elapsed. Device.