JPH0582092B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a two-wire transmission system, and more particularly to an automatic equalizer that equalizes the amplitude attenuation of an information signal depending on the state of a transmission path.

[Conventional technology]

FIG. 2 is a block diagram showing an example of a conventional automatic equalizer.

Information signal a as input signal of buffer circuit 1
and a pilot signal b are input, a high pass filter 2 and a low pass filter 3 are connected in parallel to the output of the buffer circuit 1, an information signal a is output from the output of the high pass filter 2, and a pilot signal b is output from the low pass filter 3. is output. The maximum amplitude voltage of the pilot signal b is held by the peak hold circuit 5, and the voltage held in the peak hold circuit 5 is controlled by the next-stage analog-to-digital conversion circuit 8 so that it follows the reference voltage of the reference voltage generation circuit 6. Clock CLK by percentage
The signal is digitized at the timing of , and outputted from the analog-to-digital conversion circuit 8. The gain control circuit 9 sets the gain of the amplifier circuit 41 to a gain corresponding to the pilot signal reception amplitude voltage using the gain selection circuit 42 of the variable amplifier section 4 according to the output of the analog-to-digital conversion circuit 8, and reduces the flat loss of the transmission line. Perform equalization.

[Problem that the invention seeks to solve]

In the circuit format described above, in order to operate the gain control circuit and the gain control circuit of the variable amplifier section in response to slight fluctuations in the voltage held in the peak hold circuit, the gain of the amplifier circuit 41 that amplifies the information signal also corresponds. It will be changed accordingly. This gain change is generally achieved using variable impedance elements such as thermistors and variable capacitance diodes, MOS transistors, etc.
This is done by changing the circuit constants included in the amplifier circuit 41 using an electronic switch element such as a CMOS transistor, or a relay element using a mechanical contact.

Therefore, according to the prior art, as the amplification degree of the amplifier circuit 41 changes correspondingly to a slight variation in the voltage held in the peak hold circuit, the circuit constant of the amplifier circuit 41 is frequently changed. At the time of this change, a transient phenomenon occurs in the circuit, and this transient phenomenon is superimposed on the information signal as noise, resulting in erroneous determination and reducing the operating margin.

[Means for solving problems]

The automatic equalizer of the present invention does not update the equalization amount to the gain control circuit of the variable amplifier section when the pilot signal amplitude voltage is within a preset amplitude voltage fluctuation range. It solves the above drawbacks and can also cope with temperature fluctuations that occur when the transmission line is used for a long time.

More specifically, the automatic equalizer of the present invention receives an information signal and a pilot signal via a two-wire transmission line, and controls the gain of the information signal using the pilot signal. A pilot signal is input to the input, and the output of the analog-to-digital conversion circuit is connected to the first and second registers of the next stage, and the first register is always set with the output data of the analog-to-digital conversion circuit, and the output data of the analog-to-digital conversion circuit is set to the first register. The data is set in the second register under the conditions described later, and the output of the first register is connected to one input of the subtraction circuit in the next stage, and
One output of the register is connected to the variable amplifier circuit through a gain control circuit, the other output is connected to the other input of the subtraction circuit, and the output of the first register and the second register are connected to each other. The absolute value of the subtraction result is input to one input terminal of the next stage comparator, the other input terminal is connected to the reference fluctuation amount setting circuit, and the result of comparing the two inputs of the comparator is inputted to the second stage comparator. It is characterized in that it is set as a condition for setting two registers.

[Embodiment] FIG. 1 is a block diagram showing an embodiment of the present invention.

The information signal a and the pilot signal b from the transmission path are input to the buffer circuit 1.
A high-pass filter 2 and a low-pass filter 3 are connected in parallel to the output of the high-pass filter 2, and the output of the high-pass filter 2 outputs an information signal a, and the low-pass filter 3 outputs a pilot signal b. This pilot signal b is connected to a peak hold circuit 5, and the peak hold circuit 5 holds the maximum amplitude voltage value of the pilot signal. Next, the voltage held in the peak hold circuit 5 is digitized by the analog-to-digital conversion circuit 8 at a rate according to the reference voltage of the reference voltage generation circuit 6, and is output from the analog-to-digital conversion circuit 8. The output of the analog-to-digital conversion circuit 8 is connected to register A10 and register B11, and register A10 is connected to the clock.
CLK always sets the transmission path loss equalization amount,
In the register B11, the loss equalization amount of the transmission path is set under the control of the control circuit at the subsequent stage. The operation of the control circuit at the latter stage is performed by register A10 and register B1.
The output data of 1 is subtracted by the subtraction circuit 12, and the absolute value of the result is the loss equalization fluctuation amount of the transmission line. When the comparison is made and the transmission line loss equalization change amount is larger than the reference fluctuation amount, the gate of the gate circuit 7 is opened, the transmission line loss equalization amount is newly set in the register B11, and the gain control circuit 9 The gain selection circuit 42 of the variable amplifier section 4 updates the loss equalization amount of the transmission path of the variable amplifier section 4 through , and then, when the comparison result is small, the gate of the gate circuit 7 is closed and no new update is performed.

〔Effect of the invention〕

As explained above, the present invention prevents the equalization amount from being updated to the gain selection circuit of the variable amplifier section when the pilot signal amplitude voltage is within the preset amplitude voltage fluctuation range. By updating the equalization amount to the gain selection circuit of the variable amplifier section only when the gain is outside the fluctuation range, transient phenomenon noise when changing the amplification degree of the amplifier circuit can be reduced from the information signal. In addition, it is possible to cope with changes in the equalization amount of the transmission line due to temperature changes that occur when the transmission line is used for a long time.

In addition, when a fluctuation in loss equalization that exceeds the standard fluctuation amount occurs, the value is updated to a value suitable for the new loss equalization amount after the fluctuation, so if there is a slight fluctuation within the allowable range, the equalization is is not updated, and the number of equalization updates is extremely reduced even in response to rapid fluctuations. As a result, the frequency of equalization updates can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a block diagram of a conventional transmission line equalization method. DESCRIPTION OF SYMBOLS 1...Buffer circuit, 2...High pass filter, 3...Low pass filter, 4...Variable amplification section, 41...Amplification circuit, 42...Gain selection circuit,
5...Peak hold circuit, 6...Reference voltage generation circuit, 7...Gate circuit, 8...Analog-digital conversion circuit, 9...Gain control circuit, 10...Register A, 11...Register B, 12... ...Subtraction circuit, 13...Comparator, 14...Reference fluctuation amount setting circuit.

Claims (1)

[Claims] 1. In an automatic equalizer that receives an information signal and a pilot signal via a two-wire transmission line and controls the gain of the information signal using the pilot signal, the pilot signal is input to the input of an analog-to-digital conversion circuit, and the analog-to-digital conversion is performed. Connect the output of the circuit to the first and second registers of the next stage,
The first register is always set with the output data of the analog-to-digital conversion circuit, the second register is set with the data under the conditions described later, and the output of the first register is connected to one input of the subtraction circuit in the next stage. One output of the second register is connected to the variable amplifier circuit via a gain control circuit, and the other output is connected to the other input of the subtraction circuit, so that the output of the first register and the second register are connected to each other. The absolute value of the subtraction result is subtracted from the output, and the absolute value of the subtraction result is
automatic equalization, characterized in that the second input terminal is input to one input terminal, the other input terminal is connected to a reference fluctuation amount setting circuit, and the result of comparing the two inputs of the comparator is used as the setting condition of the second register. vessel.