JPH0583032B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to CT (computer tomography),
Regarding the sampling pulse generation circuit when recording video signals introduced from multiple diagnostic devices such as US (Ultra Sonography) into a digital image recording device, more specifically, the different types of imaging devices that constitute various diagnostic devices, etc. When recording multiple video signals with different numbers of scanning lines output from a television camera (for example, a television camera) by performing A/D conversion processing on the image memory in one digital image recording device, a frequency-voltage converter ( A sampling pulse synchronized with a horizontal synchronizing signal of the video signal having a different number of scanning lines is generated using an N multiplication circuit including an equalization pulse removal circuit controlled by an F/V converter (hereinafter referred to as an F/V converter), and the sampling pulse is is controlled by an F/V converter built into the image recording device, which enables real-time recording of a plurality of video signals having different numbers of scanning lines in the image memory in the digital image recording device. Regarding the N multiplier circuit. The images recorded by the present invention are used as signal sources and analog sources for various main image recording devices (multi-format cameras, laser printers, thermal printers, ink jets, etc.) and a simple comprehensive image diagnostic system PACS (Picture Archiving).
It is suitably used as an input source for a file (and communication system), a primary image storage system for an X-ray TV or cine system, an image buffer or scan converter using an image memory, etc.

By the way, for example, if image information of the affected part of the human body and its surroundings is obtained continuously using CT, US, etc., it is possible to understand the affected part itself and its surroundings, which is extremely useful for doctors, etc. It's convenient.
In this case, if a plurality of pieces of image information are exposed and recorded in real time, particularly on photographic film or the like, and obtained as a hard copy, the information can be used for medical diagnosis without being restricted by time or place.

However, the video signals output from these medical image diagnostic apparatuses do not necessarily have the same specifications; for example, the number of scanning lines, field frequency, etc. often differ depending on the respective diagnostic apparatus.

Conventionally, in order to store video signals related to different scanning lines in the image memory of a digital image recording device, an A/D converter that generates sampling pulses that are compatible with, or synchronized with, each scanning line is required. It is necessary to record using multiple image recording devices including:

However, with the recent technological development of medical diagnostic equipment, the types of medical diagnostic equipment have changed to the above-mentioned CT,
In addition to US, DF (Digital Fluorography),
There are a wide variety of diagnostic equipment such as MRI (magnetic resonance imaging) and RI (radioisotope) equipment, and therefore, adopting and introducing digital image recording equipment compatible with each diagnostic equipment will significantly increase the economic burden and further This has led to various inconveniences, such as the need to secure a large storage space.

The present invention has been made in order to overcome the above-mentioned disadvantages, and the present invention is to record a plurality of video signals with different numbers of scanning lines output from different types of television cameras constituting various diagnostic devices into a single digital image recording device. When performing A/D conversion processing and recording into the image memory in the device, an N multiplication circuit including an equalization pulse removal circuit controlled by an F/V converter is used to horizontally convert the video signals with different numbers of scanning lines. Generating a sampling pulse of an A/D converter synchronized with a synchronization signal, and storing the plurality of video signals having different numbers of scanning lines in an image memory in the image recording device in real time by using the sampling pulse. It is an object of the present invention to provide an N multiplier circuit controlled by an F/V converter that is incorporated in an image recording device capable of the following.

In order to achieve the above object, the F/V of the present invention
The N multiplier circuit controlled by the converter includes an F/V converter that is supplied with a video synchronization signal as an input signal and converts the video synchronization signal into a voltage based on the frequency of the video synchronization signal; A synchronization signal is supplied, and the period is (1/2) triggered by the video synchronization signal and under the control of the output voltage of the F/V converter.
an equalization pulse removal circuit that alternately removes equalization pulses using output pulses controlled during a period exceeding H and less than 1H to produce a horizontal synchronization signal, and uses the horizontal synchronization signal as a reference input signal of a frequency synthesizer; It is characterized by being

FIG. 1 is a schematic block diagram of a video image recording apparatus incorporating an N multiplier circuit controlled by an F/V converter according to the present invention. As shown in FIG. 1, the video image recording apparatus includes an input section 10 that converts input video signals of various different scanning lines from analog to digital.
, a frame memory 12 for storing the A/D converted video signal, an output unit 14 for converting the video signal stored in the frame memory into a D/A and outputting it as required, and a frame memory 12 for storing the A/D converted video signal; N multiplier circuit 16 controlled by an F/V converter that generates a sampling pulse synchronized with the horizontal synchronization pulse
and an output timing signal generation means 18 which supplies a signal to the output section 14 to output the video signal stored in the frame memory 12, and according to signals from the N multiplier circuit 16 and the output timing signal generation means 18. From input section 10 to frame memory 1
2 and a frame memory control section 20 that controls the storage operation of video signals into the frame memory 12 and the output operation from the frame memory 12 to the output section 14.

Therefore, in FIG. 1, when a video signal is input to the input section 10, the A/D converted video signal is supplied to the frame memory 12. Further, the video signal is supplied to an N multiplier circuit 16 and synchronized with the sampling pulse. This sampling pulse is transmitted to the input section 10 and the frame memory control section 2.
0 and is supplied to the output timing signal generation means 18 and used as a sampling pulse of the A/D converter in the input section 10, and also controls the storage operation of each line of the video signal to the frame memory control section 20. It is also used as an overall clock pulse to generate an output timing signal.

Here, it is controlled by the F/V converter.
For example, a PLL (phase locked loop) can be used as the N multiplier circuit.
PLL is a voltage controlled oscillator (VCO) whose output is supplied through a phase comparator and a low-pass filter.
The VCO functions to generate the sampling pulse according to the voltage. This sampling pulse is frequency-divided by N by a frequency dividing circuit, fed back to a phase comparator, and the phase of this sampling pulse is compared with the horizontal synchronizing pulse period to achieve accurate synchronization, and then supplied to the frame memory control section 20. Ru. As a result, the video signals are sequentially stored in the frame memory 12.

The output of the video signal stored in the frame memory 12 is controlled by the output timing signal generating means 18 which is supplied to the frame memory control section 20. The signal from the output timing signal generating means 18 is also supplied to the output section 14, and after the output section 14 has once imported the data stored in the external storage device into the main body of the image recording apparatus, It is D/A converted and output as a video signal.

As mentioned above, in the N multiplier circuit 16 controlled by the F/V converter, the sampling pulse generated by the VCO is divided by N by the programmable N frequency divider, and the phase of the horizontal synchronizing signal is adjusted. Synchronized by a comparator. In other words, the period of the sampling pulse output from the VCO can be freely changed by setting the division ratio N, and by using this sampling pulse to sample the video signal, the image period for each line can be stored in the frame memory. It can be stored in a format suitable for the number of scanning lines on the output side.

The sampling pulse period may be automatically set and controlled using a microcomputer or the like while making correspondence with the display device on the output side.
Alternatively, the cycle may be changed manually while checking the displayed video.

Here, when determining the sampling pulse period of one line of the sampled video signal to a desired period, the number of pulses for one line of sampling pulses is N, the number of pulses in the desired image is A, and the number of pulses in the non-image area. Assuming that B is the number of pulses N for one line, the number N of pulses for one line can be expressed as follows.

N=A+B...(1) With this setting procedure, it is possible to synchronize with video input signals with various numbers of scanning lines and store them in the frame memory, and output the stored images as video signals with the desired number of scanning lines. The effect that can be achieved is achieved.

In addition, as another method for determining the period, the number of pulses for one line N is determined by the horizontal synchronization pulse oscillation period T _h ,
If the oscillation period of the sampling pulse in a desired image displayed on one line is _Ts , it can also be determined by the following equation.

N=[T _h /T _s ]...(2) Here, the symbol ([ ]) is a Gauss symbol for making N an integer.

By performing the sampling process according to this setting method, aliasing (beat) of the sampled image and edges of fine characters caused by the frequency difference between the output sampling period of the digital image and the sampling period of the A/D converter can be avoided. It becomes possible to eliminate image distortion and reproduce a good image without reducing the resolution of the image.

Next, FIG. 2 shows a detailed circuit block diagram of a video image recording device 22 incorporating the N-multiplying circuit 16 controlled by the F/V converter according to the present invention, and its operation will be described below.

In FIG. 2, the input video signal _S
The output signal VIDEO (V _s ) of the horizontal and vertical synchronizing pulse removal circuit 24 is supplied to the A/D converter 27 after the horizontal and vertical synchronizing pulses are removed. Output signal ADD of A/D converter 27
0 to ADD7 are supplied to the serial/parallel converter 28, and its output signal (F374-0-On to F374
-F-On) is supplied to a register 30, where it is stored in the frame memory 12 in time for the cycle time of the frame memory 12. In the figure, this output signal is represented by LS-374-On.

The specifications of the frame memory 12 applied in this embodiment are 1024 x 1024 x 8 bits, and it is possible to capture up to 1024 scanning lines of the input video signal S _i . Images can be captured even if the number of scanning lines is greater than 1024, but some images may be missing.

On the other hand, the video signal S _i inputted to the sync separator 26 is separated into a horizontal synchronizing signal HD and a vertical synchronizing signal VD, and each is supplied to the selector 32 . The selector 32 is connected to a switch 34A,
34B, the HD signal or VD signal from an external synchronizing signal source other than the HD signal or VD signal included in the signal S _i can also be supplied. In this case, the selector 32 is configured to also receive an HD signal and a VD signal from a video generator (not shown). This video generator is used particularly during playback, and is capable of outputting video signals of arbitrary scanning lines. Further, the output of a write timing circuit 36 is also supplied to the selector 32, and when the write switch 38 is turned on, a write timing signal is outputted to the selector 32 in synchronization with the VD signal.

Next, the HD signal from the selector 32 is
It is supplied to the equalizing pulse removal circuit 40 and F/V converter 42 in the N multiplier circuit 16 controlled by the V converter, and then output to the VCO 48 via the phase comparator 44 and low pass filter (LPF) 46. be done. Note that the output signal of the F/V converter 42 is introduced into the control terminal T of the equalization pulse removal circuit 40.

Next, the output signal of the VCO 48, that is, the sampling pulse SP, is sent to the address counter 50,
The signal is supplied to the A/D converter 27 and the D/A converter 52. The output signal of the address counter 50 is supplied to a decoder 54, and 16 bits are output from the 4-bit signal.
After being changed into bit signals (SRSELO to SRSELF), the signals are supplied to the serial/parallel converter 28. Further, after the decoder 54 outputs the output signal SRSELF, the signal DECP is supplied to the register 30 after a certain amount of time has elapsed. This register 30 determines the timing of storing data into the frame memory 12, and also controls the timing of storing 128-bit data.
LS374On is configured to be stored 64 times for each line.

On the other hand, the output signal from the VCO 48 is also supplied to a frame memory timing circuit 56, which outputs a signal to the frame memory 12 and a selector signal SEL to the selector 58.

Further, the output pulse of the VCO 48 is fed back to the phase comparator 44 via the N frequency divider 60. That is, this phase comparator 44, LPF4
6, the VCO 48 and the N frequency divider 60 constitute a so-called PLL frequency synthesizer.

The N frequency divider 60 has a function of dividing the pulse oscillated by the VCO 48 by N to have the same period as the HD signal, and the setting of this frequency division ratio N is performed by the microcomputer 62. Therefore, for example, if it is desired to set the number of sampling pulses to 1024, the number can be set to 1024 plus the number B of pulses in unnecessary areas of the video signal to be the N value (N=1024+B).

On the other hand, the VD signal output from the selector 32 is supplied to the address counter 50 and the address counter 64 via a back porch and front porch setting circuit (not shown) to determine the boundary between each image. The output signal D of the address counter 50 and the output signal E of the address counter 64 are respectively supplied to the selector 58.
2 is selectively output.

Next, the video output analog signal _SAO is outputted from the frame memory 12 via the shift register 65 and the D/A converter 52. Note that the video output digital signal S _DO is output from the frame memory 12 via the data register 66 and the digital interface 68.

Output devices to which these S _AO and S _DO output signals are supplied include medical laser printers (LP) and simple
Examples include displays such as PACS, multiformat cameras, X-ray TV systems, and intra-hospital transmission.

Next, the overall operation of this video image recording apparatus will be explained with reference to the time charts of FIGS. 3 and 4.

When the video signal S _i is input to the video image recording device 22 , the horizontal and vertical synchronizing pulse removal circuit 24 supplies only the image signal as VIDEO (V _s ) to the A/D converter 27 . The image signal VIDEO
(V _s ) is the sampling pulse SP in the A/D converter.
A/D conversion is performed in real time, and ADD0~
The digital signal of ADD7 is output to the serial/parallel converter 28. Here, the output timing of the sampling pulse SP is controlled by an N multiplier circuit 16 controlled by the F/V converter.
On the other hand, the video signal S _i is connected to the sync separator 26.
The signal is separated into an HD signal and a VD signal and input to the selector 32. Here, write timing circuit 36
Accordingly, the output timing of the VD signal from the selector 32 can be adjusted on the condition that the write switch 38 is in a conductive state.

The HD signal output from the selector 32 is F/
After the equalization pulse is removed by an equalization pulse removal circuit 40 controlled by a V converter 42, it is supplied to a phase comparator 44. The output of the phase comparator 44 is
It is supplied to the VCO 48 and multiplied by N to create a sampling pulse SP. The sampling pulse SP is set in the N frequency divider 60 by the microcomputer 62 so that the number of sampling pulses required in the image becomes a desired number (for example, 1024), and is fed back to the phase comparator 44. The period of this feedback sampling pulse SP is synchronized with the HD signal period.

Here, a video signal according to an example of calculation of the number of pulses for one line in an actual video signal is shown in FIG.

According to this, the video signal part (Horizontal
Display Time) is 49.6 μs, and this portion is A/D converted with a pulse number of 1024. Therefore, the pulse interval is 48.4 ns (49.6 μs/1024), and from this, the number of sampling clock pulses for one line can be determined by the following formula. That is, 63.5 μs/48.4 ns=1312 By substituting this into the first equation, it can be expressed as shown in the following equation.

1312(N)=1024(A)+288(B) On the other hand, data from the A/D converter 27
ADD0 to ADD7 are serial/parallel converters 2
8, and then, based on each signal SRSEL0 to SRSELF from the decoder 54 via the register 30, the data is input to the frame memory 12 in order for each frame.
is memorized. In this case, the signal is stored in the frame memory 12 at the timing of the signal DFCP, which is slightly delayed from SRSELF. To specify the address of the frame memory 12, one of the output signals D and E of the address counters 50 and 64 is selected by the signal SEL from the frame memory timing circuit 56, and the horizontal and vertical addresses are switched by the selector 58. It is carried out by. Through the above-described procedure, video signals can be captured in real time.

Next, the video stored in the frame memory 12 is
The case of displaying on CRT etc. will be explained. First of all,
The image signal stored in the frame memory 12 is supplied to the shift register 65 according to a command from the microcomputer 62, and then D/A converted by the D/A converter 52, and then the video output analog signal _SAO is generated. The scanning line of the video output analog signal _SAO corresponds to the scanning line determined by a display device such as a CRT prepared in response to the HD or VD input signal of the video generator corresponding to the video signal. As a result, it is possible to clearly display an image having a different number of scanning lines without being affected by the number of scanning lines of the input video signal S _i . Further, when outputting the signal stored in the frame memory 12 as a digital value, the video output digital signal S _DO may be outputted via the data register 66 and the digital interface 68.

Note that in this embodiment, the N value in the N frequency divider is N=
Although it was determined using the formula A+B, it goes without saying that when determining the sampling pulse period for each line of the sampled video signal to a desired period, it may be determined as determined using the second formula.

An example of calculating the number of clocks of the video signal shown in FIG. 5 using this second equation will be shown below.

[63.5 μs/48.4 ns]=1312 This value is substantially the same as the value determined by the first equation. This setting can prevent occurrence of aliasing (beat) between the output period of the signal image and the sampling period of the A/D converter 27. For example, problems such as periodic pattern bits or the letter "A" being displayed distorted will not occur.

FIG. 6 shows a second embodiment of the image recording device according to the present invention. The overall system of the image recording device applied to this second embodiment is the same as that shown in the first embodiment, so the same reference numerals are given to the same components. A detailed explanation thereof will be omitted.

Therefore, as shown in FIG. 6, the second system is configured so that the signal line from the register 30 is supplied to each of the three frame memories 70, 72, and 74. On the other hand, frame memory 7
Microcomputer 6 for 0,72,74
A control signal is supplied from 2, and this control signal controls the storage location of the video signal from 3 to 3.
The frame memories 70, 72, and 74 can be freely selected.

The output signals of each frame memory 70, 72, 74 are supplied to a shift register 65. In this case, the signal from the shift register 65 is output via the D/A converter 52 as an analog signal _SAO , or via the data register 66 and digital interface 98 as a digital signal _SDO .

With such a configuration, the input video signal S _i is stored in one of the frame memories 70, 72, and 74 according to a control signal from the microcomputer 62.

On the other hand, the microcomputer 62 determines the storage state of the video signals in the frame memories 70, 72, and 74, making it possible to simultaneously input and output the video signals.

Therefore, in this case, even if the input signals have different scanning lines, they can be stored separately in the same image recording device, and each scanning line can be changed to the desired scanning line. The present device can be applied as a so-called image buffer, for example, by making it possible to output output signals suitable for the various output devices mentioned above (for example, laser printers, etc.).

The above is an explanatory diagram of the operation of the entire video image recording apparatus.Next, the N multiplier circuit controlled by the F/V converter according to the present invention will be explained in more detail with reference to the accompanying drawings.

In FIG. 7, reference numeral 16 indicates an N multiplier circuit controlled by an F/V converter for generating sampling pulses for the A/D converter according to the present invention. It is controlled by the F/V converter. The N multiplier circuit 16 is basically an F/V converter 42.
, an equalization pulse removal circuit 40, and a frequency synthesizer 100 whose frequency division ratio can be set programmably. Here, the equalization pulse removal circuit 40 is composed of a monostable multivibrator whose specific number is set to 3/4H (H is the period of the horizontal synchronizing signal). Set the time constant to 3/4H
The reason for this setting is that it is assumed that even if the insertion position of the equalization pulse is shifted, it will not exceed the intermediate value between 1H and 1/2H.

The HD signal including the equalization pulse input to the N multiplier circuit 16 controlled by the F/V converter is introduced to the equalization pulse removal circuit 40, and is also input to the pulse shaping circuit 102 of the F/V converter 42. and is introduced into the time constant control terminal T of the equalization pulse removal circuit 40 via a low pass filter (LPF) 104. The output signal of the equalization pulse removal circuit 40 is introduced into the reference input terminal φ ₁ of the phase comparator 44 constituting the frequency synthesizer 100. The output signal of the phase comparator 44 is passed through a low pass filter (LPF) 46 and a voltage controlled oscillator (VCO) 48.
The frequency division ratio is introduced into the second signal input terminal φ ₂ of the phase comparator 44 through an N frequency divider 60 controlled by a microcomputer 62 .

On the other hand, the output terminal of the VCO 48, that is,
A sampling pulse PS, which is used as a sampling pulse for the A/D converter 27, etc., is generated at the node with the N frequency divider 60.

The N multiplier circuit 16 controlled by the F/V converter according to this embodiment is basically constructed as described above, and its operation and effects will be explained in detail next.

Therefore, the input synchronization signal HD has a waveform shown in FIG. 8a. That is, the waveform includes a horizontal synchronization signal, a vertical synchronization signal, and an equalization pulse.

The monostable multivibrator constituting the equalization pulse removal circuit 40 receives the composite synchronization signal shown in FIG. 8a.
Triggered by falling edge of HD, 1/
Since the equalization pulse and cutting pulse inserted at the 2H position are removed, the output waveform of the equalization pulse removal circuit 40 has an interval as shown in FIG. 8b.
It will be 1H. This is because, as described above, the time constant of the monostable multivibrator constituting the equalization pulse removal circuit 40 is set to 3/4H.

On the other hand, since the output signal of the F/V converter 42 consisting of the pulse shaping circuit 102 and the LPF 104 is introduced into the time constant control terminal of the equalization pulse removal circuit 40, the output signal is included in the input composite synchronization signal HD. It operates to remove the equalization pulse even if the period of the horizontal synchronization frequency (f _h ) is different, that is, even if the output signal from the diagnostic device has different types of scanning lines. In this case, the output signal of the pulse shaping circuit 102 is shown in FIG.
The output signal of the LPF 46 is shown in FIG. 8d.

By the way, in the output waveform of the time constant control signal shown in Fig. 8d, the voltage increases near the presence of the equalization pulse in the composite synchronization signal HD, but the increase in voltage due to the presence of this equalization pulse is not the main amount. This has almost no effect on the equalization pulse removal effect according to the invention.
The reason for this is, for example, if the number of scanning lines in one field period is 500, that is, the time is 500H, and the number of equalization pulses is 18, that is, the time is 9H, then 9H/500H x 100 = 1.8% The time constant of the equalization pulse removal circuit 40 is 3/4H±1/4H.
This is because it is at a level that hardly poses a problem, considering that it is sufficient if it is within the range.

Further, since the time constant of the equalization pulse removal circuit 40 is controlled by feedforward control by the F/V converter 42, high-speed and stable operation can be expected.

Next, the horizontal synchronizing signal output of the equalization pulse removal circuit 40 is introduced into the reference input terminal φ ₁ of the phase comparator 44 in the frequency synthesizer 100, and the LPF 46,
VCO48 and microcomputer 62 in advance
A signal whose frequency is N times the frequency of the input horizontal synchronizing signal is derived by the N frequency division ratio 60, which is set to a frequency division ratio N corresponding to the diagnostic device used. The N-multiplied signal is sent to the frequency synthesizer 100.
This allows accurate synchronization with the input signal. The N-multiplied signal SP is used as a sampling pulse SP of the A/D converter 27 constituting the image recording device.

The above is a detailed explanation of the N multiplier circuit controlled by the F/V converter according to the present invention.

Next, FIG. 9A shows, as a first application example of the apparatus according to the first embodiment, a case where the scanning lines of the input video signal S _i are input to the apparatus as a plurality of different signals F, G, H. explain.

In this example, the signals with different numbers of scanning lines are controlled by the F/V converter via the selector 110.
The signal is A/D converted by the input section 10 using the timing signal generated by the multiplier circuit 16 and stored in the frame memory 12 . Similarly, the output section 14 is controlled by an output timing generating means 18. If this output section 14 is configured with a D/A converter, it is possible to reproduce a stationary surface on a CRT monitor (not shown) in real time by the above-described procedure. In addition, as shown in the figure, the external storage device 11 such as a floppy disk is connected via the personal computer 112.
4 temporarily stores video information, uses the output signal of a video generator (not shown) as an input video signal to create the output timing, and transfers the contents of the floppy disk to the frame memory 12 for output. For example, diagnostic images can be viewed even in places where diagnostic equipment is not available, and can be used for various image evaluations. Note that the video generator can output the same signal as the input signal.

Next, FIG. 9B shows a system for converting scanning lines as a second application example of the first embodiment.

In this embodiment, an image processing section 116 is interposed between the frame memory 12 and the output section 14, and a signal from the frame memory control section 20 is supplied thereto. The image processing unit 116 outputs image information obtained by interpolation or thinning using a known method in the vertical direction of the image at the output timing from the output timing signal generating means 18, thereby making it possible to output the image in a single format. Become. Therefore, by normalizing the output of a medical laser printer to the same format in the vertical direction of the screen, there is no need to control the speed of the scanner's sub-scanning.
At this time, you can easily set the aspect ratio of the image.

In addition, simple PACS can be used for display purposes.
If a CRT or the like is used, a single scan line CRT monitor can be used.

Furthermore, when outputting to a CRT multi-format camera, it can be displayed on a single CRT monitor, allowing photos from various diagnostic modalities to be laid out on the same film.

FIG. 10 shows a block diagram when the apparatus according to the first embodiment is used as an image acquisition system.

That is, the image stored in the frame memory 12 is configured to be imported into the external storage device 114 via the output unit 14. Further, as the external storage device 114, a magnetic disk or a floppy disk in a microcomputer can be used. The signals stored in the external storage device 114 can be output to a system as described below as necessary.

Conventional medical laser printers have image memory, image processing, laser light source, optical modulation, optical scanning, and storage medium transport functions, and digital signal interfaces are used as signal input means for each diagnostic modality. . In this case, since the final output is output to the laser printer after performing image processing suitable for each purpose, the cost of both the hardware and software of each diagnostic modality device and the laser printer side becomes high. In such a case, if the image recording device of the present application is used, it becomes possible to incorporate an inexpensive system that can be applied to all diagnostic modalities without making any changes to the conventional system.

Next, we will discuss simple PACS. The rapid introduction and diversification of new digital image diagnostic equipment, and on the other hand, remarkable progress has been made in the development of higher performance and lower prices of image processing systems, and development of high-speed image reading devices. Under these circumstances, there is a PACS for integrating image information. By using the image recording device of the present invention, compatibility can be obtained with medical images that currently have different image formats depending on the device manufacturer, and a PACS can be configured using existing devices. That is, if this device is applied as such a medical system image collection system, an effect can be obtained in which images can be output when necessary.

Next, an application example of the image recording apparatus equipped with a plurality of frame memories shown in the second embodiment will be described.

As shown in FIG. 11, input signals F, G, and H of different scanning lines are supplied to a selector 120 provided with three input terminals and three output terminals, respectively.
The image signal can be stored in any of the three frame memories via the input section 10.

At the same time, the output unit 14 can output an image signal stored from a frame memory other than the frame memory in which the storage operation is being performed by the selector 122.

By configuring such a system, it can be applied as a so-called image buffer. An application example of this image buffer will be described below.

For example, if there are multiple diagnostic devices (CT, US, DF, etc.) and you are trying to image them with a single multi-format camera, if you output diagnostic data from multiple diagnostic devices at the same time, the image may become impossible. Become. Therefore, by applying this system, data can be stored temporarily and multiple signals can be processed. It is also possible to edit buffered data on a single film. Specifically, it is possible to buffer diagnostic images for the circulatory system and make hard copies of only the images necessary for surgery, or to display them multiple times on a CRT. It can also be applied to a system that inputs and stores images in real time, such as during fluoroscopy of the esophagus, to obtain a hard copy of only the necessary area (affected area). Furthermore, this system can be applied to a system that buffers image data by arranging this system at the input section for communication as a transmission terminal inside and outside the hospital.

As described above, according to the present invention, a plurality of video signals having different numbers of scanning lines outputted from different types of imaging devices constituting various diagnostic equipment etc. are A/ The device that generates sampling pulses for D conversion processing has a frequency synthesizer configuration that includes an equalization pulse removal circuit controlled by an F/V converter, so horizontal synchronization is achieved by removing equalization pulses from the input video synchronization signal. A signal obtained by accurately multiplying the signal by N is obtained as a sampling pulse. Moreover, since the time constant of the equalization pulse removal circuit is controlled by feedforward control, extremely high-speed operation is possible and real-time image processing is possible.
As a result, prompt medical diagnosis can be expected.

Although the present invention has been described above with reference to preferred embodiments, the present invention is not limited to these embodiments, and various improvements and changes in design are possible without departing from the gist of the present invention. Of course.

[Brief explanation of drawings]

FIG. 1 is an overall block diagram of an image recording device incorporating an N multiplication circuit controlled by an F/V converter according to the present invention, and FIG. 2 is an N multiplication circuit controlled by an F/V converter according to the present invention. A detailed block diagram of the first embodiment of the entire image recording device in which the circuit is incorporated, FIG. 3 is a display time chart, FIG. 4 is a time chart of the image input section, and FIG. 5 is an example of a video signal. FIG. 6 is a detailed block diagram of a second embodiment of the entire image recording device incorporating an N multiplier circuit controlled by an F/V converter according to the present invention, and FIG. 7 is a detailed block diagram according to the present invention. A detailed block diagram of an N multiplier circuit controlled by an F/V converter, FIG. 8 is a waveform explanatory diagram of a detailed block diagram of an N multiplier circuit controlled by an F/V converter according to the present invention, and FIG. FIG. 10 is an application example diagram of the first embodiment of the image recording device incorporating an N multiplication circuit controlled by the F/V converter according to the present invention, and FIG. 11 is an example of the F/V converter according to the present invention. FIG. 4 is an application example diagram of a second embodiment of an image recording device incorporating an N multiplication circuit controlled by the above. 16... N multiplier circuit controlled by F/V converter, 40... Equalization pulse removal circuit, 42... F/V converter, 44... Phase comparator, 46... Low pass filter (LPF), 48... Voltage controlled oscillator (VCO), 60
...N frequency divider, 62...Microcomputer, 10
0...Frequency synthesizer, 104...Low pass filter (LPF).

Claims (1)

[Claims] 1. An F/V converter that is supplied with a video synchronization signal as an input signal and converts the video synchronization signal into a voltage based on the frequency of the video synchronization signal; and the video synchronization signal is supplied as the input signal. The period is (1/2) triggered by the video synchronization signal and controlled by the output voltage of the F/V converter.
an equalization pulse removal circuit that alternately removes equalization pulses using output pulses controlled during a period exceeding H and less than 1H to produce a horizontal synchronization signal, and uses the horizontal synchronization signal as a reference input signal of a frequency synthesizer; An N multiplier circuit controlled by an F/V converter characterized by: 2. In the circuit described in claim 1,
An F/V converter that receives a video synchronization signal as an input signal is composed of a pulse shaping circuit that shapes the waveform of the video synchronization signal, and a low-pass filter that receives the output of the pulse shaping circuit as an input, and converts the output of the low-pass filter into an equalization pulse. An N multiplier circuit controlled by an F/V converter, characterized in that the voltage is used to control the output pulse of the removal circuit.