JPH0584471B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a digital signal generator used, for example, in testing semiconductor integrated circuits.

(Prior Art) For example, as a digital signal generator used for testing digital semiconductor integrated circuits, high level and low level can be freely set.
It is necessary to be able to perform tri-state operation that provides high-level output, low-level output, and high-impedance output, be able to obtain high-speed output, and be able to protect the output.

FIG. 6 is a block diagram showing an example of such a conventional device. In Figure 6, V _H is a high level power supply terminal, V _L is a low level power supply terminal, and a switch circuit is connected between these power supply terminals V _H and V _L.
SWa and SWb are connected in series. Ta is an input terminal for a digital pattern signal represented by "1" and "0", and Tb is an input terminal for a control signal for controlling tri-state operation. input terminal
Ta is connected to one input terminal of the gate Ga via the inverter INV and directly connected to one input terminal of the gate Gb, and the input terminal Tb is directly connected to the other input terminal of the gate Ga and the gate Gb is connected to the other input terminal of
The output signals of these gates Ga and Gb are from a switch circuit.
This is used as the opening/closing control signal for SWa and SWb, and the output signal of gate Ga is the switch circuit.
The output signal of the gate Gb is applied to the switch circuit SWb. switch circuit
A digital signal output terminal To of the device is connected to the connection point between SWa and SWb via an output resistor Ro.

In such a configuration, the switch circuit SWa
When switch circuit SWa is on and SWb is off, a high-level signal is output, when switch circuit SWa is off and SWb is on, a low-level signal is output, and when both switch circuits SWa and SWb are off, the output is becomes high impedance.

However, according to the configuration shown in FIG. 6, it is necessary to use high-speed elements with relatively high breakdown voltage as the switch circuits SWa and SWb, which increases the cost. Furthermore, in order to maintain the output circuit, a separate protection circuit must be provided, which further increases costs.

Therefore, as a device to solve these drawbacks, current switches connected in series via digital signal output terminals are driven according to the output level control signal, and a diode is connected to the connection point of these current switches. Some are configured to apply an output level setting signal.

FIG. 7 is a block diagram showing an example of such a device. In Figure 7, HL is a high-level setting power supply that supplies a high-level signal to the DC level at terminal _VH , and IS ₁ is a current in three states of 0, I, and 2I depending on the control signal applied from control circuit CL _1. The first current source IS ₂ is a current switch that outputs current in three states of 0, -I, and -2I according to the control signal applied from the control circuit CL ₂ . a second current source configured;
LL is a low level setting power supply that provides a low level signal at a DC level to the terminal _VL . _D1 is a first diode whose anode is connected to the output terminal of the first current source _IS1 and whose cathode is connected to the output terminal of the high level setting power supply HL, and _D2 is the first diode whose anode is connected to the output terminal of the first current source IS1.
A second diode whose cathode is connected to the output terminal of the current source IS ₁ is connected to the output terminal To of the digital signal of the device, and D ₃ has an anode connected to the output terminal To of the digital signal of the device and whose cathode is connected to the output terminal To of the digital signal of the device. The third current source IS 2 connected to the output terminal of IS ₂ .
The diode _D4 is a fourth diode whose anode is connected to the low level setting power supply LL and whose cathode is connected to the second current source _IS2 . Note that the diodes D ₁ and D ₂ and the diodes D ₃ and D ₄ are paired diodes.

FIG. 8 is a circuit diagram showing a specific example of the main part of FIG. 7. The first current source IS ₁ includes transistors Q ₁ ,
The first current switch CSa consists of transistors Q ₂ and is turned on and off by the control signal applied from the control circuit CL ₁ , and the first current switch CSa consists of transistors Q ₃ and Q ₄ and is turned on by the control signal applied from the control circuit CL ₁ . , a second current switch controlled off
It consists of CSb and cascode transistor _Q5 . On the other hand, the second current source IS ₂ includes a third current switch CSc, which is composed of transistors Q ₆ and Q ₇ and is controlled on and off by a control signal applied from the control circuit CL ₂ , and transistors Q ₈ ,
A fourth current switch CSd and a cascode transistor Q ₁₀ are configured of Q ₉ and are controlled on and off by a control signal applied from the control circuit CL ₂ .
It consists of In addition, each current switch
The currents Ia to Id having the same current value I are outputted from CSa to CSd, respectively.

In such a configuration, each control circuit CL ₁ ,
CL ₂ outputs a control signal that controls each current switch CSa to CSd to be in the on or off state as shown in FIG. 9 depending on the state of the output. When the output is at high level, the current switch CSa and
Since CSb is turned on, the discharge side current becomes 2I, current switch CSc is turned off, and CSd
is turned on, the suction side current becomes I, and the output level increases due to the difference I between these. Then, when the output level approaches _VH , the diode _D1 is turned on, and the difference flows into the high level setting power supply HL via the diode _D1 . When there is no load, the currents flowing through the diodes D ₁ and D ₂ are equal, and since the characteristics of the diodes D ₁ and D ₂ are equal, the output level To becomes V _H. When the output is at low level, current switch CSa turns off and CSb turns on, so the discharge side current becomes I, and current switches Csc and CSd turn on, so the suction side current becomes 2I. Therefore, the output level decreases due to the difference I between them. Then, when the output level approaches V _L , diode _D4 is turned on, and the difference flows from low level setting power supply LL via diode _D4 . When there is no load, the currents flowing through the diodes D ₃ and D ₄ are equal, and since the characteristics of the diodes D ₃ and D ₄ are the same, the output level V ₀ becomes V _L , and the output level is the same as that of the diode D ₄
Therefore, it will be clamped to the V _L level.
Current switch in high impedance state
CSa to CSd are all turned off and the output becomes high impedance.

With this configuration, the output rise time and fall time are determined by the charging time of the output capacitor _CL . Here, since the slew rate (SR) is determined by I/C _L , high speed can be improved by increasing the output current of the current source, and since the maximum output current only flows I, essentially Since it has a current limiter function, the output is ensured.

(Problem to be solved by the invention) However, according to such a configuration, the slew rate (hereinafter referred to as _SR ) is 1/2 of the maximum output current 2I, that is, I SR=I/C _L At this time, the remaining I is not involved in CR and is wasted, resulting in the problem of low speed efficiency with respect to power consumption.

The present invention has been made with attention to these points, and improves SR by increasing the proportion of the current involved in SR among the maximum current of the output stage, and as a result, the output signal The purpose is to improve the rise and fall times of

(Means for Solving the Problems) The present invention that achieves the above object has three output currents of 0, mI, and (m+n)I (where n>m).
A current source _IH that can set two states, and a first switching diode circuit in which n diodes are connected in parallel, both anodes are connected to the _IH , and cathodes are each connected to a high level setting power supply. , a second switching diode circuit in which m diodes are connected in parallel, the anode side is connected to the above-mentioned _IH , the cathode side is connected to the output terminal, and the output current is in three states: 0, -mI, -(m+n)I. A current source _{I L} that can be set to , and a fourth switching diode circuit whose anode side is connected to the low level setting power supply and whose cathode side is connected to the current source I _L respectively, and in the high level state, I _H = (m + n) I, I _L =
−mI, and in the low level state, I _H = mI, I _L = −(m
+n) I, and in high impedance state I _H =
This is characterized in that I _L =0.

(Example) Hereinafter, it will be explained in detail using the drawings.

FIG. 1 is a circuit diagram showing the operating principle of the present invention. In Figure 1, _IH has an output current of 0, mI,
(m+n)I (where I is any current value, and n
>m) is a current source that can set three states,
It has two current sources I _A and I _B that can be turned on and off. I _L is 3 where the output current is 0, -mI, -(m+n)I
It is a current source that can set two states, and has two current sources I _C and _ID that can be turned on and off. _SD1 is the first switching diode circuit in which n diodes D _A1 to D _Ao are connected in parallel.The anode side is connected to the current source _IH , and the cathode side is connected to the power supply _C1 for setting the high level. There is. SD ₂ is a second diode with n diodes D _B1 to D _Bn connected in parallel.
This is a switching diode circuit whose anode side is connected to the current source _IH and the cathode side is connected to the output terminal _VO . SD ₃ is a third switching diode circuit, in which m diodes D _C1 to D _Cn are connected in parallel, and the anode side is connected to the output terminal _VO .
The cathode side is connected to the current source _IL . SD ₄ is a fourth switching diode circuit, in which n diodes D _D1 to D _Do are connected in parallel, and the anode side is connected to the power supply C ₂ for setting the low level.
The cathode side is connected to the current source _IL . Note that high level and low level signals are V _H and V _H respectively.
A DC level is applied to the terminal.

The current flowing through I _A of current source I _H is mI, the current flowing through I _B is nI, and the current flowing through I _C of current source I _L is −
The current flowing through mI and _ID is −nI.

In the above configuration, three states of H (high level), L (low level), and HZ (high impedance) can be set by controlling I _A to _ID .

Figure 2 is a simplified circuit diagram of Figure 1 showing a high-level output state (load current is assumed to be 0). In this state, all current sources I _A to I _D except I _D are turn on.

As a result, I _H = (m + n) I I _L = -mI, and the difference between I _H and I _L , that is, the current nI, charges the capacitive component C _L of the load until V _O rises and V _O = V _H. do. After charging, SD ₁ changes to on state and the current of nI is
flows into current source C ₁ through SD ₁ . At this time, n
The total amount of current flowing through the diodes _SD1 is nI, m
Since the total amount of current flowing through each diode SD ₂ is mI, the current per diode is equal, and the forward voltage VD _A =VD _B. Therefore the output voltage V _O
is kept equal to the high level setting voltage _VH .

Also, in the low level state, among the current sources I _A to I _D
Turn on all current sources except I _B.

As a result, I _H = mI I _L = -(m+n)I, and the difference between I _H and I _L , that is, the current -nI charges the capacitive component C _L of the load until V _O falls and V _O = V _H. do. After charging, SD ₄ turns on and a current of −nI flows into current source C ₂ through SD ₄ . At this time,
The total amount of current flowing through n diodes SD ₄ is −
nI, the total amount of current flowing through the m diodes _SD3 is -mI, so the current per diode is equal, and the forward voltage VD _C =VD _D. Therefore, the output voltage V _O is kept equal to the low level setting voltage V _L .

In the HZ (high impedance) state, the current source I _A ~ I _D
And SD ₁ to _{SD 4} are turned off and the output becomes high impedance.

FIG. 3 is a diagram showing the operating states of current sources I _A to _ID and SD ₁ to _{SD 4} when outputting high level, low level, and high impedance.

According to the above circuit, the maximum current of current sources I _H and I _L
Imax{=((m+n)・I}, where nI is nI/C _L =
Since it is involved in SR (slew rate) as {n/(m+n)·Imax}/ _CL , the efficiency increases as n becomes larger compared to m.

Here, when the maximum output current of I _H and I _L = 50 mA, the capacitive load C _L = 20 pF, m = 1 n = 9, compare the SR of the conventional circuit shown in Fig. 8 and the circuit of the present invention. Then, (a) For the conventional example SR=1/2・50mA/20pF =1.25V/ns (b) For the present invention SR=nI/C _L = {n/(m+n)・Imax}/C _L = 9/(1+9)・50mA/20pF = 2.25V/ns, so even if the maximum output currents Imax of I _H and I _L are equal,
SR increases by 80%.

Also, the maximum output current I _O max that can be sourced from this circuit to the load when the output is high level (V _O = V _L ), and the maximum output current I O max that can be sourced to the load when the output is low level (V _O = V _L ). The maximum current −I _O max that can be sunk into this circuit is I _O maxnI=n/(m+n)・Imax, and the larger n compared to m, the closer it can be to Imax, and the larger the value can do.

Here, when the maximum output current of I _H and I _L = 50 mA m = 1 n = 9, comparing I _O max between the conventional circuit shown in Fig. 8 and the circuit of the present invention, (a) In the case of the conventional example, I _O max1/2・Imax = 1/2・50mA=25mA (b) In the case of the present invention, I _O maxnI=n/(m+n)・Imax =9/(1+9)・50mA=45mA, and Imax is Even if they are equal, it will improve by 80%.

Also, the maximum output voltage of a low impedance load is determined by its H side level and L side level as V _OH max,
If V _OL max is V _OH max - V _T = | V _OL max - V _T | I _O max・R _O = n/(m+n)・Imax・R _O where R _O = load resistance V _T = termination of R _O voltage. Therefore, the larger n is made compared to m, the larger V _OH max and V _OL max can be made.

Here, maximum output current of I _H and I _L = 50 mA m = 1 n = 9 Load resistance R _O = 50 Ω, (a) For conventional example 1/2・Imax・R _O = 1/2・50 mA・50Ω=1.25V (b) In the case of the present invention, n/(m+n)・Imax・R _O =9/(1+9)・50mA・50Ω=2.25V, which increases the maximum output voltage by 80% when using a low impedance load. .

FIG. 4 shows another embodiment, and is a simplified diagram of FIG. 1, similar to FIG. 2. In this example, the current source I _H is a current source I _E that always flows a constant current of (m+n)I, and two current sources I _A ′ (=
−mI), I _B ′ (=−nI), and the current source I _L is a current source I _F that always flows a constant current of −(m+n)I, and two current sources I _C ′ (= mI), I _D ′
(=nI).

Even in the above configuration, the output current is 0, mI, (m+
n) I (where n>m) can be set, and as shown in Fig. 5, the current source I _A '~
By controlling _ID ' and _SD1 to _SD4 , high level, low level, and high impedance output states can be set.

Note that instead of connecting m and n diodes, diodes having the same forward voltage when mI and nI currents flow may be used. Such a diode can be obtained, for example, by setting the junction area to n:m and making the current density equal.

<Effects of the Invention> As specifically explained above in conjunction with the embodiments, according to the present invention, by increasing the maximum current of the output stage and the proportion of the current involved in SR, the SR
As a result, the rise time and fall time of the output signal can be shortened.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
The figure is a simplified circuit diagram of the high level output state of Figure 1. Figures 3 and 5 are the current sources I _A to I _D at high level, low level, and high impedance output.
₄ is _a circuit diagram showing another embodiment, FIGS. 6 and 7 are block diagrams showing an example of a conventional device, and FIG. 8 is a circuit diagram showing an example of a conventional device. A circuit diagram showing a specific example of the main part of the figure, FIG.
It is an explanatory diagram of the operating state of the figure. I _H , I _L ... Current source, SD ₁ - SD ₄ ... Switching diode circuit, C ₁ ... High level setting power supply, C ₂ ... Low level setting power supply, D _A1 - D _Ao , D _B1
~D _Bn , D _C1 ~ D _Cn , D _d1 ~ D _do ...Diode.

Claims (1)

[Claims] 1 Output current is 0, mI, (m+n)I (however,
A current source _IH that can set three states (n>m),
A first switching circuit in which n diodes are connected in parallel, the anode sides of which are connected to the above-mentioned _IH , and the cathode sides of which are each connected to the high level setting power supply.
A diode circuit, a second switching diode circuit in which m diodes are connected in parallel, the anode side is connected to the above-mentioned _IH , and the cathode side is connected to the output terminal, and the output current is 0, -mI, -(m+n)I. 3
A current source I _L that can set two states, m diodes are connected in parallel, and a third switching diode whose anode is connected to the output terminal and the cathode side is both connected to the I _L , and n diodes are connected in parallel. and a fourth switching diode whose anode side is connected to the low level setting power supply and whose cathode side is connected to the current source I _L , respectively, and in the high level state I _H = (m + n) I, I _L =
−mI, and in low level state I _L = mI, I _L = −
(m+n)I, and in high impedance state
A digital signal generation circuit characterized in that I _H =I _L =0.