JPH0584564B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a data writing circuit for a floppy disk device or the like.

(Prior art) In a normal data write circuit, as shown in Fig. 5, when the write gate is opened and write data is sent, the write current of the magnetic head is changed at the timing of the falling edge of this data. data is written to the recording medium. When the write gate closes, the write current for the magnetic head is turned off.

Further, in the known magnetic head magnetization prevention circuit, as shown in FIG. 6 in the data write circuit, after the write gate is closed, the write current is attenuated and erased with a constant time constant in accordance with the falling edge of data. However, several bits of write data are required even after the write gate is closed.

(Problem to be solved by the invention) In a normal data write circuit, the magnetic head is magnetized in the direction of the final write current after data is written due to the core material and shape of the magnetic head.
The magnetic properties of the magnetic head deteriorate and the asymmetry of the recording waveform worsens. Asymmetry of recorded waveform
As shown in Fig. 7, AS is the absolute value of the difference between the length T ₁ from the positive peak to the negative peak of the recording waveform and the length T ₂ from the negative peak to the positive peak |T ₁ ~ _{T 2} | When the residual magnetization of the magnetic head increases, the peak of the recording waveform shifts from the normal solid line in FIG. 7 to the dotted line in FIG. 7, and the symmetry AS deteriorates. Moreover, the symmetry changes greatly with each write.

Further, the magnetic head magnetization prevention circuit has a restriction that several bits of write data must be continuous even after the write gate is closed.

(Means for Solving the Problems) The present invention provides a delay means for delaying a write gate, a means for conducting or cutting off a current-carrying path to a magnetic head by a write gate signal delayed by the delay means, and the above-mentioned. It has means for inverting the write current of the magnetic head based on the signal from the write gate, and means for switching the magnitude of the write current for the magnetic head based on the signal from the write gate.

(Function) The write gate signal is delayed by the delay means,
The delayed write gate signal turns on and off the current supply path to the magnetic head. Furthermore, the above means inverts the write current of the magnetic head based on the write gate signal, and switches the magnitude of the write current to the magnetic head based on the write gate signal.

(Embodiment) FIG. 1 shows an embodiment of the present invention, and FIG. 2 shows its timing chart. In Figure 1
HD is a magnetic head, Tr1 to Tr5 are transistors,
BS is bias power supply, NR1 and NR2 are NOR gates, FF is flip-flop, S is switch, N
is an inverter, DL is a counter or a well-known delay circuit consisting of a resistor, a capacitor, etc., D is a diode, R1 to R10 are resistors, and Vcc is a DC power supply. The write circuit of the magnetic head HD consists of transistors Tr4 and Tr5 and their drive transistor Tr.
A switching transistor Tr1 is connected to this write circuit via resistors R8 and R9 connected in parallel.
Resistor R9 is turned on by write gate signal WG.
An OFF switch S is installed, and the magnitude of the write current can be switched by turning the switch S on and off using a write gate signal WG. Write data signal WD is a NOR gate
The signal is input to flip-flop FF via NR1 and NR2, and based on the output of flip-flop FF, transistors Tr2 and Tr3 are switched and a write current flows. This write current is inverted in response to the fall of the write data signal WD, and the write current is reversed according to the fall of the write data signal WD.
When WD is at a low level, the flip-flop FF is inverted at the rise of the write data signal WD, and the write current is inverted. The write gate signal WG is passed through the delay circuit DL and the inverter N to the transistor Tr1.
For a while after the write gate signal WG turns off (high level), the transistor Tr1 is on and a current flows to the magnetic head HD.

Assuming that the write gate signal WG is turned on now,
The transistor Tr1 turns on after a delay of the time set by the delay circuit DL, and the magnetic head HD enters a write-enabled state in which a write current can flow. Note that the write data is written between the turn-on of the write gate signal WG and the turn-on of transistor Tr1.
WD will never be sent. When write data WD is sent in this writable state, flip-flop FF is inverted at the falling timing of this data WD, and transistors Tr2 to Tr5 are
is switched, the write current of the magnetic head HD is reversed, and data is recorded on the magnetic recording medium by the magnetic head HD. After that, when data recording is finished and the write gate signal WG is turned off, the flip-flop FF is inverted at this timing and the write current is inverted. At this time, switch S is turned off and write current Iw' flows only through resistor R8. This current Iw' is the write current when the switch S is on due to the write gate signal WG being on.
smaller than Iw. Also, the time Δt during which this current Iw′ flows
is set by delay circuit DL, typically 2μ~10S
degree. At the end of this writing, a current Iw' in the opposite direction to the writing current Iw flows, so that the residual magnetization of the magnetic head HD is kept small.

FIG. 3 is a timing chart of the relationship between the operation of the flip-flop FF and the energization of the magnetic head HD. To explain this relationship in detail, the flip-flop FF is the output signal of the NOR gate NR2.
When WD'' is input to the T terminal, both the non-inverted output and the inverted output are inverted at the fall of this signal WD''. When the first data WD'' is input to the T terminal of the flip-flop FF, the flip-flop FF is inverted at the falling edge, the Q output (non-inverted output) becomes high level, and the output (inverted output) becomes low level. Therefore, the transistor Tr3 is turned on, the transistor Tr2 is turned off, and the transistor Tr3 is turned on, and the transistor Tr2 is turned off.
5 is turned off, transistor Tr4 is turned on, and the write current flows to the magnetic head HD through transistor Tr4. When the next data WD'' is input to the T terminal of the flip-flop FF, the flip-flop FF is inverted at the falling edge of the data, its Q output becomes low level, and the output becomes high level.Therefore, the transistor Tr3 is turned off. transistor
Tr2 is turned on, transistor Tr5 is turned on, transistor Tr4 is turned off, and the write current flows to the magnetic head HD through transistor Tr5.

In the above embodiment, as shown in FIG. 4, the asymmetry value became small, and the fluctuation in the number of times due to magnetization (the change in asymmetry when the current was applied many times) became small and became almost constant.

(Effects of the Invention) As described above, according to the present invention, the write gate signal is delayed, the delayed write gate signal is used to conduct or cut off the conduction path to the magnetic head, and the write current of the magnetic head is controlled based on the write gate signal. Since the write current to the magnetic head is inverted and the magnitude of the write current to the magnetic head is switched based on the write gate signal, it is possible to prevent magnetization of the magnetic head due to the write current and prevent deterioration of the characteristics of the magnetic head. Asymmetry can be improved. Furthermore, there is no longer a restriction that several bits of write data must be written consecutively after the write gate signal is turned off. Furthermore, it is easy to design and can be realized with a small number of parts.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
3 and 3 are timing charts of the same embodiment,
Figure 4 is an asymmetry characteristic diagram of the same example.
6 and 6 are timing charts of the conventional circuit,
FIG. 7 is a waveform diagram for explaining a conventional circuit. HD...magnetic head, Tr1 to Tr5...transistor, FF...flip-flop, S...switch, DL...delay circuit.

Claims (1)

[Claims] 1. Delay means for delaying the write gate signal;
means for conducting or cutting off the current conduction path to the magnetic head by the write gate signal delayed by the delay means; means for reversing the write current of the magnetic head based on the signal of the write gate; and the write gate. and means for switching the magnitude of the write current to the magnetic head based on the signal.