JPH0585990B2 - - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a dynamic type semiconductor memory device that includes a one-transistor, one-capacitor type memory cell, and has a counter electrode of the capacitor at an intermediate potential between a power supply voltage and a ground potential.

Prior Art and Problems The memory cell of a dynamic semiconductor memory device is generally of the one-transistor, one-capacitor type, and the capacitor is formed by using a dielectric film or a dielectric film on the surface of the semiconductor substrate.
It is configured as a MOS type in which the metal or polycrystalline silicon on the insulating film is used as one electrode, and the semiconductor substrate below it is used as the other electrode. A device in which the lower p-type semiconductor substrate is n-inverted and used as the other electrode is widely used. Also, the voltage applied to the counter electrode does not have to be Vcc; if the substrate is made n-type by diffusing n-type impurities, the counter electrode potential can be an intermediate potential between the power supply voltage Vcc and the ground potential of 0 volts, or the ground potential itself. .

As memories become larger and larger, memory cells tend to become smaller and smaller. Miniaturization requires uniform scaling of all parts, and as a result, insulating films and the like must also be made thinner, which poses problems in terms of withstand voltage. That is, when Vcc is applied to the opposing electrode of the capacitor, and the other electrode, that is, the semiconductor substrate, stores or does not store charge at Vcc (data "1" and "0" are stored), the potential of the other electrode becomes Vcc or Vss. (0 volt), Vcc is applied to the capacitor's insulating film at most. This produces a strong electric field when the film is thin,
There is a risk of dielectric breakdown of the insulating film. Therefore, it has been considered to apply an intermediate potential, for example, Vcc/2, to the counter electrode. In this case, the other electrode is Vcc,
For either Vss, the potential difference with the counter electrode is Vcc/2
This is half of the above value, and the problem of dielectric breakdown is greatly reduced. The main parts of such a dynamic memory are shown in FIG.

In FIG. 1, WL is a word line, BL is a bit line pair, and SA is a sense amplifier MC, which is a memory cell consisting of a MOS transistor _Q1 and a capacitor _C1 . Voltage divider circuit VD consists of two resistors with equal resistance value.
R ₁ and R ₂ are connected in series between Vcc and Vss, and this intermediate connection point is connected to the cell counter electrode OP.
The counter electrode OP is common to many memory cells,
In the figure, it is shown in a wiring form similar to a word line.
E is the other electrode, which is the transistor Q ₁
Sometimes it is integrated with the source. The connection between this other electrode E and the source of the transistor _Q1 is indicated by a node _N1 .

By the way, the counter electrode OP has a large area and intersects with the bit line BL, etc., and has large stray capacitances C _p1 , C _{p2 ,} etc. between them, and as a result, capacitive coupling occurs due to changes in the potential of those signal lines. As a result, potential fluctuations occur. Therefore, the potential of the counter electrode OP must always be adjusted correctly.
To maintain Vcc/2, these stray capacitances and voltage divider circuits are required.
The time constant with the resistance in VD becomes a problem. Of course, the smaller this time constant is, the better. However, the resistance R ₁ ,
Since the current flowing through R ₂ continues to flow as long as the power is applied to the memory chip, reducing R ₁ and R ₂ constantly increases power consumption. Therefore, resistors R ₁ and R ₂ must have high resistance to avoid an increase in power consumption. However, the values of resistance R ₁ and R ₂ are large,
If the counter electrode OP cannot be charged or discharged immediately, the counter potential will fluctuate due to coupling with the bit line etc. due to the parasitic capacitance. Although the details of this variation are quite complicated, they can be summarized as follows. That is, in the memory, the sense amplifier SA operates to set one of the bit lines BL to H (high) level or
There is an active state in which Vcc and the other are set to L (low) level, that is, Vss, and a standby state in which the sense amplifier SA does not operate and the bit line BL is charged to the H level, Vcc. is ignored due to the time constant, the counter electrode OP
When the former is active, the potential is lower than when the latter is standby by the amount of variation due to capacitive coupling of one of the parasitic capacitances C _p1 and C _p2 .

When active and standby are repeated, the counter electrode potential fluctuates between the above two values, but in reality, this is affected by charging and discharging of parasitic capacitance. In other words, if OP = Vcc/2, C _p2 is charged with a polarity with the OP side being + and the OP side being -, and the voltage of that polarity is
It has Vcc/2. In this state, if = Vcc
OP is pushed up by the voltage of C _p2 , and at the same time charges are charged and discharged in the parasitic capacitances C _p1 and C _p2 . If the potential of the pushed-up OP is Vcc/2+ΔV _H , the voltages of C _p1 and C _p2 are Vcc/2−ΔV _H , and the polarity of the charged charge of C _p2 is opposite to that before. In this state, Vss is again
When this happens, OP is pushed down by C _p2 and at the same time the parasitic capacitances C _p1 and C _p2 are charged and discharged. If the potential of this pushed down OP is Vcc/2-ΔV _L , the voltage of C _p1 is Vcc/2+ΔV _L , the voltage of C _p2 is Vcc/2-ΔV _L , and the polarity returns to the initial state. If the standby period and active period are the same length, ΔV _H is ΔV _L
be equivalent to.

In this way, the potential of the counter electrode OP changes between Vcc/2 + ΔV _H and Vcc/2 - ΔV _L , but this is a case where active and standby are repeated in a short time, and the active period or standby period is When the length becomes longer, OP becomes Vcc/
2 is given, so it will settle down to this Vcc/2. When the voltage has settled down to Vcc/2, for example, what had been on standby becomes active and BL = H, = L, a depression occurs due to C _p2 , and the potential of OP becomes Vcc/2 - (ΔV _L +ΔV _H ). In the above description, this is set to be Vcc/2-ΔV _L , but this is because the previous state was Vcc/2+ΔV _H , and the fluctuation range is the same, ΔV _L +ΔV _H.
The same thing happens when what has been active until now changes to standby; in this case, it is pushed up to Vcc/2 + ΔV _H + ΔV _L.

Such fluctuations in the potential of OP similarly occur when the ratio between the active period and the standby period changes over a relatively long period of time. As mentioned above, applying the intermediate potential Vcc/2 to the counter electrode is to prevent insulation deterioration of the insulating film, but if the potential of the counter electrode changes significantly as described above, the effect of adopting the intermediate potential is poor. will be reduced. Also, the potential of the opposing electrode OP affects the potential of the other electrode E, and hence the node _N1 , and if the potential of the OP drops significantly,
The potential of _N1 also drops significantly, causing the sense amplifier SA to malfunction, and the data "1" storage state may be erroneously determined to be the data "0" storage state.

Therefore, the inventor of the present invention considered switching the output of the voltage divider circuit VD between active and standby states, and previously proposed this (Japanese Patent Application No. 57-211146). 1st
The resistor R ₃ and MOS transistor Q ₂ shown in the figure turn on and off the transistor Q ₂ using the clock φ _A , thereby changing the output level of the voltage dividing circuit between H and L. That is, if the clock φ _A is set to H during active and L during standby, transistor Q ₂ turns on during active, connects resistor R ₂ and resistor R ₃ in parallel, and lowers the output of the voltage divider circuit, and during standby, transistor Q ₂ turns on. Turn off to disconnect resistor _R3 and increase the output of the voltage divider circuit. The average potential of OP is
To set it to Vcc/2, the resistance values of R ₁ and R ₂ are made different. In other words, the H level output of the voltage divider circuit VD is
Vcc/2+ΔV _H , L level output is selected to be Vcc/2−ΔV _L , even if the active period and standby period are long, the potential settling of the counter electrode and the output level of the voltage divider circuit are the same, so there is no change. There is no significant fluctuation in the potential of the counter electrode when active or standby is restarted.

However, this proposed circuit also has drawbacks.
That is, in order to reduce power consumption as mentioned above,
Resistors R ₁ and R ₂ have high resistance, and resistor R ₃ also has high resistance, but high resistance creates parasitic capacitance and a large time constant. In particular, when MOS transistor Q ₂ is used to insert and remove resistor R ₃ , it has large source and drain capacitances, so even if transistor Q ₂ is turned off, the potential at node N ₂ does not rise immediately. , the state will be the same as if the resistor R ₃ was connected. FIG. 2 is a diagram for explaining this, and a curve N ₂ shows a change in the potential of the node N ₂ . Similarly, the curve φ _A shows the potential change of the clock φ _A and the curve OP shows the potential change of the counter electrode OP. is a row address strobe signal, which is applied from the outside.When it is at L level, the sense amplifier SA of the memory chip is active, and when it is at H level, it is in standby. As mentioned above, when the bit line BL becomes active, one becomes H and the other becomes L, and the potential of the counter electrode OP decreases.
When in standby, both bit lines BL and BL become H, and the potential of the opposing electrode rises. The clock φ _A is set to H and L in accordance with the potential change of the counter electrode OP,
Change the output level of the voltage divider circuit VD. That is, in the active state, φ _A is set to H and transistor Q ₂ is turned on.
Drop node N ₂ to Vss and connect resistor R ₃ in parallel with R ₂ . Since this can be done immediately, the output of the voltage divider circuit quickly becomes L level. However, even if the clock φ _A is set to L during standby and the transistor Q ₂ is turned off, the potential of the node N ₂ does not rise as shown in the figure. In order to raise the potential of node _N2 , it is necessary to charge the node through high resistances _R1 and _R3 , but this takes time. If the potential of node _N2 does not rise, this is the same as connecting resistor _R3 to resistor _R2 in parallel, and the output of voltage divider circuit VD is at L level. In this state, the potential of OP is low,
C _p1 and C _p2 are charged to a high voltage with the BL side set to +, and when they become active in this state and, for example, become Vss, OP is strongly pushed down, causing deterioration of the capacitor insulating film and misreading of stored data. There is a fear.

OBJECTS OF THE INVENTION The present invention aims to improve the above points and to make it possible to quickly switch the intermediate potential applied to the counter electrode between H and L.

Structure of the Invention The present invention includes a one-transistor, one-capacitor type dynamic memory cell consisting of a transistor and a capacitor having one electrode connected to the transistor, and the other electrode of the capacitor has a voltage lower than the power supply voltage. In the given semiconductor memory device, a voltage generating circuit capable of simultaneously outputting a first voltage higher than a substantially intermediate voltage of the power supply voltage by a predetermined value and a second voltage lower than the substantially intermediate voltage by a predetermined value; During standby, the first voltage is
The device is characterized by comprising a switching element that selectively switches and supplies the second voltage to the other electrode of the capacitor when it is active, which will be explained next with reference to embodiments.

Embodiment of the Invention FIG. 3 shows an embodiment of the invention, in which the same parts as in FIG. 1 are given the same reference numerals. In the present invention, the high resistance voltage divider circuit has two terminals that produce an H level output and an L level output, and the opposing electrode OP is selectively connected to one of these two terminals by switching transistors Q ₃ and Q ₄ . Resistors R ₁ and R ₂ are the H level output circuit, resistors R ₄ and R ₃ are the L level output circuit, and N ₃ and N ₄ are the output ends thereof. Clock φ _A
When is at H level, transistor _Q4 is turned on and applies L level output O _L to the opposite electrode OP. Also, when clock _A , which has the opposite phase to clock φA _, is at H level, transistor _Q3 is turned on, and the opposite electrode OP is connected to H level.
Add level output O _H. As mentioned above, the output O _H is selected to be 1/2Vcc + ΔV _H , and the output O _L is selected to be 1/2Vcc - ΔV _L , that is, the potentials of the H and L types of the opposing electrode OP when the memory is repeatedly active and standby. choose. In this way, even if the active and standby periods become longer, there is no change in the potential of the counter electrode. This voltage divider circuit always generates two voltages, H and L, at its output terminals N ₃ and N ₄ , and one of them is selected by switching elements Q ₃ and Q ₄ and the opposite electrode is OP.
Since the voltage application is performed immediately, there is no problem that the desired potential cannot be reached immediately due to a time constant as in the circuit shown in FIG.

FIG. 4 is a diagram similar to FIG. 2, but in addition to the clock _φA , a clock _A is also shown in FIG.
Although RAS is not shown, it also goes to L level, the potential of the counter electrode OP decreases, and RAS goes to H level.
As the voltage increases, the potential of the counter electrode OP increases. Clock φ _A
Start up after OP goes down, and down before OP goes up. Similarly, clock _A starts up after OP goes up, and goes down before OP goes down. During the potential change of OP, both φ _A and _A are L, and the transistor
Q ₃ and Q ₄ are off and the counter electrode OP is in a floating state.

The reason why the counter electrode OP is separated from the voltage dividing circuit while the potential of the counter electrode OP is changing is as follows. That is, the voltage becomes L, the sense amplifier operates, and the potential of OP drops, but this potential change is not rapid. So OP
If φ _A is raised and Q ₄ is turned on before it reaches 1/2 Vcc - ΔV _L , that is, the potential L of O _L , the current will flow from OP to Vss through Q ₄ , N ₄ , and R ₃ for a short time. flows out. Since the resistance of R ₃ is also high, the amount of leakage at one time is small, but if this phenomenon is repeated many times, the potential of OP will decrease. Also, when _φA falls, a similar problem will occur unless _φA is lowered and _Q4 is completely turned off before OP rises. This problem also applies to _A. As the amount of current flowing out is different when the OP potential falls and rises, as the active and standby states are repeated, the OP potential changes to a potential different from H and L depending on the repetition cycle. I will go there. In order to avoid this, as shown in Figure 4, φ ₄ is applied only when the potential of OP is completely O _L or O _H.
Alternatively, this can be done by turning φ ₃ ON and turning both Q ₄ and Q ₃ OFF when the OP potential changes.

FIG. 5 shows another embodiment of the invention. _R5 ～ _R7
are three high resistances connected in series between the power supplies Vcc and Vss. The counter electrode OP connects to nodes N ₅ and N ₆ , that is, resistor R ₅ via switching transistors Q ₃ and Q ₄ .
Connected to the series connection point of R ₆ and the series connection point of resistors R ₆ and R ₇ . Clock _A and φ _A are applied to the gates of transistors Q ₃ and Q ₄ , and nodes N ₅ and N ₆ are at H,
Since the L level outputs O _H and O _L are generated (the resistance values of R ₅ to R ₇ are selected accordingly), the same operation as in FIG. 3 is performed. In terms of power consumption, Figure 5 ranks third.
This is more advantageous than the figure. It goes without saying that the resistors R ₁ to _{R 7} may be composed of transistors or the like in addition to diffused resistors.

Effects of the Invention As explained above, in the present invention, the memory repeatedly activates and standsby the intermediate potential applied to the cell capacitor counter electrode by the high resistance voltage divider circuit, and as a result, the counter electrode becomes The voltage dividing circuit always outputs the two potentials at the same time, and one of them is selected and applied to the opposite electrode, so that the voltage is applied at the same time as the selection. The voltage application can be applied to the counter electrode without delaying the voltage application due to time constants associated with high resistance circuits.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram explaining the proposed method, FIG. 2 is a waveform diagram explaining its operation, FIG. 3 is a circuit diagram showing an embodiment of the present invention, FIG. 4 is a diagram explaining its operation, and FIG.
The figure shows a circuit showing another embodiment. In the drawing, MC is the memory cell, Q ₁ is its transistor, C ₁ is the capacitor, OP is the counter electrode, C _p1 ,
C _p2 is a parasitic capacitance, VD is a voltage dividing circuit, N ₃ and M ₄ are its output terminals, Vcc is a power supply voltage, and Vss is a ground potential.

Claims (1)

[Claims] A one-transistor, one-capacitor type dynamic memory cell consisting of a transistor and a capacitor having one electrode connected to the transistor, and the other electrode of the capacitor is connected to a voltage lower than the power supply voltage. In the provided semiconductor memory device, a voltage generating circuit capable of simultaneously outputting a first voltage higher by a predetermined value than a substantially intermediate voltage of the power supply voltage and a second voltage lower by a predetermined value than the substantially intermediate voltage; A semiconductor memory device comprising a switching element that selectively switches and supplies the first voltage to the other electrode of the capacitor during standby and the second voltage during active.