JPH05869B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for forming a gate oxide film for a MOS type semiconductor device, and is particularly used for a method for forming a gate oxide film for a radiation-resistant MOS type semiconductor device. .

[Technical background of the invention and its problems]

Conventionally, when forming a gate oxide film for a MOS type semiconductor device, silicon is oxidized to obtain a desired film thickness. Furthermore, the thickness of the film etched by ordinary chemical treatment after the formation of the gate oxide film and before the formation of the gate electrode was at most 10 to 20 Å since the purpose of this was to remove natural oxide.

On the other hand, when a substance is irradiated with radiation such as gamma rays, the substance is ionized, producing positive charges and electrons. If the material is an insulator such as a gate oxide film, electrons have high mobility and therefore flow out to the outside quickly, but some of the positive charges are semi-permanently captured within the insulator. Regarding the capture, the microscopic structure of the insulator becomes a problem, and the places where the structure is disordered become the centers of positive charge capture.

Due to the trapping of positive charges in the gate oxide film due to radiation irradiation, the gate threshold voltage, VT, of the MOS type semiconductor device shifts in the negative direction. The smaller the gate oxide film thickness, the smaller the shift, which is advantageous for a radiation-resistant device, but if the gate oxide film thickness is 300Å,
Below this, more trapping centers exist near the Si-SiO ₂ interface due to structural disorder. Therefore, the threshold voltage VT shift is larger than the expected threshold voltage VT shift, which has the disadvantage that a large VT margin of the MOS device must be provided.

[Purpose of the invention]

The present invention has been made in view of the above points, and the threshold voltage VT caused by a radiation device of a MOS type semiconductor device is
It is an object of the present invention to provide a method for forming a gate insulating film of a MOS type semiconductor device, which can suppress fluctuations in .

[Summary of the invention]

The outline of the present invention is to first form a silicon oxide film with a thickness of 400 Å or more in order to reduce the positive charge trapping center near the Si-SiO ₂ interface and move the center away from Si when forming a silicon oxide film with a thickness of 300 Å or less. , and then etching to reduce the thickness of this oxide film to 300 Å or less.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail according to examples.
Figure 1 shows SOS (Silicon), a promising radiation-resistant element.
FIG. After forming the device region 11 on the sapphire 10 as shown in FIG. 1a, hydrogen combustion oxidation is performed at 850° C. for 27 minutes as shown in FIG. 1b, resulting in the growth of SiO ₂ 12 of 400 Å. Next, as shown in Figure 1c, this was added to 1% HF.
When etched with an aqueous solution for 3 minutes, the silicon oxide film 13 is etched by about 120 Å and has a thickness of 280 Å.
Furthermore, as shown in Figure 1d, by impurity implantation,
By forming the gate electrode 14 after performing VT control, a MOS type half-dehyde device that is resistant to radiation can be obtained.

Although this embodiment describes an SOS structure, it can also be applied to silicon wafers.
Also, instead of hydrogen combustion oxidation, wet oxidation or
Dry oxidation at about 1000°C may also be used. The concentration of the HF aqueous solution may be any percentage. Alternatively, a material capable of etching SiO ₂ such as an aqueous ammonium fluoride solution may be used.

When a MOS transistor is irradiated with radiation,
Positive charges are captured in the gate insulating film, and as a result, the threshold voltage VT of the transistor is
Both NMOS shift to the negative side. FIG. 2 shows an example of the shift in transistor characteristics. If the shift is large, the circuit will not operate beyond the VT margin during LSI design.

Positive charge trapping in the gate oxide film actually has a certain distribution, but IEEE Transactions on
Nuclear Science, vol.NS−25, NO6.
December1978, “A SIMPLE MODEL FOR
PREDICTING RADIATION EFFECTS IN
According to the model described in "MOS DEVICES," it is assumed that all charges exist at the center of gravity of the distribution as shown in Figure 3. Here, Q ₂ and Qm are the captured charges induced by radiation irradiation, respectively. Charge Qox
This is the charge induced on the Si side and the gate side to support this. According to this model, the threshold voltage shift ΔVT due to radiation irradiation is expressed by the following equation.

ΔVT=qNoxx ₂ /εoxεo Here, εox・εo is the dielectric constant q of SiO ₂ , the elementary charge, Nox is the number of positive charges captured by radiation irradiation, and x ₁ is the distance from the Si-SiO ₂ interface to the capture center. , _x2 is the distance from the capture center to the gate electrode.

When irradiating with a positive voltage applied, Nox is proportional to x ₂ , and if the proportionality constant is C, Nox = Cx ^2/2 , and ΔVT is: ΔVT = -qc/εox・εox ^2/2 = -qc/ εox・εo(Tox−x ₁ ) ² , (Tox is the gate oxide film thickness). When Tox is large enough, X ₁ becomes constant (~130 Å in our experiments) and ΔVT becomes a function of Tox squared. Figure 4 shows a log-log diagram of the relationship between Tox and ΔVT.

In Figure 4, the left is N-ch, the right is P-ch, o
The marks are as grown, and the x marks are those formed at 600 Å and then etched to 200 Å and 300 Å. When Tox is 400 Å or more, ΔVT becomes a function of the square of Tox. However, at Tox lower than that, the relationship deviates from the square relationship and becomes larger than the expected ΔVT (marked with a circle). This is because when Tox is small, there is no time to improve the disorder of the SiO ₂ structure near the Si-SiO ₂ interface, and the positive charge trapping center becomes more Si
It is expected to exist near the interface. Therefore, the figure shows the ΔVT (x mark) when a thermal oxide film of 600 Å is first formed and then etched to 300 Å. In N-ch, ΔVT decreases from 1.4V to 0.7V,
In P-ch, it can be reduced from 1.8V to 1.0V.

〔Effect of the invention〕

As explained above, according to the present invention, the MOS
In forming the gate oxide film of a type semiconductor device, first
By forming a silicon oxide film with a thickness of 400 Å or more and then removing it to a thickness of 300 Å or less, it is possible to provide a method for forming a gate insulating film of a MOS type semiconductor device with less fluctuation in threshold voltage.

[Brief explanation of the drawing]

FIG. 1 is a process sectional view showing an embodiment of the present invention;
Figure 2 is a diagram showing changes in transistor characteristics due to gamma ray irradiation, Figure 3 is a simplified diagram of positive charge capture in SiO ₂ , and Figure 4 is a logarithm of threshold shift ΔVT with respect to gate oxide film thickness and Tox. - a diagram represented by a logarithmic graph; In the figure, 10...Sapphire substrate, 11...Silicon element region, 12...Thick gate oxide film immediately after oxidation,
13... Thin oxide film after etching, 14...
...Gate electrode.

Claims (1)

[Claims] 1 When forming a silicon oxide film of 300 Å or less in the gate oxide film formation process of a MOS type semiconductor, a silicon thermal oxide film of 400 Å or more is formed and then removed to reduce the oxide film thickness to 300 Å.
A method for forming gate insulation of a MOS type semiconductor, characterized by the following steps.